Switch devicetree-rebasing to kernel.googlesource.com mirror

CI builds have been failing lately with:
Error: fatal: unable to access
'https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/':
Failed to connect to git.kernel.org port 443 after
134198 ms: Couldn't connect to server

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>

.gitmodules

@@ -4,9 +4,6 @@
 [submodule "edk2-non-osi"]
 	path = edk2-non-osi
 	url = https://github.com/tianocore/edk2-non-osi.git
-[submodule "edk2-platforms"]
-	path = edk2-platforms
-	url = https://github.com/tianocore/edk2-platforms.git
 [submodule "misc/rkbin"]
 	path = misc/rkbin
 	url = https://github.com/rockchip-linux/rkbin.git
@@ -16,4 +13,7 @@
 	branch = rk3588
 [submodule "devicetree/mainline/upstream"]
 	path = devicetree/mainline/upstream
-	url = https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
+	url = https://kernel.googlesource.com/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
+[submodule "edk2-platforms"]
+	path = edk2-platforms
+	url = https://github.com/tianocore/edk2-platforms.git

README.md

@@ -12,7 +12,7 @@ Platinum devices are considered to have the best overall support, based on facto
 - Device Tree and peripherals compatible with mainline Linux. [**Required**]
 - Active interest from the vendor in supporting their hardware.
 - Hardware design choices:
-  - If an Ethernet port is present, Realtek PCIe NIC (for netboot) or RK GMAC. [**Required**]
+  - If an Ethernet port is present, Realtek PCIe NIC or integrated GMAC. [**Required**]
   - SPI NOR flash for dedicated firmware storage. [Preferred]
 
 Bronze devices may have limitations such as:
@@ -69,7 +69,7 @@ Note that this list is subject to change at any time as devices gain better supp
 ### Mainline compatibility mode
 | OS | Version | Tested/supported hardware | Notes |
 | --- | --- | --- | --- |
-| Generic upstream Linux | Kernel 6.10 or newer.<br> Tested with:<br> - Ubuntu 24.10<br> - Fedora Workstation 41 | Platform and kernel version dependent, see [Collabora's RK3588 upstream status](https://gitlab.collabora.com/hardware-enablement/rockchip-3588/notes-for-rockchip-3588/-/blob/main/mainline-status.md). | * Kernels older than 6.13 lack HDMI output. To work around this, see: [Device Tree configuration](#device-tree-configuration). |
+| Generic upstream Linux | Kernel 6.10 or newer.<br> Tested with:<br> - Ubuntu 24.10<br> - Fedora Workstation 41<br> - Fedora Workstation Rawhide | Platform and kernel version dependent, see [Collabora's RK3588 upstream status](https://gitlab.collabora.com/hardware-enablement/rockchip-3588/notes-for-rockchip-3588/-/blob/main/mainline-status.md). | * Kernels older than 6.15 lack display output. To work around this, see: [Device Tree configuration](#device-tree-configuration). |
 
 > [!NOTE]
 > Mainline support is only available on [Platinum](#platinum) platforms.
@@ -87,11 +87,11 @@ Note that this list is subject to change at any time as devices gain better supp
 | PCIe 3.0 / 2.1                        | 🟢 Working     | |
 | SATA                                  | 🟢 Working     | |
 | SD/eMMC                               | 🟢 Working     | |
-| HDMI output                           | 🟡 Partial     | Single display with mode limited at 1080p 60 Hz |
-| DisplayPort output (USB-C)            | 🟡 Partial     | Mode fixed at 1080p 60 Hz, only works in one orientation of the Type-C port. Some displays may not work regardless. |
+| HDMI output                           | 🟢 Working     | |
+| DisplayPort output (USB-C)            | 🟡 Partial     | No hot-plug detect & EDID. Only works in one orientation of the Type-C port. Some displays may not work regardless. |
 | eDP output                            | 🟡 Partial     | Disabled, requires manual configuration depending on the platform and panel. |
 | DSI output                            | 🟢 Working     | Only enabled on Fydetab Duo. Requires manual configuration depending on the platform and panel. |
-| GMAC Ethernet                         | 🔴 Not working | Only brought-up for OS usage |
+| GMAC Ethernet                         | 🟢 Working     | |
 | Realtek PCIe Ethernet                 | 🟢 Working     | Some platforms don't have MAC addresses set, networking may not work in that case. |
 | Low-speed (GPIO/UART/I2C/SPI/PWM)     | 🟢 Working     | UART2 console available at 1500000 baud rate |
 | SPI NOR Flash                         | 🟢 Working     | |
@@ -109,7 +109,7 @@ Note that this list is subject to change at any time as devices gain better supp
 * Quality power supply that can provide at least 15 W. Depending on the peripherals you use, more may be needed.
 
   Note: on Mixtile Blade 3, a fixed voltage *higher than* 5V must be supplied. The board cannot power any external peripherals if the input voltage is just 5V. USB-PD negotiation is not supported by firmware.
-* HDMI or DisplayPort (USB-C) screen capable of at least 1080p 60Hz.
+* HDMI (preferred) or DisplayPort (USB-C) screen.
 * Optionally, if display is not available or for debugging purposes, an UART adapter capable of 1500000 baud rate (e.g. USB CH340, CP2104).
 
 ## 2. Download the firmware image
@@ -120,7 +120,7 @@ If your platform is not yet supported, using an image meant for another device i
 ## 3. Flash the firmware
 UEFI can be flashed to either an SPI NOR flash, SD card or eMMC module:
 * For removable SD or eMMC (easiest), you can simply use balenaEtcher, RPi Imager or dd.
-* For SPI NOR or soldered eMMC, instructions can be found at: <https://wiki.radxa.com/Rock5/install/spi>.
+* For SPI NOR or soldered eMMC, instructions can be found at: <https://docs.radxa.com/en/rock5/lowlevel-development/bootloader_spi_flash>.
 
   In short, you can flash the image from Linux booted on the device or by using RKDevTool on another computer. The latter requires entering Maskrom mode on the device. The way to do this slightly varies across platforms, refer to your vendor documentation.
 
@@ -142,15 +142,27 @@ Also check the configuration options described below, some of which may need to
 If you experience any issues, please see the [Troubleshooting](#troubleshooting) section.
 
 # Configuration settings
-The UEFI provides a few configuration options, like CPU frequency, PCIe/SATA selection for an M.2 port, fan control, etc. These can be viewed and changed using the UI configuration menu (under `Device Manager` -> `Rockchip Platform Configuration`).
+The UEFI provides a few configuration options, like CPU frequency, PCIe/SATA selection for an M.2 port, fan control, etc. These can be viewed and changed using the UI configuration menu (under `Device Manager`->`Rockchip Platform Configuration`).
 
 Configuration through the user interface is fairly straightforward and help/navigation information is provided around the menus.
 
 ## Tips
-* CPU clocks are set to 816 MHz (boot default) on platforms without a cooling fan included. If you have adequate cooling, go to the configuration menu -> `CPU Performance` and set all Cluster Presets to `Maximum`.
+### Boot time optimization
+* If there are unused M.2/PCIe slots, you can disable them to skip initialization: `Device Manager`->`Rockchip Platform Configuration`->`PCIe/SATA/USB Combo PIPE PHY` and set the relevant PHYs to `Unconnected`. Do the same for `PCI Express 3.0` by setting `Support State` to `Disabled`.
+
+* Auto boot time-out can be decreased from `Boot Maintenance Manager`.
+
+* If network boot is not used, it can be disabled: `Device Manager`->`Network Stack Configuration` then uncheck `Network Stack`.
+
+* If you do not need the ability to hot-plug displays or use DisplayPort while in the firmware: `Device Manager`->`Rockchip Platform Configuration`->`Display` and set `Force Output` to `Disabled`. This will skip display initialization when none is connected.
+
+* By default, the firmware connects all boot devices regardless of whether they are needed for the current boot. This is done to address potential compatibility issues and generally takes a negligible amount of time, thus it is recommended to not change it. However, it is still possible to do so: `Boot Maintenance Manager`->`Boot Discovery Policy`.
+
+### Linux boot
+* If you're getting a Synchronous Exception when booting certain distros, go to `Device Manager`->`EFI Memory Attribute Protocol` and uncheck `Enable Protocol`.
 
 ## Device Tree configuration
-For rich Linux support, it is recommended to enable Device Tree mode. You can do so by going to the configuration menu -> `ACPI / Device Tree` and setting `Config Table Mode` to `Device Tree`.
+For rich Linux support, it is recommended to enable Device Tree mode. You can do so by going to `Device Manager`->`Rockchip Platform Configuration`->`ACPI / Device Tree` and setting `Config Table Mode` to `Device Tree`.
 
 The firmware provides two compatibility modes:
 * `Vendor` - compatible with Rockchip SDK Linux 5.10/6.1 kernel only.
@@ -159,22 +171,31 @@ The firmware provides two compatibility modes:
 [Platinum](#platinum) platforms will have the `Mainline` option enabled by default, while [Bronze](#bronze) ones will fall back to `Vendor`.
 
 > [!TIP]
-> In `Mainline` mode with generic Linux kernels older than 6.13, the HDMI output will not be usable. To use the UEFI-initialized display instead, go to the configuration menu -> `ACPI / Device Tree` and enable `Force UEFI GOP Display`. Note that GPU acceleration cannot work in this mode.
+> In `Mainline` mode with generic Linux kernels older than 6.15, the HDMI output will not be usable. To use the UEFI-initialized display instead, go to `Device Manager`->`Rockchip Platform Configuration`->`ACPI / Device Tree` and enable `Force UEFI GOP Display`. Note that GPU acceleration cannot work in this mode.
 
 ### Custom Device Tree Blob (DTB) override and overlays
-It is also possible to provide a custom DTB and overlays. To enable this, go to the configuration menu -> `ACPI / Device Tree` and set `Support DTB override & overlays` to `Enabled`.
+It is also possible to provide a custom DTB and overlays. This is useful in cases where the firmware DTB is outdated, does not match the kernel used or for testing purposes. To enable overrides, go to `Device Manager`->`Rockchip Platform Configuration`->`ACPI / Device Tree` and set `Support DTB override & overlays` to `Enabled`.
 
-The firmware will now look for overrides in the partition of a selected boot option / OS loader. In most cases, this will be the first FAT32 EFI System Partition.
+The firmware will now look for overrides in all supported file systems / partitions (FAT, ext4) on the selected boot device.
 
-**Important:** The `dtb` directory must be placed at the root of the partition. It should not be inside any sub-directory.
+**Important:**
+* The paths below are relative to the root of the partition. They must not be inside any sub-directory.
+* All overrides (base DTB and overlays) must be stored within a single partition. Using a base DTB from one partition and overlays from another is not allowed.
 
-* The base DTB must be located at `\dtb\base\<PLATFORM-DT-NAME>.dtb`.
+The base DTB can be placed in:
+* `\dtb`
+* `\dtb\base`
+* `\dtb\rockchip` - Fedora images have the kernel DTBs in this location on the second ext4 boot partition.
 
-* The overlays can be placed in:
-  * `\dtb\overlays` - will be applied first, regardless of the platform.
-  * `\dtb\overlays\<PLATFORM-DT-NAME>` - will be applied only to the specified platform.
+and must have the `<PLATFORM-DT-NAME>.dtb` file name.
 
-  and must have the `.dtbo` extension.
+The overlays can be placed in:
+* `\dtb\overlays` - will be applied first, regardless of the platform.
+* `\dtb\overlays\<PLATFORM-DT-NAME>` - will be applied only to the specified platform.
+
+and must have the `.dtbo` extension.
+
+In addition to the default paths above, it is possible to specify custom ones via the `Preferred Base DTB Path` and `Preferred Overlays Path` setup options in the menu described above.
 
 `<PLATFORM-DT-NAME>` can be:
 | Name                                    | Platform                      |
@@ -202,15 +223,16 @@ The firmware will now look for overrides in the partition of a selected boot opt
 | `rk3588s-nanopi-m6`                     | NanoPi M6                     |
 | `rk3588-hinlink-h88k`                   | H88K                          |
 
-In the absence of a custom base DTB override, the overlays are applied on top of the firmware-provided DTB.
+**Notes:**
+* The firmware applies some fix-ups to the DTB depending on the user settings (e.g. PCIe/SATA/USB selection, making SATA overlays redundant). These fix-ups are not applied when providing overrides by other means, such as the Grub `devicetree` command.
 
-The firmware applies some fix-ups to its own DTB depending on the user settings (e.g. PCIe/SATA/USB selection, making SATA overlays redundant). These fix-ups are not applied to a custom base DTB - overlays must be used instead.
+* In the absence of a base DTB override, the overlays are applied on top of the firmware-provided DTB.
 
-If the application of an overlay fails (e.g. due to it being invalid in regard to the base DTB), all overlays are discarded, including those that got applied up to that point.
+* If the application of an overlay fails (e.g. due to incompatibility with the base DTB), all other overlays are discarded.
 
-If the custom base DTB is invalid, the firmware-provided one will be passed to the OS instead.
+* If the base DTB override is invalid, the firmware-provided one will be passed to the OS instead.
 
-This entire process is logged to the [serial console](#advanced-troubleshooting). There's currently no other way to see potential errors.
+* This process is logged to the [serial console](#advanced-troubleshooting). It is the only way to see potential errors.
 
 # Updating the firmware
 If the storage is only used for UEFI and nothing else, simply download the latest image and flash it as described in the [Getting started](#getting-started) section.
@@ -226,6 +248,20 @@ dd if=FIRMWARE.img of=DESTINATION bs=512 skip=64 seek=64 conv=notrunc
 
 Here we skip the GPT and copy the firmware starting at offset 0x8000 (`64` blocks * `512` bytes block size) until its end. See [Flash layout](#flash-layout) for more details.
 
+## Flash SPI NOR from the UEFI Shell
+1) Copy the firmware image to a FAT32 partition on a storage drive and connect it to the device.
+
+2) Launch the UEFI Shell (press <kbd>F1</kbd> during boot or go to `Boot Manager`->`UEFI Shell`).
+
+3) Navigate to the partition / file system containing the firmware image:
+   * Use the `map` command to list all mounted file systems, e.g. `fs0:`, `fs1:`, etc. Type the file system name and press <kbd>Enter</kbd> to change directory to it.
+
+   * If you're unsure which file system to use, run `ls fsX:` (replace `X` with the actual number) to list its contents.
+
+4) Run `sf updatefile FIRMWARE.img 0x0` and wait for the update process to complete.
+
+5) Reboot the device.
+
 # Troubleshooting
 
 > [!IMPORTANT]
@@ -260,11 +296,13 @@ Additionally, holding the Recovery (or volume up) button while powering on the d
 Make sure you've flashed the firmware correctly and that it is the version designed for your device. In most cases this is the culprit.
 
 Assuming the firmware loads fine:
-* The display must support a resolution of at least 1080p at 60 Hz.
-* If you're using HDMI and the system has two ports, only one will work. Try both.
+* The display must support a resolution of at least 640 x 480 at 60 Hz.
+
+* Try booting without any display connected, then plug it in after a couple of seconds (when the status LED pattern changes). This will force the firmware to output at the minimum supported resolution. You can then increase the resolution by going to `Device Manager`->`Rockchip Platform Configuration`->`Display`.
+
 * If you're using USB-C to DisplayPort, only one orientation of the USB-C connector will work. Check both.
 
-If you are not able to get any display output, the only way to interact with UEFI is via the [serial console](#advanced-troubleshooting).
+If you are still not able to get any display output, the only way to interact with UEFI is via the [serial console](#advanced-troubleshooting).
 
 ### Configuration settings do not get saved
 This has been observed in cases where firmware was present on more than one device (SPI NOR, eMMC or SD). This is not a supported scenario, because UEFI will be unable to accurately determine the boot device it belongs to. The solution is to unplug or erase devices that may have other firmware on them.
@@ -275,7 +313,7 @@ This has been observed in cases where firmware was present on more than one devi
 * Make sure the power supply and cable are good.
 
 ### Networking does not work
-* Only Realtek PCIe and USB controllers are supported. Native Gigabit provided by RK3588 isn't.
+* Only integrated Gigabit Ethernet (GMAC), Realtek PCIe and USB controllers are supported.
 
 * Some boards with Realtek NICs do not have a MAC address set at factory and will show-up as being all zeros in UEFI, possibly preventing the adapter from obtaining an IP address.
 
@@ -317,6 +355,20 @@ This has been observed in cases where firmware was present on more than one devi
 
   **Note:** the number of eFuses is limited, thus MAC addresses can only be changed a few times.
 
+### Wi-Fi / Bluetooth not working on mainline Linux
+The most likely cause is missing upstream firmware support. Check `dmesg` for messages that indicate firmware load errors.
+
+This can usually be fixed by manually copying the necessary blobs to `/usr/lib/firmware`.
+
+For instance, on Khadas Edge2 with an onboard AP6275P module (BCM/SYN43752):
+```bash
+sudo wget https://github.com/armbian/firmware/raw/refs/heads/master/brcm/brcmfmac43752-pcie.bin -P /usr/lib/firmware/brcm/
+sudo wget https://github.com/armbian/firmware/raw/refs/heads/master/brcm/brcmfmac43752-pcie.clm_blob -P /usr/lib/firmware/brcm/
+sudo wget https://github.com/armbian/firmware/raw/refs/heads/master/brcm/brcmfmac43752-pcie.txt -P /usr/lib/firmware/brcm/
+sudo wget https://github.com/armbian/firmware/raw/refs/heads/master/brcm/BCM4362A2.hcd -P /usr/lib/firmware/brcm/
+```
+then reboot.
+
 ## Advanced troubleshooting
 The firmware will log detailed information to the serial console when using a debug version. See the [release notes](https://github.com/edk2-porting/edk2-rk3588/releases) for details on how to obtain this version.
 

build.sh

@@ -11,10 +11,11 @@ function _help(){
     echo "  -r, --release MODE          Release mode for building, default is 'DEBUG', 'RELEASE' alternatively."
     echo "  -t, --toolchain TOOLCHAIN   Set toolchain, default is 'GCC'."
     echo "  --open-tfa ENABLE           Use open-source TF-A submodule. Default: ${OPEN_TFA}"
-    echo "  -C, --clean                 Clean workspace and output."
-    echo "  -D, --distclean             Clean up all files that are not in repo."
     echo "  --tfa-flags \"FLAGS\"         Flags appended to open TF-A build process."
     echo "  --edk2-flags \"FLAGS\"        Flags appended to the EDK2 build process."
+    echo "  --skip-patchsets            Skip applying upstream submodule patchsets during development."
+    echo "  -C, --clean                 Clean workspace and output."
+    echo "  -D, --distclean             Clean up all files that are not in repo."
     echo "  -h, --help                  Show this help."
     echo
     exit "${1}"
@@ -22,6 +23,59 @@ function _help(){
 
 function _error() { echo "${@}" >&2; exit 1; }
 
+function apply_patchset() {
+    ${SKIP_PATCHSETS} && return 0
+
+    local patches_dir="$1"
+    local target_dir="$2"
+
+    [ ! -d "${patches_dir}" ] && return 0
+
+    if [ ! -d "${target_dir}" ]; then
+        echo "Patchset target directory does not exist: ${target_dir}"
+        return 1
+    fi
+
+    echo "Checking patchset ${patches_dir} for ${target_dir}"
+
+    local patchset_name=$(basename "${patches_dir}")
+    local patchset_marker="${target_dir}/.patchset_${patchset_name}"
+
+    if [ ! -f "${patchset_marker}" ] || [ "${patches_dir}" -nt "${patchset_marker}" ]; then
+        echo "Patchset needs to be (re)applied"
+        if ! git -C "${target_dir}" reset --hard || ! git -C "${target_dir}" clean -xfd; then
+            echo "Failed to reset git repository - aborting"
+            return 1
+        fi
+    else
+        echo "Patchset already applied - skipping"
+        return 0
+    fi
+
+    local patch_file
+    local patch_count=0
+
+    for patch_file in "${patches_dir}"/*.patch; do
+        [ -f "${patch_file}" ] || continue
+
+        local patch_name=$(basename "${patch_file}")
+        echo "Patch ${patch_count}: ${patch_name}"
+
+        if patch -p1 -d "${target_dir}" < "${patch_file}"; then
+            echo "  Successfully applied"
+            ((patch_count++))
+        else
+            echo "  Failed to apply - aborting"
+            return 1
+        fi
+    done
+
+    touch "${patchset_marker}"
+
+    echo "Patchset summary: ${patch_count} applied"
+    return 0
+}
+
 function _build_idblock() {
     echo " => Building idblock.bin"
     pushd ${WORKSPACE}
@@ -58,7 +112,7 @@ function _build_fit() {
     BL31="${ROOTDIR}/misc/rkbin/${BL31_RKBIN}"
     BL32="${ROOTDIR}/misc/rkbin/${BL32_RKBIN}"
 
-    if [ ${OPEN_TFA} == 1 ]; then
+    if ${OPEN_TFA}; then
         BL31="${ROOTDIR}/arm-trusted-firmware/build/${TFA_PLAT}/${RELEASE_TYPE,,}/bl31/bl31.elf"
     fi
 
@@ -117,7 +171,9 @@ function _build(){
     #
     # Build TF-A
     #
-    if [ ${OPEN_TFA} == 1 ]; then
+    if ${OPEN_TFA}; then
+        apply_patchset "${ROOTDIR}/arm-trusted-firmware-patches" "${ROOTDIR}/arm-trusted-firmware" || exit 1
+
         pushd arm-trusted-firmware
 
         if [ ${RELEASE_TYPE} == "DEBUG" ]; then
@@ -134,11 +190,21 @@ function _build(){
     #
     # Build EDK2
     #
+    apply_patchset "${ROOTDIR}/edk2-patches" "${ROOTDIR}/edk2" || exit 1
+    apply_patchset "${ROOTDIR}/devicetree/mainline/patches" "${ROOTDIR}/devicetree/mainline/upstream" || exit 1
+
     [ -d "${WORKSPACE}/Conf" ] || mkdir -p "${WORKSPACE}/Conf"
 
     export GCC_AARCH64_PREFIX="${CROSS_COMPILE}"
     export CLANG38_AARCH64_PREFIX="${CROSS_COMPILE}"
-    export PACKAGES_PATH="${ROOTDIR}/edk2:${ROOTDIR}/edk2-platforms:${ROOTDIR}/edk2-rockchip:${ROOTDIR}/devicetree:${ROOTDIR}/edk2-non-osi:${ROOTDIR}"
+    PACKAGES_PATH="${ROOTDIR}"
+    PACKAGES_PATH+=":${ROOTDIR}/devicetree"
+    PACKAGES_PATH+=":${ROOTDIR}/edk2"
+    PACKAGES_PATH+=":${ROOTDIR}/edk2-non-osi"
+    PACKAGES_PATH+=":${ROOTDIR}/edk2-platforms"
+    PACKAGES_PATH+=":${ROOTDIR}/edk2-rockchip"
+    PACKAGES_PATH+=":${ROOTDIR}/edk2-rockchip-non-osi"
+    export PACKAGES_PATH
 
     make -C "${ROOTDIR}/edk2/BaseTools"
     source "${ROOTDIR}/edk2/edksetup.sh"
@@ -151,6 +217,9 @@ function _build(){
         -p "${ROOTDIR}/${DSC_FILE}" \
         -b "${RELEASE_TYPE}" \
         -D FIRMWARE_VER="${GIT_COMMIT}" \
+        -D NETWORK_ALLOW_HTTP_CONNECTIONS=TRUE \
+        -D NETWORK_ISCSI_ENABLE=TRUE \
+        -D INCLUDE_TFTP_COMMAND=TRUE \
         --pcd gRockchipTokenSpaceGuid.PcdFitImageFlashAddress=0x100000 \
         ${EDK2_FLAGS}
 
@@ -173,9 +242,10 @@ typeset -u RELEASE_TYPE
 DEVICE=""
 RELEASE_TYPE=DEBUG
 TOOLCHAIN=GCC
-OPEN_TFA=1
+OPEN_TFA=true
 TFA_FLAGS=""
 EDK2_FLAGS=""
+SKIP_PATCHSETS=false
 CLEAN=false
 DISTCLEAN=false
 OUTDIR="${PWD}"
@@ -183,7 +253,7 @@ OUTDIR="${PWD}"
 #
 # Get options
 #
-OPTS=$(getopt -o "d:r:t:CDh" -l "device:,release:,toolchain:,open-tfa:,tfa-flags:,edk2-flags:,clean,distclean,help" -n build.sh -- "${@}") || _help $?
+OPTS=$(getopt -o "d:r:t:CDh" -l "device:,release:,toolchain:,open-tfa:,tfa-flags:,edk2-flags:,skip-patchsets,clean,distclean,help" -n build.sh -- "${@}") || _help $?
 eval set -- "${OPTS}"
 while true; do
     case "${1}" in
@@ -193,6 +263,7 @@ while true; do
         --open-tfa) OPEN_TFA="${2}"; shift 2 ;;
         --tfa-flags) TFA_FLAGS="${2}"; shift 2 ;;
         --edk2-flags) EDK2_FLAGS="${2}"; shift 2 ;;
+        --skip-patchsets) SKIP_PATCHSETS=true; shift ;;
         -C|--clean) CLEAN=true; shift ;;
         -D|--distclean) DISTCLEAN=true; shift ;;
         -h|--help) _help 0; shift ;;

devicetree/mainline/rk3588-buzztv-p6.dts

@@ -60,6 +60,31 @@
 		pinctrl-0 = <&ir_receiver_pin>;
 	};
 
+	rfkill {
+		compatible = "rfkill-gpio";
+		label = "rfkill-pcie-wlan";
+		radio-type = "wlan";
+		shutdown-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+	};
+
+	spdif_dit: spdif-dit {
+		compatible = "linux,spdif-dit";
+		#sound-dai-cells = <0>;
+	};
+
+	spdif_sound: spdif-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "SPDIF";
+
+		simple-audio-card,cpu {
+			sound-dai = <&spdif_tx1>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&spdif_dit>;
+		};
+	};
+
 	vcc12v_dcin: regulator-vcc12v-dcin {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc12v_dcin";
@@ -195,6 +220,11 @@
 };
 
 &hdmi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmim0_tx0_cec
+		     &hdmim1_tx0_hpd
+		     &hdmim0_tx0_scl
+		     &hdmim0_tx0_sda>;
 	status = "okay";
 };
 
@@ -210,7 +240,11 @@
 	};
 };
 
-&hdptxphy_hdmi0 {
+&hdmi0_sound {
+ 	status = "okay";
+};
+
+&hdptxphy0 {
 	status = "okay";
 };
 
@@ -340,6 +374,10 @@
 	};
 };
 
+&i2s5_8ch {
+ 	status = "okay";
+};
+
 /* RTL8852BE */
 &pcie2x1l0 {
 	pinctrl-names = "default";
@@ -394,6 +432,10 @@
 	};
 };
 
+&pd_gpu {
+ 	domain-supply = <&vdd_gpu_s0>;
+};
+
 &pinctrl {
 	hym8563 {
 		hym8563_int: hym8563-int {
@@ -503,6 +545,12 @@
 	status = "okay";
 };
 
+&spdif_tx1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spdif1m1_tx>;
+	status = "okay";
+};
+
 &spi2 {
 	status = "okay";
 	assigned-clocks = <&cru CLK_SPI2>;

devicetree/mainline/rk3588-friendlyelec-cm3588-nas-fixup.dts

@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588-friendlyelec-cm3588-nas.dts"
+
+&hdmi0_sound {
+ 	status = "okay";
+};
+
+&hdmi1_sound {
+	status = "okay";
+};
+
+&i2s5_8ch {
+ 	status = "okay";
+};
+
+&i2s6_8ch {
+	status = "okay";
+};

devicetree/mainline/rk3588-nanopc-t6-fixup.dts

@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588-nanopc-t6.dts"
+
+&hdmi0_sound {
+ 	status = "okay";
+};
+
+&hdmi1_sound {
+	status = "okay";
+};
+
+&i2s5_8ch {
+ 	status = "okay";
+};
+
+&i2s6_8ch {
+	status = "okay";
+};

devicetree/mainline/rk3588-rock-5-itx-fixup.dts

@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588-rock-5-itx.dts"
+
+/ {
+	/delete-node/ pcie-oscillator;
+};
+
+&hdmi1_sound {
+	status = "okay";
+};
+
+&i2s6_8ch {
+	status = "okay";
+};
+
+/*
+ * Remove the "pcie30_refclk" gated-fixed-clock to maintain compatibility
+ * with kernels older than v6.13-rc1. It is backed by a GPIO regulator
+ * anyway, so simply referencing it in vpcie3v3-supply also addresses
+ * the potential issue where pcie3x2 might probe earlier than pcie3x4 and
+ * hang on DBI access because the clock didn't have a chance to be enabled.
+ */
+&pcie3x2 {
+	clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
+		 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
+		 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
+	clock-names = "aclk_mst", "aclk_slv",
+		      "aclk_dbi", "pclk",
+		      "aux", "pipe";
+	vpcie3v3-supply = <&vcc3v3_pi6c_05>;
+};
+
+&pcie3x4 {
+	clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
+		 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
+		 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
+	clock-names = "aclk_mst", "aclk_slv",
+		      "aclk_dbi", "pclk",
+		      "aux", "pipe";
+};

devicetree/mainline/rk3588s-indiedroid-nova-fixup.dts

@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-indiedroid-nova.dts"
+
+&hdmi0_sound {
+ 	status = "okay";
+};
+
+&i2s5_8ch {
+ 	status = "okay";
+};

devicetree/mainline/rk3588s-khadas-edge2-fixup.dts

@@ -0,0 +1,279 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3588s-khadas-edge2.dts"
+
+/ {
+	analog-sound {
+		compatible = "audio-graph-card";
+		label = "rk3588-es8316";
+
+		widgets = "Microphone", "Mic Jack",
+			  "Headphone", "Headphones";
+
+		routing = "MIC2", "Mic Jack",
+			  "Headphones", "HPOL",
+			  "Headphones", "HPOR";
+
+		dais = <&i2s0_8ch_p0>;
+		hp-det-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&hp_detect>;
+	};
+
+	hdmi0-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi0_con_in: endpoint {
+				remote-endpoint = <&hdmi0_out_con>;
+			};
+		};
+	};
+
+	vbus5v0_typec: regulator-vbus5v0-typec {
+		compatible = "regulator-fixed";
+		regulator-name = "vbus5v0_typec";
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&typec5v_pwren>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+};
+
+&i2c2 {
+	fusb302: typec-portc@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PB5 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usbc0_int>;
+		vbus-supply = <&vbus5v0_typec>;
+
+		usb_con: connector {
+			compatible = "usb-c-connector";
+			data-role = "dual";
+			label = "USB-C";
+			power-role = "dual";
+			try-power-role = "source";
+			op-sink-microwatt = <1000000>;
+			sink-pdos =
+				<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+				 PDO_FIXED(9000, 3000, PDO_FIXED_USB_COMM)
+				 PDO_FIXED(12000, 3000, PDO_FIXED_USB_COMM)>;
+			source-pdos =
+				<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					usbc0_orien_sw: endpoint {
+						remote-endpoint = <&usbdp_phy0_orientation_switch>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					usbc0_role_sw: endpoint {
+						remote-endpoint = <&dwc3_0_role_switch>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					dp_altmode_mux: endpoint {
+						remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
+					};
+				};
+			};
+		};
+	};
+};
+
+&i2c3 {
+	status = "okay";
+
+	es8316: audio-codec@10 {
+		compatible = "everest,es8316";
+		reg = <0x10>;
+		clocks = <&cru I2S0_8CH_MCLKOUT>;
+		clock-names = "mclk";
+		assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+		assigned-clock-rates = <12288000>;
+		#sound-dai-cells = <0>;
+
+		port {
+			es8316_p0_0: endpoint {
+				remote-endpoint = <&i2s0_8ch_p0_0>;
+			};
+		};
+	};
+};
+
+&i2s0_8ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s0_lrck
+		     &i2s0_mclk
+		     &i2s0_sclk
+		     &i2s0_sdi0
+		     &i2s0_sdo0>;
+	status = "okay";
+
+	i2s0_8ch_p0: port {
+		i2s0_8ch_p0_0: endpoint {
+			dai-format = "i2s";
+			mclk-fs = <256>;
+			remote-endpoint = <&es8316_p0_0>;
+		};
+	};
+};
+
+&pinctrl {
+	usb-typec {
+		usbc0_int: usbc0-int {
+			rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		typec5v_pwren: typec5v-pwren {
+			rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sound {
+		hp_detect: hp-detect {
+			rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	bluetooth {
+		bt_reset: bt-reset {
+			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_dev_wake: bt-dev-wake {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_host_wake: bt-host-wake {
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+};
+
+&uart9 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart9m2_xfer>, <&uart9m2_rtsn>, <&uart9m2_ctsn>;
+	uart-has-rtscts;
+
+	bluetooth {
+		compatible = "brcm,bcm43752-bt", "cypress,cyw4373a0-bt";
+		max-speed = <4000000>;
+		clocks = <&hym8563>;
+		clock-names = "lpo";
+		shutdown-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+		device-wakeup-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PD5 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "host-wakeup";
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_reset>, <&bt_dev_wake>, <&bt_host_wake>;
+	};
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	status = "okay";
+};
+
+&usbdp_phy0 {
+	mode-switch;
+	orientation-switch;
+	sbu1-dc-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>;
+	sbu2-dc-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usbdp_phy0_orientation_switch: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_orien_sw>;
+		};
+
+		usbdp_phy0_dp_altmode_mux: endpoint@1 {
+			reg = <1>;
+			remote-endpoint = <&dp_altmode_mux>;
+		};
+	};
+};
+
+&usb_host0_xhci {
+	usb-role-switch;
+	status = "okay";
+
+	port {
+		dwc3_0_role_switch: endpoint {
+			remote-endpoint = <&usbc0_role_sw>;
+		};
+	};
+};
+
+&hdmi0 {
+	status = "okay";
+};
+
+&hdmi0_in {
+	hdmi0_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi0>;
+	};
+};
+
+&hdmi0_out {
+	hdmi0_out_con: endpoint {
+		remote-endpoint = <&hdmi0_con_in>;
+	};
+};
+
+&hdmi0_sound {
+ 	status = "okay";
+};
+
+&hdptxphy0 {
+	status = "okay";
+};
+
+&i2s5_8ch {
+ 	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi0_in_vp0>;
+	};
+};

devicetree/mainline/rk3588s-nanopi-r6c-fixup.dts

@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-nanopi-r6c.dts"
+
+&hdmi0_sound {
+ 	status = "okay";
+};
+
+&i2s5_8ch {
+ 	status = "okay";
+};

devicetree/mainline/rk3588s-nanopi-r6s-fixup.dts

@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-nanopi-r6s.dts"
+
+&hdmi0_sound {
+ 	status = "okay";
+};
+
+&i2s5_8ch {
+ 	status = "okay";
+};

devicetree/mainline/rk3588s-rock-5a-fixup.dts

@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-rock-5a.dts"
+
+&hdmi0_sound {
+ 	status = "okay";
+};
+
+&i2s5_8ch {
+ 	status = "okay";
+};

edk2-patches/0001-MdePkg-BaseFdtLib-Add-more-wrappers.patch

@@ -0,0 +1,103 @@
+From 7f9f0713b06cadff7071271c76d10a2091c8823d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Mario=20B=C4=83l=C4=83nic=C4=83?=
+ <mariobalanica02@gmail.com>
+Date: Fri, 5 Dec 2025 14:02:15 +0200
+Subject: [PATCH] MdePkg/BaseFdtLib: Add more wrappers
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add FDT_HEADER field accessors and FdtOverlayApply() wrapper.
+
+Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
+---
+ MdePkg/Include/Library/FdtLib.h    | 29 ++++++++++++++++++++++++++++-
+ MdePkg/Library/BaseFdtLib/FdtLib.c | 18 ++++++++++++++++++
+ 2 files changed, 46 insertions(+), 1 deletion(-)
+
+diff --git a/MdePkg/Include/Library/FdtLib.h b/MdePkg/Include/Library/FdtLib.h
+index a7f63f3d5a..16e8179af4 100644
+--- a/MdePkg/Include/Library/FdtLib.h
++++ b/MdePkg/Include/Library/FdtLib.h
+@@ -181,7 +181,16 @@ typedef struct {
+ 
+ #define FdtGetHeader(Fdt, Field) \
+   (Fdt32ToCpu (((const FDT_HEADER *)(Fdt))->Field))
+-#define FdtTotalSize(Fdt)  (FdtGetHeader ((Fdt), TotalSize))
++#define FdtMagic(Fdt)            (FdtGetHeader ((Fdt), Magic))
++#define FdtTotalSize(Fdt)        (FdtGetHeader ((Fdt), TotalSize))
++#define FdtOffsetDtStruct(Fdt)   (FdtGetHeader ((Fdt), OffsetDtStruct))
++#define FdtOffsetDtStrings(Fdt)  (FdtGetHeader ((Fdt), OffsetDtStrings))
++#define FdtOffsetMemRsvmap(Fdt)  (FdtGetHeader ((Fdt), OffsetMemRsvmap))
++#define FdtVersion(Fdt)          (FdtGetHeader ((Fdt), Version))
++#define FdtLastCompVersion(Fdt)  (FdtGetHeader ((Fdt), LastCompVersion))
++#define FdtBootCpuidPhys(Fdt)    (FdtGetHeader ((Fdt), BootCpuidPhys))
++#define FdtSizeDtStrings(Fdt)    (FdtGetHeader ((Fdt), SizeDtStrings))
++#define FdtSizeDtStruct(Fdt)     (FdtGetHeader ((Fdt), SizeDtStruct))
+ 
+ #define FdtForEachSubnode(Node, Fdt, Parent) \
+   for (Node = FdtFirstSubnode (Fdt, Parent); \
+@@ -191,6 +200,9 @@ typedef struct {
+ #define FdtSetPropString(Fdt, NodeOffset, Name, String) \
+   FdtSetProp ((Fdt), (NodeOffset), (Name), (String), AsciiStrLen (String) + 1)
+ 
++#define FdtSetPropEmpty(Fdt, NodeOffset, Name) \
++  FdtSetProp ((Fdt), (NodeOffset), (Name), NULL, 0)
++
+ /**
+   Convert UINT16 data of the FDT blob to little-endian
+ 
+@@ -960,6 +972,21 @@ FdtGetPhandle (
+   IN INT32       NodeOffset
+   );
+ 
++/**
++  Applies a DT overlay on a base DT.
++
++  @param[in] Fdt            The pointer to FDT blob.
++  @param[in] Fdto           The pointer to FDT overlay blob.
++
++  @return 0 on success, or negative error code.
++**/
++INT32
++EFIAPI
++FdtOverlayApply (
++  IN VOID  *Fdt,
++  IN VOID  *Fdto
++  );
++
+ /* Debug functions. */
+ CONST
+ CHAR8
+diff --git a/MdePkg/Library/BaseFdtLib/FdtLib.c b/MdePkg/Library/BaseFdtLib/FdtLib.c
+index 3dacfbee45..8c986650dc 100644
+--- a/MdePkg/Library/BaseFdtLib/FdtLib.c
++++ b/MdePkg/Library/BaseFdtLib/FdtLib.c
+@@ -918,6 +918,24 @@ FdtGetPhandle (
+   return fdt_get_phandle (Fdt, NodeOffset);
+ }
+ 
++/**
++  Applies a DT overlay on a base DT.
++
++  @param[in] Fdt            The pointer to FDT blob.
++  @param[in] Fdto           The pointer to FDT overlay blob.
++
++  @return 0 on success, or negative error code.
++**/
++INT32
++EFIAPI
++FdtOverlayApply (
++  IN VOID  *Fdt,
++  IN VOID  *Fdto
++  )
++{
++  return fdt_overlay_apply (Fdt, Fdto);
++}
++
+ /* Debug functions. */
+ CONST
+ CHAR8
+-- 
+2.39.1.windows.1
+

edk2-rockchip-non-osi/Drivers/AMD/Gop/AmdGopOpRomOverride.c

@@ -0,0 +1,213 @@
+/** @file
+ *
+ *  AMD GOP OpROM override
+ *
+ *  Copyright (c) 2025, Mario Bălănică <mariobalanica02@gmail.com>
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <Protocol/DriverFamilyOverride.h>
+#include <Protocol/LoadedImage.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+
+STATIC CONST EFI_GUID  mAmdGopDriverGuids[] = {
+  { 0x62c34cea, 0xa08d, 0x4676, { 0x81, 0xe5, 0xf1, 0x6b, 0x0e, 0xe2, 0x2f, 0x22 }
+  }, // AmdGopPreSoc15Dxe.inf
+  { 0x92f10585, 0xfb63, 0x430f, { 0x81, 0x88, 0x71, 0xfe, 0xeb, 0x2d, 0xda, 0x5b }
+  }, // AmdGopPostSoc15Dxe.inf
+};
+
+STATIC
+UINT32
+AmdGopDriverFamilyOverrideGetVersion (
+  IN EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL  *This
+  )
+{
+  return MAX_UINT32;
+}
+
+STATIC EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL  mAmdGopDriverFamilyOverride = {
+  AmdGopDriverFamilyOverrideGetVersion
+};
+
+STATIC
+EFI_STATUS
+EFIAPI
+AmdGopUnloadImage (
+  IN  EFI_HANDLE  ImageHandle
+  )
+{
+  EFI_STATUS                 Status;
+  EFI_LOADED_IMAGE_PROTOCOL  *LoadedImage;
+  EFI_IMAGE_UNLOAD           OriginalUnload;
+
+  Status = gBS->HandleProtocol (
+                  ImageHandle,
+                  &gEfiLoadedImageProtocolGuid,
+                  (VOID **)&LoadedImage
+                  );
+  if (EFI_ERROR (Status)) {
+    ASSERT_EFI_ERROR (Status);
+    return Status;
+  }
+
+  Status = gBS->HandleProtocol (
+                  ImageHandle,
+                  &gEfiCallerIdGuid,
+                  (VOID **)&OriginalUnload
+                  );
+  if (EFI_ERROR (Status)) {
+    ASSERT_EFI_ERROR (Status);
+    return Status;
+  }
+
+  gBS->UninstallMultipleProtocolInterfaces (
+         ImageHandle,
+         &gEfiDriverFamilyOverrideProtocolGuid,
+         &mAmdGopDriverFamilyOverride,
+         &gEfiCallerIdGuid,
+         OriginalUnload,
+         NULL
+         );
+
+  LoadedImage->Unload = OriginalUnload;
+
+  return LoadedImage->Unload (ImageHandle);
+}
+
+STATIC
+EFI_GUID *
+GetLoadedImageGuid (
+  IN EFI_LOADED_IMAGE_PROTOCOL  *LoadedImage
+  )
+{
+  EFI_DEVICE_PATH_PROTOCOL  *DevPathNode;
+  EFI_GUID                  *NameGuid;
+
+  if ((LoadedImage == NULL) || (LoadedImage->FilePath == NULL)) {
+    return NULL;
+  }
+
+  DevPathNode = LoadedImage->FilePath;
+
+  while (!IsDevicePathEnd (DevPathNode)) {
+    NameGuid = EfiGetNameGuidFromFwVolDevicePathNode (
+                 (MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *)DevPathNode
+                 );
+    if (NameGuid != NULL) {
+      return NameGuid;
+    }
+
+    DevPathNode = NextDevicePathNode (DevPathNode);
+  }
+
+  return NULL;
+}
+
+STATIC VOID  *mDriverBindingEventRegistration;
+
+STATIC
+VOID
+EFIAPI
+NotifyDriverBinding (
+  IN EFI_EVENT  Event,
+  IN VOID       *Context
+  )
+{
+  EFI_STATUS                 Status;
+  UINTN                      BufferSize;
+  EFI_HANDLE                 Handle;
+  EFI_LOADED_IMAGE_PROTOCOL  *LoadedImage;
+  EFI_GUID                   *LoadedImageGuid;
+  UINTN                      Index;
+
+  while (TRUE) {
+    BufferSize = sizeof (EFI_HANDLE);
+    Status     = gBS->LocateHandle (
+                        ByRegisterNotify,
+                        NULL,
+                        mDriverBindingEventRegistration,
+                        &BufferSize,
+                        &Handle
+                        );
+    if (EFI_ERROR (Status)) {
+      if (Status != EFI_NOT_FOUND) {
+        ASSERT_EFI_ERROR (Status);
+      }
+
+      break;
+    }
+
+    Status = gBS->HandleProtocol (
+                    Handle,
+                    &gEfiLoadedImageProtocolGuid,
+                    (VOID **)&LoadedImage
+                    );
+    if (EFI_ERROR (Status)) {
+      continue;
+    }
+
+    LoadedImageGuid = GetLoadedImageGuid (LoadedImage);
+    if (LoadedImageGuid == NULL) {
+      continue;
+    }
+
+    for (Index = 0; Index < ARRAY_SIZE (mAmdGopDriverGuids); Index++) {
+      if (!CompareGuid (LoadedImageGuid, &mAmdGopDriverGuids[Index])) {
+        continue;
+      }
+
+      DEBUG ((DEBUG_INFO, "%a: %g\n", gEfiCallerBaseName, LoadedImageGuid));
+
+      Status = gBS->InstallMultipleProtocolInterfaces (
+                      &Handle,
+                      &gEfiDriverFamilyOverrideProtocolGuid,
+                      &mAmdGopDriverFamilyOverride,
+                      NULL
+                      );
+      if (EFI_ERROR (Status)) {
+        ASSERT_EFI_ERROR (Status);
+        break;
+      }
+
+      if (LoadedImage->Unload != NULL) {
+        Status = gBS->InstallMultipleProtocolInterfaces (
+                        &Handle,
+                        &gEfiCallerIdGuid,
+                        LoadedImage->Unload,
+                        NULL
+                        );
+        if (EFI_ERROR (Status)) {
+          ASSERT_EFI_ERROR (Status);
+          break;
+        }
+
+        LoadedImage->Unload = AmdGopUnloadImage;
+      }
+    }
+  }
+}
+
+EFI_STATUS
+EFIAPI
+AmdGopOpRomOverrideInitialize (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  EfiCreateProtocolNotifyEvent (
+    &gEfiDriverBindingProtocolGuid,
+    TPL_CALLBACK,
+    NotifyDriverBinding,
+    NULL,
+    &mDriverBindingEventRegistration
+    );
+
+  return EFI_SUCCESS;
+}

edk2-rockchip-non-osi/Drivers/AMD/Gop/AmdGopOpRomOverrideDxe.inf

@@ -0,0 +1,40 @@
+#/** @file
+#
+#  AMD GOP OpROM override
+#
+#  Copyright (c) 2025, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AmdGopOpRomOverrideDxe
+  FILE_GUID                      = 261d0e39-4663-4f0f-94ad-2903b7bb31e1
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = AmdGopOpRomOverrideInitialize
+
+[Sources]
+  AmdGopOpRomOverride.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+
+[LibraryClasses]
+  BaseMemoryLib
+  DebugLib
+  DevicePathLib
+  UefiBootServicesTableLib
+  UefiLib
+  UefiDriverEntryPoint
+
+[Protocols]
+  gEfiDriverBindingProtocolGuid
+  gEfiDriverFamilyOverrideProtocolGuid
+  gEfiLoadedImageProtocolGuid
+
+[Depex]
+  TRUE

edk2-rockchip-non-osi/Drivers/AMD/Gop/AmdGopPostSoc15Dxe.inf

@@ -0,0 +1,9 @@
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AMDGopPostSoc15Dxe
+  FILE_GUID                      = 92f10585-fb63-430f-8188-71feeb2dda5b
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+
+[Binaries.AARCH64]
+  PE32|AArch64/ARM64Gop_2_10.efi|*

edk2-rockchip-non-osi/Drivers/AMD/Gop/AmdGopPreSoc15Dxe.inf

@@ -0,0 +1,9 @@
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AMDGopPreSoc15Dxe
+  FILE_GUID                      = 62c34cea-a08d-4676-81e5-f16b0ee22f22
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+
+[Binaries.AARCH64]
+  PE32|AArch64/Arm64Gop_1_68.efi|*

edk2-rockchip-non-osi/Drivers/AMD/Gop/README.md

@@ -0,0 +1,19 @@
+# AMD AARCH64 Gop Driver
+
+## Important Notes
+
+- This driver should be considered "as is" and may not be supported with further updates, upgrades or bug fixes.
+- Contact info: James Huang  (James.Huang@amd.com), Plamen Belomorski (Plamen.Belomorski@amd.com).
+- When a headless GPU ROM image is found, return “unsupported” from Supported.
+
+## Pre-SOC15 Gop Driver
+
+**Supported Asic Device ID ranges:**
+
+(0x6880, 0x689f), (0x68A0, 0x68Bf), (0x68C0, 0x68Df), (0x68E0, 0x68FF), (0x9640, 0x964f), (0x9800, 0x980f), (0x9990, 0x99Af), (0x6700, 0x671f), (0x6720, 0x673f), (0x6740, 0x675f), (0x6840, 0x685f), (0x6760, 0x677f), (0x6780, 0x679f),  (0x6800, 0x681f),  (0x6820, 0x683f), (0x6600, 0x663f), (0x6660, 0x667f), (0x1304, 0x131d), (0x6640, 0x665f), (0x67a0, 0x67bf), (0x9830, 0x983f), (0x98b0, 0x98bf), (0x6900, 0x691f), (0x6920, 0x693f), (0x6960, 0x697f), (0x7300, 0x7304), (0x67C0, 0x67DF), (0x67E0, 0x67Ff), (0x6980, 0x699f), (0x6940, 0x695f), (0x9850, 0x985f), (0x9870, 0x988f), (0x98e0, 0x98ff), (0x9890, 0x98af), (0x98c0, 0x98df)
+
+## Post-SOC15 Gop Driver
+
+For the DIDs that are not supported in pre-SoC15 GOP, please use this Post-SoC15 GOP driver.
+
+https://www.amd.com/en/resources/support-articles/release-notes/RN-AAR.html

edk2-rockchip/Platform/Ameridroid/Drivers/LogoDxe/Logo.c

@@ -19,15 +19,15 @@
 #include <Library/DebugLib.h>
 
 typedef struct {
-  EFI_IMAGE_ID                          ImageId;
-  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
-  INTN                                  OffsetX;
-  INTN                                  OffsetY;
+  EFI_IMAGE_ID                             ImageId;
+  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE    Attribute;
+  INTN                                     OffsetX;
+  INTN                                     OffsetY;
 } LOGO_ENTRY;
 
-STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
-STATIC EFI_HII_HANDLE            mHiiHandle;
-STATIC LOGO_ENTRY                mLogos[] = {
+STATIC EFI_HII_IMAGE_EX_PROTOCOL  *mHiiImageEx;
+STATIC EFI_HII_HANDLE             mHiiHandle;
+STATIC LOGO_ENTRY                 mLogos[] = {
   {
     IMAGE_TOKEN (IMG_LOGO),
     EdkiiPlatformLogoDisplayAttributeCenter,
@@ -53,18 +53,19 @@ STATIC
 EFI_STATUS
 EFIAPI
 GetImage (
-  IN     EDKII_PLATFORM_LOGO_PROTOCOL          *This,
-  IN OUT UINT32                                *Instance,
-     OUT EFI_IMAGE_INPUT                       *Image,
-     OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
-     OUT INTN                                  *OffsetX,
-     OUT INTN                                  *OffsetY
+  IN     EDKII_PLATFORM_LOGO_PROTOCOL        *This,
+  IN OUT UINT32                              *Instance,
+  OUT EFI_IMAGE_INPUT                        *Image,
+  OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE  *Attribute,
+  OUT INTN                                   *OffsetX,
+  OUT INTN                                   *OffsetY
   )
 {
-  UINT32 Current;
+  UINT32  Current;
 
-  if (Instance == NULL || Image == NULL ||
-      Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
+  if ((Instance == NULL) || (Image == NULL) ||
+      (Attribute == NULL) || (OffsetX == NULL) || (OffsetY == NULL))
+  {
     return EFI_INVALID_PARAMETER;
   }
 
@@ -78,11 +79,15 @@ GetImage (
   *OffsetX   = mLogos[Current].OffsetX;
   *OffsetY   = mLogos[Current].OffsetY;
 
-  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
-                        mLogos[Current].ImageId, Image);
+  return mHiiImageEx->GetImageEx (
+                        mHiiImageEx,
+                        mHiiHandle,
+                        mLogos[Current].ImageId,
+                        Image
+                        );
 }
 
-STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+STATIC EDKII_PLATFORM_LOGO_PROTOCOL  mPlatformLogo = {
   GetImage
 };
 
@@ -101,44 +106,66 @@ STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
 EFI_STATUS
 EFIAPI
 InitializeLogo (
-  IN EFI_HANDLE               ImageHandle,
-  IN EFI_SYSTEM_TABLE         *SystemTable
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
-  EFI_STATUS                  Status;
-  EFI_HII_PACKAGE_LIST_HEADER *PackageList;
-  EFI_HII_DATABASE_PROTOCOL   *HiiDatabase;
-  EFI_HANDLE                  Handle;
+  EFI_STATUS                   Status;
+  EFI_HII_PACKAGE_LIST_HEADER  *PackageList;
+  EFI_HII_DATABASE_PROTOCOL    *HiiDatabase;
+  EFI_HANDLE                   Handle;
 
-  Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
-                  (VOID **) &HiiDatabase);
+  Status = gBS->LocateProtocol (
+                  &gEfiHiiDatabaseProtocolGuid,
+                  NULL,
+                  (VOID **)&HiiDatabase
+                  );
   ASSERT_EFI_ERROR (Status);
 
-  Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
-                  (VOID **) &mHiiImageEx);
+  Status = gBS->LocateProtocol (
+                  &gEfiHiiImageExProtocolGuid,
+                  NULL,
+                  (VOID **)&mHiiImageEx
+                  );
   ASSERT_EFI_ERROR (Status);
 
   //
   // Retrieve HII package list from ImageHandle
   //
-  Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
-                  (VOID **) &PackageList, ImageHandle, NULL,
-                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+  Status = gBS->OpenProtocol (
+                  ImageHandle,
+                  &gEfiHiiPackageListProtocolGuid,
+                  (VOID **)&PackageList,
+                  ImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
   if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR,
-      "HII Image Package with logo not found in PE/COFF resource section\n"));
+    DEBUG ((
+      DEBUG_ERROR,
+      "HII Image Package with logo not found in PE/COFF resource section\n"
+      ));
     return Status;
   }
 
   //
   // Publish HII package list to HII Database.
   //
-  Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
-                          &mHiiHandle);
+  Status = HiiDatabase->NewPackageList (
+                          HiiDatabase,
+                          PackageList,
+                          NULL,
+                          &mHiiHandle
+                          );
   if (!EFI_ERROR (Status)) {
     Handle = NULL;
-    Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
-                    &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
+    Status = gBS->InstallMultipleProtocolInterfaces (
+                    &Handle,
+                    &gEdkiiPlatformLogoProtocolGuid,
+                    &mPlatformLogo,
+                    NULL
+                    );
   }
+
   return Status;
 }

edk2-rockchip/Platform/Ameridroid/IndiedroidNova/DeviceTree/Mainline.inf

@@ -14,7 +14,7 @@
   VERSION_STRING                 = 1.0
 
 [Sources]
-  devicetree/mainline/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts
+  devicetree/mainline/rk3588s-indiedroid-nova-fixup.dts
 
 [Packages]
   MdePkg/MdePkg.dec

edk2-rockchip/Platform/Ameridroid/IndiedroidNova/IndiedroidNova.dsc

@@ -27,6 +27,9 @@
   FLASH_DEFINITION               = Silicon/Rockchip/RK3588/RK3588.fdf
   RK_PLATFORM_FVMAIN_MODULES     = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc
 
+  # GMAC is not exposed
+  DEFINE RK3588_GMAC_ENABLE = FALSE
+
   # No status LED on this platform.
   DEFINE RK_STATUS_LED_ENABLE = FALSE
 
@@ -74,13 +77,6 @@
   gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
   gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6
 
-  #
-  # CPU Performance default values
-  #
-  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX)
-  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX)
-  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX)
-
   #
   # PCIe/SATA/USB Combo PIPE PHY support flags and default values
   #
@@ -103,6 +99,14 @@
   #
   gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
 
+  #
+  # Display support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
+    VOP_OUTPUT_IF_HDMI0,
+    VOP_OUTPUT_IF_DP0
+  })}
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.

edk2-rockchip/Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -17,29 +17,29 @@
 #include <Soc.h>
 #include <VarStoreData.h>
 
-static struct regulator_init_data rk806_init_data[] = {
+static struct regulator_init_data  rk806_init_data[] = {
   /* Master PMIC */
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
- // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK4,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK5,  850000),
+  // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK7,  2000000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK8,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK10, 1800000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO2,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO4,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO5,  750000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO1,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO2,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO3,  1200000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO4,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO5,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO6,  1800000),
 
   /* No dual PMICs on this platform */
 };
@@ -51,9 +51,9 @@ SdmmcIoMux (
   )
 {
   /* sdmmc0 iomux (microSD socket) */
-  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
-  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
-  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+  BUS_IOC->GPIO4D_IOMUX_SEL_L  = (0xFFFFUL << 16) | (0x1111); // SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H  = (0x00FFUL << 16) | (0x0011); // SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); // SDMMC_DET
 }
 
 VOID
@@ -66,9 +66,9 @@ SdhciEmmcIoMux (
   /* Do not override, set by earlier boot stages. */
 }
 
-#define NS_CRU_BASE         0xFD7C0000
-#define CRU_CLKSEL_CON59    0x03EC
-#define CRU_CLKSEL_CON78    0x0438
+#define NS_CRU_BASE       0xFD7C0000
+#define CRU_CLKSEL_CON59  0x03EC
+#define CRU_CLKSEL_CON78  0x0438
 
 VOID
 EFIAPI
@@ -77,11 +77,11 @@ Rk806SpiIomux (
   )
 {
   /* io mux */
-  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
-  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  // BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  // BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
   PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
   PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+  MmioWrite32 (NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
 }
 
 VOID
@@ -90,24 +90,27 @@ Rk806Configure (
   VOID
   )
 {
-  UINTN RegCfgIndex;
+  UINTN  RegCfgIndex;
 
-  RK806Init();
+  RK806Init ();
 
-  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
-    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
+    RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
+  }
 }
 
 VOID
 EFIAPI
 SetCPULittleVoltage (
-  IN UINT32 Microvolts
+  IN UINT32  Microvolts
   )
 {
-  struct regulator_init_data Rk806CpuLittleSupply =
-        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+  struct regulator_init_data  Rk806CpuLittleSupply =
+    RK8XX_VOLTAGE_INIT (MASTER_BUCK2, Microvolts);
 
-  RK806RegulatorInit(Rk806CpuLittleSupply);
+  RK806RegulatorInit (Rk806CpuLittleSupply);
 }
 
 VOID
@@ -123,7 +126,7 @@ NorFspiIomux (
 VOID
 EFIAPI
 GmacIomux (
-  IN UINT32 Id
+  IN UINT32  Id
   )
 {
   /* No GMAC here */
@@ -132,51 +135,51 @@ GmacIomux (
 VOID
 EFIAPI
 NorFspiEnableClock (
-  UINT32 *CruBase
+  UINT32  *CruBase
   )
 {
-  UINTN BaseAddr = (UINTN) CruBase;
+  UINTN  BaseAddr = (UINTN)CruBase;
 
-  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+  MmioWrite32 (BaseAddr + 0x087C, 0x0E000000);
 }
 
 VOID
 EFIAPI
 I2cIomux (
-   UINT32 id
+  UINT32  id
   )
 {
   switch (id) {
-  case 0:
-    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
-    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
-    break;
-  case 1:
-    break;
-  case 2:
-    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
-    break;
-  case 3:
-    break;
-  case 4:
-    GpioPinSetFunction(1, GPIO_PIN_PA3, 9); //i2c4_scl_m3
-    GpioPinSetFunction(1, GPIO_PIN_PA2, 9); //i2c4_sda_m3
-    break;
-  case 5:
-    GpioPinSetFunction(3, GPIO_PIN_PC7, 9); //i2c5_scl_m0
-    GpioPinSetFunction(3, GPIO_PIN_PD0, 9); //i2c5_sda_m0
-    break;
-  case 6:
-    GpioPinSetFunction(4, GPIO_PIN_PB1, 9); //i2c6_scl_m3
-    GpioPinSetFunction(4, GPIO_PIN_PB0, 9); //i2c6_sda_m3
-    break;
-  case 7:
-    GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0
-    GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0
-    break;
-  default:
-    break;
+    case 0:
+      GpioPinSetFunction (0, GPIO_PIN_PD1, 3); // i2c0_scl_m2
+      GpioPinSetFunction (0, GPIO_PIN_PD2, 3); // i2c0_sda_m2
+      break;
+    case 1:
+      break;
+    case 2:
+      GpioPinSetFunction (0, GPIO_PIN_PB7, 9); // i2c2_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC0, 9); // i2c2_sda_m0
+      break;
+    case 3:
+      break;
+    case 4:
+      GpioPinSetFunction (1, GPIO_PIN_PA3, 9); // i2c4_scl_m3
+      GpioPinSetFunction (1, GPIO_PIN_PA2, 9); // i2c4_sda_m3
+      break;
+    case 5:
+      GpioPinSetFunction (3, GPIO_PIN_PC7, 9); // i2c5_scl_m0
+      GpioPinSetFunction (3, GPIO_PIN_PD0, 9); // i2c5_sda_m0
+      break;
+    case 6:
+      GpioPinSetFunction (4, GPIO_PIN_PB1, 9); // i2c6_scl_m3
+      GpioPinSetFunction (4, GPIO_PIN_PB0, 9); // i2c6_sda_m3
+      break;
+    case 7:
+      GpioPinSetFunction (1, GPIO_PIN_PD0, 9); // i2c7_scl_m0
+      GpioPinSetFunction (1, GPIO_PIN_PD1, 9); // i2c7_sda_m0
+      break;
+    default:
+      break;
   }
 }
 
@@ -186,7 +189,7 @@ UsbPortPowerEnable (
   VOID
   )
 {
-  DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n"));
+  DEBUG ((DEBUG_INFO, "UsbPortPowerEnable called\n"));
 
   /* Set GPIO4 PA5 output high to enable USB-C VBUS */
   GpioPinWrite (4, GPIO_PIN_PA5, TRUE);
@@ -199,22 +202,23 @@ Usb2PhyResume (
   VOID
   )
 {
-  MmioWrite32(0xfd5d0008, 0x20000000);
-  MmioWrite32(0xfd5d4008, 0x20000000);
-  MmioWrite32(0xfd5d8008, 0x20000000);
-  MmioWrite32(0xfd5dc008, 0x20000000);
-  MmioWrite32(0xfd7f0a10, 0x07000700);
-  MmioWrite32(0xfd7f0a10, 0x07000000);
+  MmioWrite32 (0xfd5d0008, 0x20000000);
+  MmioWrite32 (0xfd5d4008, 0x20000000);
+  MmioWrite32 (0xfd5d8008, 0x20000000);
+  MmioWrite32 (0xfd5dc008, 0x20000000);
+  MmioWrite32 (0xfd7f0a10, 0x07000700);
+  MmioWrite32 (0xfd7f0a10, 0x07000000);
 }
 
 VOID
 EFIAPI
 PcieIoInit (
-  UINT32 Segment
+  UINT32  Segment
   )
 {
   /* Set reset to gpio output mode */
-  if(Segment == PCIE_SEGMENT_PCIE20L2) { // RTL8111
+  if (Segment == PCIE_SEGMENT_PCIE20L2) {
+    // RTL8111
     GpioPinSetDirection (3, GPIO_PIN_PD1, GPIO_PIN_OUTPUT);
   }
 }
@@ -222,8 +226,8 @@ PcieIoInit (
 VOID
 EFIAPI
 PciePowerEn (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
   /* nothing to power on */
@@ -232,21 +236,41 @@ PciePowerEn (
 VOID
 EFIAPI
 PciePeReset (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  if(Segment == PCIE_SEGMENT_PCIE20L2) {
+  if (Segment == PCIE_SEGMENT_PCIE20L2) {
     GpioPinWrite (3, GPIO_PIN_PD1, !Enable);
   }
 }
 
-PWM_DATA pwm_data = {
+VOID
+EFIAPI
+HdmiTxIomux (
+  IN UINT32  Id
+  )
+{
+  switch (Id) {
+    case 0:
+      GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
+      GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
+      GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
+      GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
+      break;
+  }
+}
+
+PWM_DATA  pwm_data = {
   .ControllerID = PWM_CONTROLLER2,
-  .ChannelID = PWM_CHANNEL3,
-  .PeriodNs = 4000000,
-  .DutyNs = 4000000,
-  .Polarity = FALSE,
+  .ChannelID    = PWM_CHANNEL3,
+  .PeriodNs     = 4000000,
+  .DutyNs       = 4000000,
+  .Polarity     = FALSE,
 }; // PWM2_CH3
 
 VOID
@@ -263,7 +287,7 @@ PwmFanIoSetup (
 VOID
 EFIAPI
 PwmFanSetSpeed (
-  IN UINT32 Percentage
+  IN UINT32  Percentage
   )
 {
   pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100;
@@ -282,7 +306,7 @@ PlatformInitLeds (
 VOID
 EFIAPI
 PlatformSetStatusLed (
-  IN BOOLEAN Enable
+  IN BOOLEAN  Enable
   )
 {
   // No controllable LEDs on this platform
@@ -291,13 +315,15 @@ PlatformSetStatusLed (
 CONST EFI_GUID *
 EFIAPI
 PlatformGetDtbFileGuid (
-  IN UINT32 CompatMode
+  IN UINT32  CompatMode
   )
 {
-  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+  STATIC CONST EFI_GUID  VendorDtbFileGuid = {
+    // DeviceTree/Vendor.inf
     0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
   };
-  STATIC CONST EFI_GUID MainlineDtbFileGuid = {       // DeviceTree/Mainline.inf
+  STATIC CONST EFI_GUID  MainlineDtbFileGuid = {
+    // DeviceTree/Mainline.inf
     0x84492e97, 0xa10f, 0x49a7, { 0x85, 0xe9, 0x02, 0x5d, 0x19, 0x66, 0xb3, 0x43 }
   };
 
@@ -318,5 +344,5 @@ PlatformEarlyInit (
   )
 {
   // Configure various things specific to this platform
-  GpioPinSetFunction(4, GPIO_PIN_PA7, 0); //jdet
+  GpioPinSetFunction (4, GPIO_PIN_PA7, 0); // jdet
 }

edk2-rockchip/Platform/BuzzTV/Drivers/LogoDxe/Logo.c

@@ -19,15 +19,15 @@
 #include <Library/DebugLib.h>
 
 typedef struct {
-  EFI_IMAGE_ID                          ImageId;
-  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
-  INTN                                  OffsetX;
-  INTN                                  OffsetY;
+  EFI_IMAGE_ID                             ImageId;
+  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE    Attribute;
+  INTN                                     OffsetX;
+  INTN                                     OffsetY;
 } LOGO_ENTRY;
 
-STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
-STATIC EFI_HII_HANDLE            mHiiHandle;
-STATIC LOGO_ENTRY                mLogos[] = {
+STATIC EFI_HII_IMAGE_EX_PROTOCOL  *mHiiImageEx;
+STATIC EFI_HII_HANDLE             mHiiHandle;
+STATIC LOGO_ENTRY                 mLogos[] = {
   {
     IMAGE_TOKEN (IMG_LOGO),
     EdkiiPlatformLogoDisplayAttributeCenter,
@@ -53,18 +53,19 @@ STATIC
 EFI_STATUS
 EFIAPI
 GetImage (
-  IN     EDKII_PLATFORM_LOGO_PROTOCOL          *This,
-  IN OUT UINT32                                *Instance,
-     OUT EFI_IMAGE_INPUT                       *Image,
-     OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
-     OUT INTN                                  *OffsetX,
-     OUT INTN                                  *OffsetY
+  IN     EDKII_PLATFORM_LOGO_PROTOCOL        *This,
+  IN OUT UINT32                              *Instance,
+  OUT EFI_IMAGE_INPUT                        *Image,
+  OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE  *Attribute,
+  OUT INTN                                   *OffsetX,
+  OUT INTN                                   *OffsetY
   )
 {
-  UINT32 Current;
+  UINT32  Current;
 
-  if (Instance == NULL || Image == NULL ||
-      Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
+  if ((Instance == NULL) || (Image == NULL) ||
+      (Attribute == NULL) || (OffsetX == NULL) || (OffsetY == NULL))
+  {
     return EFI_INVALID_PARAMETER;
   }
 
@@ -78,11 +79,15 @@ GetImage (
   *OffsetX   = mLogos[Current].OffsetX;
   *OffsetY   = mLogos[Current].OffsetY;
 
-  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
-                        mLogos[Current].ImageId, Image);
+  return mHiiImageEx->GetImageEx (
+                        mHiiImageEx,
+                        mHiiHandle,
+                        mLogos[Current].ImageId,
+                        Image
+                        );
 }
 
-STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+STATIC EDKII_PLATFORM_LOGO_PROTOCOL  mPlatformLogo = {
   GetImage
 };
 
@@ -101,44 +106,66 @@ STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
 EFI_STATUS
 EFIAPI
 InitializeLogo (
-  IN EFI_HANDLE               ImageHandle,
-  IN EFI_SYSTEM_TABLE         *SystemTable
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
-  EFI_STATUS                  Status;
-  EFI_HII_PACKAGE_LIST_HEADER *PackageList;
-  EFI_HII_DATABASE_PROTOCOL   *HiiDatabase;
-  EFI_HANDLE                  Handle;
+  EFI_STATUS                   Status;
+  EFI_HII_PACKAGE_LIST_HEADER  *PackageList;
+  EFI_HII_DATABASE_PROTOCOL    *HiiDatabase;
+  EFI_HANDLE                   Handle;
 
-  Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
-                  (VOID **) &HiiDatabase);
+  Status = gBS->LocateProtocol (
+                  &gEfiHiiDatabaseProtocolGuid,
+                  NULL,
+                  (VOID **)&HiiDatabase
+                  );
   ASSERT_EFI_ERROR (Status);
 
-  Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
-                  (VOID **) &mHiiImageEx);
+  Status = gBS->LocateProtocol (
+                  &gEfiHiiImageExProtocolGuid,
+                  NULL,
+                  (VOID **)&mHiiImageEx
+                  );
   ASSERT_EFI_ERROR (Status);
 
   //
   // Retrieve HII package list from ImageHandle
   //
-  Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
-                  (VOID **) &PackageList, ImageHandle, NULL,
-                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+  Status = gBS->OpenProtocol (
+                  ImageHandle,
+                  &gEfiHiiPackageListProtocolGuid,
+                  (VOID **)&PackageList,
+                  ImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
   if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR,
-      "HII Image Package with logo not found in PE/COFF resource section\n"));
+    DEBUG ((
+      DEBUG_ERROR,
+      "HII Image Package with logo not found in PE/COFF resource section\n"
+      ));
     return Status;
   }
 
   //
   // Publish HII package list to HII Database.
   //
-  Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
-                          &mHiiHandle);
+  Status = HiiDatabase->NewPackageList (
+                          HiiDatabase,
+                          PackageList,
+                          NULL,
+                          &mHiiHandle
+                          );
   if (!EFI_ERROR (Status)) {
     Handle = NULL;
-    Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
-                    &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
+    Status = gBS->InstallMultipleProtocolInterfaces (
+                    &Handle,
+                    &gEdkiiPlatformLogoProtocolGuid,
+                    &mPlatformLogo,
+                    NULL
+                    );
   }
+
   return Status;
 }

edk2-rockchip/Platform/BuzzTV/PowerStation6/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -16,29 +16,29 @@
 #include <Soc.h>
 #include <VarStoreData.h>
 
-static struct regulator_init_data rk806_init_data[] = {
+static struct regulator_init_data  rk806_init_data[] = {
   /* Master PMIC */
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
-  //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK4,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK5,  850000),
+  // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK7,  2000000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK8,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK10, 1800000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 837500),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO2,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO3,  837500),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO4,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO5,  750000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO1,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO2,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO3,  1200000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO4,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO5,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO6,  1800000),
 
   /* No dual PMICs on this platform */
 };
@@ -50,9 +50,9 @@ SdmmcIoMux (
   )
 {
   /* sdmmc0 iomux (microSD socket) */
-  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
-  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
-  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+  BUS_IOC->GPIO4D_IOMUX_SEL_L  = (0xFFFFUL << 16) | (0x1111); // SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H  = (0x00FFUL << 16) | (0x0011); // SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); // SDMMC_DET
 
   /* vcc_3v3_sd_s0 */
   GpioPinWrite (4, GPIO_PIN_PA5, TRUE);
@@ -66,14 +66,14 @@ SdhciEmmcIoMux (
   )
 {
   /* sdmmc0 iomux */
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); // EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
 }
 
-#define NS_CRU_BASE         0xFD7C0000
-#define CRU_CLKSEL_CON59    0x03EC
-#define CRU_CLKSEL_CON78    0x0438
+#define NS_CRU_BASE       0xFD7C0000
+#define CRU_CLKSEL_CON59  0x03EC
+#define CRU_CLKSEL_CON78  0x0438
 
 VOID
 EFIAPI
@@ -82,11 +82,11 @@ Rk806SpiIomux (
   )
 {
   /* io mux */
-  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
-  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  // BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  // BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
   PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
   PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+  MmioWrite32 (NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
 }
 
 VOID
@@ -95,24 +95,27 @@ Rk806Configure (
   VOID
   )
 {
-  UINTN RegCfgIndex;
+  UINTN  RegCfgIndex;
 
-  RK806Init();
+  RK806Init ();
 
-  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
-    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
+    RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
+  }
 }
 
 VOID
 EFIAPI
 SetCPULittleVoltage (
-  IN UINT32 Microvolts
+  IN UINT32  Microvolts
   )
 {
-  struct regulator_init_data Rk806CpuLittleSupply =
-        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+  struct regulator_init_data  Rk806CpuLittleSupply =
+    RK8XX_VOLTAGE_INIT (MASTER_BUCK2, Microvolts);
 
-  RK806RegulatorInit(Rk806CpuLittleSupply);
+  RK806RegulatorInit (Rk806CpuLittleSupply);
 }
 
 VOID
@@ -122,31 +125,33 @@ NorFspiIomux (
   )
 {
   /* io mux */
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
-             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
-#define FSPI_M1
-#if defined(FSPI_M0)
-   /*FSPI M0*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
-#elif defined(FSPI_M1)
+  MmioWrite32 (
+    NS_CRU_BASE + CRU_CLKSEL_CON78,
+    (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)
+    );
+  #define FSPI_M1
+ #if defined (FSPI_M0)
+  /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0);   // FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222);     // FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); // FSPI_CS0N_M0
+ #elif defined (FSPI_M1)
   /*FSPI M1*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
-#else
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); // FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); // FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3);         // FSPI_CS0N_M1
+ #else
   /*FSPI M2*/
-  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
-  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
-  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
-#endif
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); // [FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50);     // FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2);         // FSPI_CS0_M2
+ #endif
 }
 
 VOID
 EFIAPI
 GmacIomux (
-  IN UINT32 Id
+  IN UINT32  Id
   )
 {
   switch (Id) {
@@ -186,45 +191,45 @@ GmacIoPhyReset (
 VOID
 EFIAPI
 NorFspiEnableClock (
-  UINT32 *CruBase
+  UINT32  *CruBase
   )
 {
-  UINTN BaseAddr = (UINTN) CruBase;
+  UINTN  BaseAddr = (UINTN)CruBase;
 
-  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+  MmioWrite32 (BaseAddr + 0x087C, 0x0E000000);
 }
 
 VOID
 EFIAPI
 I2cIomux (
-   UINT32 id
+  UINT32  id
   )
 {
   switch (id) {
-  case 0:
-    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
-    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
-    break;
-  case 1:
-    GpioPinSetFunction(0, GPIO_PIN_PD4, 9); //i2c1_scl_m2
-    GpioPinSetFunction(0, GPIO_PIN_PD5, 9); //i2c1_sda_m2
-    break;
-  case 2:
-    break;
-  case 3:
-    break;
-  case 4:
-    break;
-  case 5:
-    break;
-  case 6:
-    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
-    break;
-  case 7:
-    break;
-  default:
-    break;
+    case 0:
+      GpioPinSetFunction (0, GPIO_PIN_PD1, 3); // i2c0_scl_m2
+      GpioPinSetFunction (0, GPIO_PIN_PD2, 3); // i2c0_sda_m2
+      break;
+    case 1:
+      GpioPinSetFunction (0, GPIO_PIN_PD4, 9); // i2c1_scl_m2
+      GpioPinSetFunction (0, GPIO_PIN_PD5, 9); // i2c1_sda_m2
+      break;
+    case 2:
+      break;
+    case 3:
+      break;
+    case 4:
+      break;
+    case 5:
+      break;
+    case 6:
+      GpioPinSetFunction (0, GPIO_PIN_PD0, 9); // i2c6_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC7, 9); // i2c6_sda_m0
+      break;
+    case 7:
+      break;
+    default:
+      break;
   }
 }
 
@@ -234,10 +239,10 @@ UsbPortPowerEnable (
   VOID
   )
 {
-  DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n"));
+  DEBUG ((DEBUG_INFO, "UsbPortPowerEnable called\n"));
 
   /* vcc5v0-host */
-  GpioPinWrite(4, GPIO_PIN_PB0, TRUE);
+  GpioPinWrite (4, GPIO_PIN_PB0, TRUE);
   GpioPinSetDirection (4, GPIO_PIN_PB0, GPIO_PIN_OUTPUT);
 }
 
@@ -247,21 +252,21 @@ Usb2PhyResume (
   VOID
   )
 {
-  MmioWrite32(0xfd5d0008, 0x20000000);
-  MmioWrite32(0xfd5d4008, 0x20000000);
-  MmioWrite32(0xfd5d8008, 0x20000000);
-  MmioWrite32(0xfd5dc008, 0x20000000);
-  MmioWrite32(0xfd7f0a10, 0x07000700);
-  MmioWrite32(0xfd7f0a10, 0x07000000);
+  MmioWrite32 (0xfd5d0008, 0x20000000);
+  MmioWrite32 (0xfd5d4008, 0x20000000);
+  MmioWrite32 (0xfd5d8008, 0x20000000);
+  MmioWrite32 (0xfd5dc008, 0x20000000);
+  MmioWrite32 (0xfd7f0a10, 0x07000700);
+  MmioWrite32 (0xfd7f0a10, 0x07000000);
 }
 
 VOID
 EFIAPI
 PcieIoInit (
-  UINT32 Segment
+  UINT32  Segment
   )
 {
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4: // M.2 M Key
       /* reset */
       GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
@@ -280,11 +285,11 @@ PcieIoInit (
 VOID
 EFIAPI
 PciePowerEn (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4:
       GpioPinWrite (2, GPIO_PIN_PC5, Enable);
       break;
@@ -298,11 +303,11 @@ PciePowerEn (
 VOID
 EFIAPI
 PciePeReset (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4:
       GpioPinWrite (4, GPIO_PIN_PB6, !Enable);
       break;
@@ -314,6 +319,26 @@ PciePeReset (
   }
 }
 
+VOID
+EFIAPI
+HdmiTxIomux (
+  IN UINT32  Id
+  )
+{
+  switch (Id) {
+    case 0:
+      GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
+      GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (3, GPIO_PIN_PD4, 3); // hdmim1_tx0_hpd
+      GpioPinSetPull (3, GPIO_PIN_PD4, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
+      GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
+      GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
+      break;
+  }
+}
+
 VOID
 EFIAPI
 PwmFanIoSetup (
@@ -325,7 +350,7 @@ PwmFanIoSetup (
 VOID
 EFIAPI
 PwmFanSetSpeed (
-  IN UINT32 Percentage
+  IN UINT32  Percentage
   )
 {
 }
@@ -347,7 +372,7 @@ PlatformInitLeds (
 VOID
 EFIAPI
 PlatformSetStatusLed (
-  IN BOOLEAN Enable
+  IN BOOLEAN  Enable
   )
 {
   GpioPinWrite (3, GPIO_PIN_PD0, !Enable);
@@ -357,13 +382,15 @@ PlatformSetStatusLed (
 CONST EFI_GUID *
 EFIAPI
 PlatformGetDtbFileGuid (
-  IN UINT32 CompatMode
+  IN UINT32  CompatMode
   )
 {
-  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+  STATIC CONST EFI_GUID  VendorDtbFileGuid = {
+    // DeviceTree/Vendor.inf
     0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
   };
-  STATIC CONST EFI_GUID MainlineDtbFileGuid = {       // DeviceTree/Mainline.inf
+  STATIC CONST EFI_GUID  MainlineDtbFileGuid = {
+    // DeviceTree/Mainline.inf
     0x84492e97, 0xa10f, 0x49a7, { 0x85, 0xe9, 0x02, 0x5d, 0x19, 0x66, 0xb3, 0x43 }
   };
 

edk2-rockchip/Platform/BuzzTV/PowerStation6/PowerStation6.dsc

@@ -71,13 +71,6 @@
   gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
   gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6
 
-  #
-  # CPU Performance default values
-  #
-  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX)
-  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX)
-  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX)
-
   #
   # PCIe/SATA/USB Combo PIPE PHY support flags and default values
   #
@@ -102,6 +95,14 @@
   gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE
   gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x43
 
+  #
+  # Display support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
+    VOP_OUTPUT_IF_HDMI0,
+    VOP_OUTPUT_IF_DP0
+  })}
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.

edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc.inc

@@ -72,13 +72,6 @@
   gRockchipTokenSpaceGuid.PcdPca9555Address|0x21
   gRockchipTokenSpaceGuid.PcdPca9555Bus|0x6
 
-  #
-  # CPU Performance default values
-  #
-  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-
   #
   # PCIe/SATA/USB Combo PIPE PHY support flags and default values
   #
@@ -115,6 +108,15 @@
   #
   gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
 
+  #
+  # Display support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
+    VOP_OUTPUT_IF_HDMI0,
+    VOP_OUTPUT_IF_DP0,
+    VOP_OUTPUT_IF_DP1
+  })}
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.

edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -20,29 +20,29 @@
 
 #include <Protocol/Pca9555.h>
 
-static struct regulator_init_data rk806_init_data[] = {
+static struct regulator_init_data  rk806_init_data[] = {
   /* Master PMIC */
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
- // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK4,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK5,  850000),
+  // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK7,  2000000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK8,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK10, 1800000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO2,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO4,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO5,  750000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO1,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO2,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO3,  1200000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO4,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO5,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO6,  1800000),
 
   /* No dual PMICs on this platform */
 };
@@ -50,39 +50,45 @@ static struct regulator_init_data rk806_init_data[] = {
 EFI_STATUS
 EFIAPI
 GetPca9555Protocol (
-  IN OUT PCA95XX_PROTOCOL        **Pca95xxProtocl
+  IN OUT PCA95XX_PROTOCOL  **Pca95xxProtocl
   )
 {
-  EFI_HANDLE          *HandleBuffer;
-  EFI_STATUS           Status;
-  UINTN                HandleCount;
+  EFI_HANDLE  *HandleBuffer;
+  EFI_STATUS  Status;
+  UINTN       HandleCount;
 
   /* Locate Handles of all PCA95XX_PROTOCOL producers */
-  Status = gBS->LocateHandleBuffer (ByProtocol,
+  Status = gBS->LocateHandleBuffer (
+                  ByProtocol,
                   &gPca95xxProtocolGuid,
                   NULL,
                   &HandleCount,
-                  &HandleBuffer);
+                  &HandleBuffer
+                  );
   if (EFI_ERROR (Status)) {
     DEBUG ((DEBUG_ERROR, "%a: Unable to locate handles\n", __FUNCTION__));
     return Status;
   }
 
-  DEBUG ((DEBUG_INFO,
-          "%a: got %d PCA95XX_PROTOCOLs\n",
-          __FUNCTION__,
-          HandleCount));
+  DEBUG ((
+    DEBUG_INFO,
+    "%a: got %d PCA95XX_PROTOCOLs\n",
+    __FUNCTION__,
+    HandleCount
+    ));
 
   /*
    * Open Pca95xxProtocl. With EFI_OPEN_PROTOCOL_GET_PROTOCOL attribute
    * the consumer is not obliged to call CloseProtocol.
    */
-  Status = gBS->OpenProtocol (HandleBuffer[0],
+  Status = gBS->OpenProtocol (
+                  HandleBuffer[0],
                   &gPca95xxProtocolGuid,
                   (VOID **)Pca95xxProtocl,
                   HandleBuffer[0],
                   NULL,
-                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
 
   return Status;
 }
@@ -94,9 +100,9 @@ SdmmcIoMux (
   )
 {
   /* sdmmc0 iomux (microSD socket) */
-  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
-  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
-  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+  BUS_IOC->GPIO4D_IOMUX_SEL_L  = (0xFFFFUL << 16) | (0x1111); // SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H  = (0x00FFUL << 16) | (0x0011); // SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); // SDMMC_DET
 }
 
 VOID
@@ -109,9 +115,9 @@ SdhciEmmcIoMux (
   /* Do not override, set by earlier boot stages. */
 }
 
-#define NS_CRU_BASE         0xFD7C0000
-#define CRU_CLKSEL_CON59    0x03EC
-#define CRU_CLKSEL_CON78    0x0438
+#define NS_CRU_BASE       0xFD7C0000
+#define CRU_CLKSEL_CON59  0x03EC
+#define CRU_CLKSEL_CON78  0x0438
 
 VOID
 EFIAPI
@@ -120,11 +126,11 @@ Rk806SpiIomux (
   )
 {
   /* io mux */
-  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
-  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  // BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  // BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
   PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
   PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+  MmioWrite32 (NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
 }
 
 VOID
@@ -133,24 +139,27 @@ Rk806Configure (
   VOID
   )
 {
-  UINTN RegCfgIndex;
+  UINTN  RegCfgIndex;
 
-  RK806Init();
+  RK806Init ();
 
-  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
-    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
+    RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
+  }
 }
 
 VOID
 EFIAPI
 SetCPULittleVoltage (
-  IN UINT32 Microvolts
+  IN UINT32  Microvolts
   )
 {
-  struct regulator_init_data Rk806CpuLittleSupply =
-        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+  struct regulator_init_data  Rk806CpuLittleSupply =
+    RK8XX_VOLTAGE_INIT (MASTER_BUCK2, Microvolts);
 
-  RK806RegulatorInit(Rk806CpuLittleSupply);
+  RK806RegulatorInit (Rk806CpuLittleSupply);
 }
 
 VOID
@@ -166,7 +175,7 @@ NorFspiIomux (
 VOID
 EFIAPI
 GmacIomux (
-  IN UINT32 Id
+  IN UINT32  Id
   )
 {
   switch (Id) {
@@ -222,39 +231,39 @@ GmacIoPhyReset (
 VOID
 EFIAPI
 NorFspiEnableClock (
-  UINT32 *CruBase
+  UINT32  *CruBase
   )
 {
-  UINTN BaseAddr = (UINTN) CruBase;
+  UINTN  BaseAddr = (UINTN)CruBase;
 
-  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+  MmioWrite32 (BaseAddr + 0x087C, 0x0E000000);
 }
 
 VOID
 EFIAPI
 I2cIomux (
-   UINT32 id
+  UINT32  id
   )
 {
   switch (id) {
-  case 0:
-    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); // I2C0_SCL_M2
-    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); // I2C0_SDA_M2
-    break;
-  case 1:
-    GpioPinSetFunction(0, GPIO_PIN_PD4, 9); // I2C1_SCL_M2
-    GpioPinSetFunction(0, GPIO_PIN_PD5, 9); // I2C1_SDA_M2
-    break;
-  case 3:
-    GpioPinSetFunction(1, GPIO_PIN_PC1, 9); // I2C3_SCL_M0
-    GpioPinSetFunction(1, GPIO_PIN_PC0, 9); // I2C3_SDA_M0
-    break;
-  case 6:
-    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); // I2C6_SCL_M0
-    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); // I2C6_SDA_M0
-    break;
-  default:
-    break;
+    case 0:
+      GpioPinSetFunction (0, GPIO_PIN_PD1, 3); // I2C0_SCL_M2
+      GpioPinSetFunction (0, GPIO_PIN_PD2, 3); // I2C0_SDA_M2
+      break;
+    case 1:
+      GpioPinSetFunction (0, GPIO_PIN_PD4, 9); // I2C1_SCL_M2
+      GpioPinSetFunction (0, GPIO_PIN_PD5, 9); // I2C1_SDA_M2
+      break;
+    case 3:
+      GpioPinSetFunction (1, GPIO_PIN_PC1, 9); // I2C3_SCL_M0
+      GpioPinSetFunction (1, GPIO_PIN_PC0, 9); // I2C3_SDA_M0
+      break;
+    case 6:
+      GpioPinSetFunction (0, GPIO_PIN_PD0, 9); // I2C6_SCL_M0
+      GpioPinSetFunction (0, GPIO_PIN_PC7, 9); // I2C6_SDA_M0
+      break;
+    default:
+      break;
   }
 }
 
@@ -264,53 +273,53 @@ UsbPortPowerEnable (
   VOID
   )
 {
-  EFI_STATUS Status = EFI_SUCCESS;
-  PCA95XX_PROTOCOL *Pca95xxProtocol;
+  EFI_STATUS        Status = EFI_SUCCESS;
+  PCA95XX_PROTOCOL  *Pca95xxProtocol;
 
   /* On Firefly AIO-3588Q this is controlled via the PCA9555. */
-  Status = GetPca9555Protocol(&Pca95xxProtocol);
-  if (EFI_ERROR(Status)) {
+  Status = GetPca9555Protocol (&Pca95xxProtocol);
+  if (EFI_ERROR (Status)) {
     DEBUG ((DEBUG_ERROR, "UsbPortPowerEnable failed to get PCA9555! (%d)\n", Status));
   } else {
     /* USB-C */
-    Pca95xxProtocol->GpioProtocol.Set(
-      &Pca95xxProtocol->GpioProtocol,
-      12, /* vbus5v0_typec_pwr_en */
-      GPIO_MODE_OUTPUT_0
-    );
+    Pca95xxProtocol->GpioProtocol.Set (
+                                    &Pca95xxProtocol->GpioProtocol,
+                                    12, /* vbus5v0_typec_pwr_en */
+                                    GPIO_MODE_OUTPUT_0
+                                    );
 
-    gBS->Stall(1200000);
+    gBS->Stall (1200000);
 
-    Pca95xxProtocol->GpioProtocol.Set(
-      &Pca95xxProtocol->GpioProtocol,
-      12, /* vbus5v0_typec_pwr_en */
-      GPIO_MODE_OUTPUT_1
-    );
+    Pca95xxProtocol->GpioProtocol.Set (
+                                    &Pca95xxProtocol->GpioProtocol,
+                                    12, /* vbus5v0_typec_pwr_en */
+                                    GPIO_MODE_OUTPUT_1
+                                    );
 
     /* other USB stuff */
-    Pca95xxProtocol->GpioProtocol.Set(
-      &Pca95xxProtocol->GpioProtocol,
-      5, /* vcc5v0_host */
-      GPIO_MODE_OUTPUT_1
-    );
+    Pca95xxProtocol->GpioProtocol.Set (
+                                    &Pca95xxProtocol->GpioProtocol,
+                                    5, /* vcc5v0_host */
+                                    GPIO_MODE_OUTPUT_1
+                                    );
 
-    Pca95xxProtocol->GpioProtocol.Set(
-      &Pca95xxProtocol->GpioProtocol,
-      4, /* vcc_hub_reset */
-      GPIO_MODE_OUTPUT_1
-    );
+    Pca95xxProtocol->GpioProtocol.Set (
+                                    &Pca95xxProtocol->GpioProtocol,
+                                    4, /* vcc_hub_reset */
+                                    GPIO_MODE_OUTPUT_1
+                                    );
 
-    Pca95xxProtocol->GpioProtocol.Set(
-      &Pca95xxProtocol->GpioProtocol,
-      6, /* vcc_hub3_reset */
-      GPIO_MODE_OUTPUT_1
-    );
+    Pca95xxProtocol->GpioProtocol.Set (
+                                    &Pca95xxProtocol->GpioProtocol,
+                                    6, /* vcc_hub3_reset */
+                                    GPIO_MODE_OUTPUT_1
+                                    );
 
-    Pca95xxProtocol->GpioProtocol.Set(
-      &Pca95xxProtocol->GpioProtocol,
-      7, /* vcc5v0_host3 */
-      GPIO_MODE_OUTPUT_1
-    );
+    Pca95xxProtocol->GpioProtocol.Set (
+                                    &Pca95xxProtocol->GpioProtocol,
+                                    7, /* vcc5v0_host3 */
+                                    GPIO_MODE_OUTPUT_1
+                                    );
   }
 }
 
@@ -320,95 +329,116 @@ Usb2PhyResume (
   VOID
   )
 {
-  MmioWrite32(0xfd5d0008, 0x20000000);
-  MmioWrite32(0xfd5d4008, 0x20000000);
-  MmioWrite32(0xfd5d8008, 0x20000000);
-  MmioWrite32(0xfd5dc008, 0x20000000);
-  MmioWrite32(0xfd7f0a10, 0x07000700);
-  MmioWrite32(0xfd7f0a10, 0x07000000);
+  MmioWrite32 (0xfd5d0008, 0x20000000);
+  MmioWrite32 (0xfd5d4008, 0x20000000);
+  MmioWrite32 (0xfd5d8008, 0x20000000);
+  MmioWrite32 (0xfd5dc008, 0x20000000);
+  MmioWrite32 (0xfd7f0a10, 0x07000700);
+  MmioWrite32 (0xfd7f0a10, 0x07000000);
 }
 
 VOID
 EFIAPI
 PcieIoInit (
-  UINT32 Segment
+  UINT32  Segment
   )
 {
   switch (Segment) {
-  case PCIE_SEGMENT_PCIE30X4:
-    GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT); // PCIE30X4_PERSTN_M1
-    GpioPinSetDirection (4, GPIO_PIN_PC6, GPIO_PIN_OUTPUT); // vcc3v3_pcie30
-    break;
-  case PCIE_SEGMENT_PCIE20L0:
-    GpioPinSetDirection (1, GPIO_PIN_PB4, GPIO_PIN_OUTPUT);
-    break;
-  case PCIE_SEGMENT_PCIE20L1:
-    break;
-  case PCIE_SEGMENT_PCIE20L2:
-    break;
+    case PCIE_SEGMENT_PCIE30X4:
+      GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT); // PCIE30X4_PERSTN_M1
+      GpioPinSetDirection (4, GPIO_PIN_PC6, GPIO_PIN_OUTPUT); // vcc3v3_pcie30
+      break;
+    case PCIE_SEGMENT_PCIE20L0:
+      GpioPinSetDirection (1, GPIO_PIN_PB4, GPIO_PIN_OUTPUT);
+      break;
+    case PCIE_SEGMENT_PCIE20L1:
+      break;
+    case PCIE_SEGMENT_PCIE20L2:
+      break;
   }
 }
 
 VOID
 EFIAPI
 PciePowerEn (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
   switch (Segment) {
-  case PCIE_SEGMENT_PCIE30X4:
-    GpioPinWrite (4, GPIO_PIN_PC6, Enable); // vcc3v3_pcie30
-    break;
-  case PCIE_SEGMENT_PCIE20L0:
-    break;
-  case PCIE_SEGMENT_PCIE20L1:
-    break;
-  case PCIE_SEGMENT_PCIE20L2:
-    break;
+    case PCIE_SEGMENT_PCIE30X4:
+      GpioPinWrite (4, GPIO_PIN_PC6, Enable); // vcc3v3_pcie30
+      break;
+    case PCIE_SEGMENT_PCIE20L0:
+      break;
+    case PCIE_SEGMENT_PCIE20L1:
+      break;
+    case PCIE_SEGMENT_PCIE20L2:
+      break;
   }
 }
 
 VOID
 EFIAPI
 PciePeReset (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  EFI_STATUS Status = EFI_SUCCESS;
-  PCA95XX_PROTOCOL *Pca95xxProtocol;
+  EFI_STATUS        Status = EFI_SUCCESS;
+  PCA95XX_PROTOCOL  *Pca95xxProtocol;
 
   switch (Segment) {
-  case PCIE_SEGMENT_PCIE30X4:
-    GpioPinWrite (4, GPIO_PIN_PB6, !Enable); // PCIE30X4_PERSTN_M1
-    break;
-  case PCIE_SEGMENT_PCIE20L0:
-    GpioPinWrite (1, GPIO_PIN_PB4, !Enable);
-    break;
-  case PCIE_SEGMENT_PCIE20L1:
-    break;
-  case PCIE_SEGMENT_PCIE20L2:
-    Status = GetPca9555Protocol(&Pca95xxProtocol);
-    if (EFI_ERROR(Status)) {
-      DEBUG ((DEBUG_ERROR, "PciePeReset(L2) failed to get PCA9555! (%d)\n", Status));
-    } else {
-      Pca95xxProtocol->GpioProtocol.Set(
-        &Pca95xxProtocol->GpioProtocol,
-        14, /* PCA_IO1_6 */
-        Enable ? GPIO_MODE_OUTPUT_0 : GPIO_MODE_OUTPUT_1
-      );
-    }
-    break;
+    case PCIE_SEGMENT_PCIE30X4:
+      GpioPinWrite (4, GPIO_PIN_PB6, !Enable); // PCIE30X4_PERSTN_M1
+      break;
+    case PCIE_SEGMENT_PCIE20L0:
+      GpioPinWrite (1, GPIO_PIN_PB4, !Enable);
+      break;
+    case PCIE_SEGMENT_PCIE20L1:
+      break;
+    case PCIE_SEGMENT_PCIE20L2:
+      Status = GetPca9555Protocol (&Pca95xxProtocol);
+      if (EFI_ERROR (Status)) {
+        DEBUG ((DEBUG_ERROR, "PciePeReset(L2) failed to get PCA9555! (%d)\n", Status));
+      } else {
+        Pca95xxProtocol->GpioProtocol.Set (
+                                        &Pca95xxProtocol->GpioProtocol,
+                                        14, /* PCA_IO1_6 */
+                                        Enable ? GPIO_MODE_OUTPUT_0 : GPIO_MODE_OUTPUT_1
+                                        );
+      }
+
+      break;
   }
 }
 
-PWM_DATA pwm_data = {
+VOID
+EFIAPI
+HdmiTxIomux (
+  IN UINT32  Id
+  )
+{
+  switch (Id) {
+    case 0:
+      GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
+      GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
+      GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
+      GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
+      break;
+  }
+}
+
+PWM_DATA  pwm_data = {
   .ControllerID = PWM_CONTROLLER3,
-  .ChannelID = PWM_CHANNEL3,
-  .PeriodNs = 50000,
-  .DutyNs = 50000,
-  .Polarity = FALSE,
+  .ChannelID    = PWM_CHANNEL3,
+  .PeriodNs     = 50000,
+  .DutyNs       = 50000,
+  .Polarity     = FALSE,
 }; // PWM15
 
 VOID
@@ -425,7 +455,7 @@ PwmFanIoSetup (
 VOID
 EFIAPI
 PwmFanSetSpeed (
-  IN UINT32 Percentage
+  IN UINT32  Percentage
   )
 {
   pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100;
@@ -445,7 +475,7 @@ PlatformInitLeds (
 VOID
 EFIAPI
 PlatformSetStatusLed (
-  IN BOOLEAN Enable
+  IN BOOLEAN  Enable
   )
 {
   GpioPinWrite (3, GPIO_PIN_PB2, Enable);
@@ -454,10 +484,11 @@ PlatformSetStatusLed (
 CONST EFI_GUID *
 EFIAPI
 PlatformGetDtbFileGuid (
-  IN UINT32 CompatMode
+  IN UINT32  CompatMode
   )
 {
-  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+  STATIC CONST EFI_GUID  VendorDtbFileGuid = {
+    // DeviceTree/Vendor.inf
     0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
   };
 

edk2-rockchip/Platform/Firefly/Drivers/LogoDxe/Logo.c

@@ -19,15 +19,15 @@
 #include <Library/DebugLib.h>
 
 typedef struct {
-  EFI_IMAGE_ID                          ImageId;
-  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
-  INTN                                  OffsetX;
-  INTN                                  OffsetY;
+  EFI_IMAGE_ID                             ImageId;
+  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE    Attribute;
+  INTN                                     OffsetX;
+  INTN                                     OffsetY;
 } LOGO_ENTRY;
 
-STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
-STATIC EFI_HII_HANDLE            mHiiHandle;
-STATIC LOGO_ENTRY                mLogos[] = {
+STATIC EFI_HII_IMAGE_EX_PROTOCOL  *mHiiImageEx;
+STATIC EFI_HII_HANDLE             mHiiHandle;
+STATIC LOGO_ENTRY                 mLogos[] = {
   {
     IMAGE_TOKEN (IMG_LOGO),
     EdkiiPlatformLogoDisplayAttributeCenter,
@@ -53,18 +53,19 @@ STATIC
 EFI_STATUS
 EFIAPI
 GetImage (
-  IN     EDKII_PLATFORM_LOGO_PROTOCOL          *This,
-  IN OUT UINT32                                *Instance,
-     OUT EFI_IMAGE_INPUT                       *Image,
-     OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
-     OUT INTN                                  *OffsetX,
-     OUT INTN                                  *OffsetY
+  IN     EDKII_PLATFORM_LOGO_PROTOCOL        *This,
+  IN OUT UINT32                              *Instance,
+  OUT EFI_IMAGE_INPUT                        *Image,
+  OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE  *Attribute,
+  OUT INTN                                   *OffsetX,
+  OUT INTN                                   *OffsetY
   )
 {
-  UINT32 Current;
+  UINT32  Current;
 
-  if (Instance == NULL || Image == NULL ||
-      Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
+  if ((Instance == NULL) || (Image == NULL) ||
+      (Attribute == NULL) || (OffsetX == NULL) || (OffsetY == NULL))
+  {
     return EFI_INVALID_PARAMETER;
   }
 
@@ -78,11 +79,15 @@ GetImage (
   *OffsetX   = mLogos[Current].OffsetX;
   *OffsetY   = mLogos[Current].OffsetY;
 
-  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
-                        mLogos[Current].ImageId, Image);
+  return mHiiImageEx->GetImageEx (
+                        mHiiImageEx,
+                        mHiiHandle,
+                        mLogos[Current].ImageId,
+                        Image
+                        );
 }
 
-STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+STATIC EDKII_PLATFORM_LOGO_PROTOCOL  mPlatformLogo = {
   GetImage
 };
 
@@ -101,44 +106,66 @@ STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
 EFI_STATUS
 EFIAPI
 InitializeLogo (
-  IN EFI_HANDLE               ImageHandle,
-  IN EFI_SYSTEM_TABLE         *SystemTable
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
-  EFI_STATUS                  Status;
-  EFI_HII_PACKAGE_LIST_HEADER *PackageList;
-  EFI_HII_DATABASE_PROTOCOL   *HiiDatabase;
-  EFI_HANDLE                  Handle;
+  EFI_STATUS                   Status;
+  EFI_HII_PACKAGE_LIST_HEADER  *PackageList;
+  EFI_HII_DATABASE_PROTOCOL    *HiiDatabase;
+  EFI_HANDLE                   Handle;
 
-  Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
-                  (VOID **) &HiiDatabase);
+  Status = gBS->LocateProtocol (
+                  &gEfiHiiDatabaseProtocolGuid,
+                  NULL,
+                  (VOID **)&HiiDatabase
+                  );
   ASSERT_EFI_ERROR (Status);
 
-  Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
-                  (VOID **) &mHiiImageEx);
+  Status = gBS->LocateProtocol (
+                  &gEfiHiiImageExProtocolGuid,
+                  NULL,
+                  (VOID **)&mHiiImageEx
+                  );
   ASSERT_EFI_ERROR (Status);
 
   //
   // Retrieve HII package list from ImageHandle
   //
-  Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
-                  (VOID **) &PackageList, ImageHandle, NULL,
-                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+  Status = gBS->OpenProtocol (
+                  ImageHandle,
+                  &gEfiHiiPackageListProtocolGuid,
+                  (VOID **)&PackageList,
+                  ImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
   if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR,
-      "HII Image Package with logo not found in PE/COFF resource section\n"));
+    DEBUG ((
+      DEBUG_ERROR,
+      "HII Image Package with logo not found in PE/COFF resource section\n"
+      ));
     return Status;
   }
 
   //
   // Publish HII package list to HII Database.
   //
-  Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
-                          &mHiiHandle);
+  Status = HiiDatabase->NewPackageList (
+                          HiiDatabase,
+                          PackageList,
+                          NULL,
+                          &mHiiHandle
+                          );
   if (!EFI_ERROR (Status)) {
     Handle = NULL;
-    Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
-                    &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
+    Status = gBS->InstallMultipleProtocolInterfaces (
+                    &Handle,
+                    &gEdkiiPlatformLogoProtocolGuid,
+                    &mPlatformLogo,
+                    NULL
+                    );
   }
+
   return Status;
 }

edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.dsc.inc

@@ -69,13 +69,6 @@
   gRockchipTokenSpaceGuid.PcdPca9555Address|0x21
   gRockchipTokenSpaceGuid.PcdPca9555Bus|0x6
 
-  #
-  # CPU Performance default values
-  #
-  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-
   #
   # PCIe/SATA/USB Combo PIPE PHY support flags and default values
   #
@@ -106,6 +99,16 @@
   #
   gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
 
+  #
+  # Display support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
+    VOP_OUTPUT_IF_HDMI0,
+    VOP_OUTPUT_IF_HDMI1,
+    VOP_OUTPUT_IF_DP0,
+    VOP_OUTPUT_IF_DP1
+  })}
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.

edk2-rockchip/Platform/Firefly/ITX-3588J/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -20,29 +20,29 @@
 
 #include <Protocol/Pca9555.h>
 
-static struct regulator_init_data rk806_init_data[] = {
+static struct regulator_init_data  rk806_init_data[] = {
   /* Master PMIC */
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
- // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK4,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK5,  850000),
+  // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK7,  2000000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK8,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK10, 1800000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO2,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO4,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO5,  750000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO1,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO2,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO3,  1200000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO4,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO5,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO6,  1800000),
 
   /* No dual PMICs on this platform */
 };
@@ -50,40 +50,45 @@ static struct regulator_init_data rk806_init_data[] = {
 EFI_STATUS
 EFIAPI
 GetPca9555Protocol (
-  IN OUT PCA95XX_PROTOCOL        **Pca95xxProtocl
+  IN OUT PCA95XX_PROTOCOL  **Pca95xxProtocl
   )
 {
-  EFI_HANDLE          *HandleBuffer;
-  EFI_STATUS           Status;
-  UINTN                HandleCount;
-  UINTN                Index;
+  EFI_HANDLE  *HandleBuffer;
+  EFI_STATUS  Status;
+  UINTN       HandleCount;
 
   /* Locate Handles of all PCA95XX_PROTOCOL producers */
-  Status = gBS->LocateHandleBuffer (ByProtocol,
+  Status = gBS->LocateHandleBuffer (
+                  ByProtocol,
                   &gPca95xxProtocolGuid,
                   NULL,
                   &HandleCount,
-                  &HandleBuffer);
+                  &HandleBuffer
+                  );
   if (EFI_ERROR (Status)) {
     DEBUG ((DEBUG_ERROR, "%a: Unable to locate handles\n", __FUNCTION__));
     return Status;
   }
 
-  DEBUG ((DEBUG_INFO,
-          "%a: got %d PCA95XX_PROTOCOLs\n",
-          __FUNCTION__,
-          HandleCount));
+  DEBUG ((
+    DEBUG_INFO,
+    "%a: got %d PCA95XX_PROTOCOLs\n",
+    __FUNCTION__,
+    HandleCount
+    ));
 
   /*
    * Open Pca95xxProtocl. With EFI_OPEN_PROTOCOL_GET_PROTOCOL attribute
    * the consumer is not obliged to call CloseProtocol.
    */
-  Status = gBS->OpenProtocol (HandleBuffer[0],
+  Status = gBS->OpenProtocol (
+                  HandleBuffer[0],
                   &gPca95xxProtocolGuid,
                   (VOID **)Pca95xxProtocl,
                   HandleBuffer[0],
                   NULL,
-                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
 
   return Status;
 }
@@ -95,9 +100,9 @@ SdmmcIoMux (
   )
 {
   /* sdmmc0 iomux (microSD socket) */
-  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
-  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
-  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+  BUS_IOC->GPIO4D_IOMUX_SEL_L  = (0xFFFFUL << 16) | (0x1111); // SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H  = (0x00FFUL << 16) | (0x0011); // SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); // SDMMC_DET
 }
 
 VOID
@@ -107,14 +112,14 @@ SdhciEmmcIoMux (
   )
 {
   /* sdmmc0 iomux */
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); // EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
 }
 
-#define NS_CRU_BASE         0xFD7C0000
-#define CRU_CLKSEL_CON59    0x03EC
-#define CRU_CLKSEL_CON78    0x0438
+#define NS_CRU_BASE       0xFD7C0000
+#define CRU_CLKSEL_CON59  0x03EC
+#define CRU_CLKSEL_CON78  0x0438
 
 VOID
 EFIAPI
@@ -123,11 +128,11 @@ Rk806SpiIomux (
   )
 {
   /* io mux */
-  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
-  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  // BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  // BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
   PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
   PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+  MmioWrite32 (NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
 }
 
 VOID
@@ -136,24 +141,27 @@ Rk806Configure (
   VOID
   )
 {
-  UINTN RegCfgIndex;
+  UINTN  RegCfgIndex;
 
-  RK806Init();
+  RK806Init ();
 
-  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
-    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
+    RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
+  }
 }
 
 VOID
 EFIAPI
 SetCPULittleVoltage (
-  IN UINT32 Microvolts
+  IN UINT32  Microvolts
   )
 {
-  struct regulator_init_data Rk806CpuLittleSupply =
-        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+  struct regulator_init_data  Rk806CpuLittleSupply =
+    RK8XX_VOLTAGE_INIT (MASTER_BUCK2, Microvolts);
 
-  RK806RegulatorInit(Rk806CpuLittleSupply);
+  RK806RegulatorInit (Rk806CpuLittleSupply);
 }
 
 VOID
@@ -163,31 +171,33 @@ NorFspiIomux (
   )
 {
   /* io mux */
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
-             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
-#define FSPI_M1
-#if defined(FSPI_M0)
-   /*FSPI M0*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
-#elif defined(FSPI_M1)
+  MmioWrite32 (
+    NS_CRU_BASE + CRU_CLKSEL_CON78,
+    (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)
+    );
+  #define FSPI_M1
+ #if defined (FSPI_M0)
+  /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0);   // FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222);     // FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); // FSPI_CS0N_M0
+ #elif defined (FSPI_M1)
   /*FSPI M1*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
-#else
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); // FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); // FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3);         // FSPI_CS0N_M1
+ #else
   /*FSPI M2*/
-  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
-  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
-  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
-#endif
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); // [FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50);     // FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2);         // FSPI_CS0_M2
+ #endif
 }
 
 VOID
 EFIAPI
 GmacIomux (
-  IN UINT32 Id
+  IN UINT32  Id
   )
 {
   switch (Id) {
@@ -243,53 +253,53 @@ GmacIoPhyReset (
 VOID
 EFIAPI
 NorFspiEnableClock (
-  UINT32 *CruBase
+  UINT32  *CruBase
   )
 {
-  UINTN BaseAddr = (UINTN) CruBase;
+  UINTN  BaseAddr = (UINTN)CruBase;
 
-  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+  MmioWrite32 (BaseAddr + 0x087C, 0x0E000000);
 }
 
 VOID
 EFIAPI
 I2cIomux (
-   UINT32 id
+  UINT32  id
   )
 {
   switch (id) {
-  case 0:
-    /* io mux M2 */
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
-    break;
-  case 1:
-    /* io mux */
-    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
-    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
-    break;
-  case 2:
-    /* io mux */
-    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
-    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
-    PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
-    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
-    break;
-  case 3:
-    break;
-  case 4:
-    break;
-  case 5:
-    break;
-  case 6:
-    /* io mux M0 */
-    BUS_IOC->GPIO0C_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
-    BUS_IOC->GPIO0D_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
-    PMU2_IOC->GPIO0C_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
-    break;
-  default:
-    break;
+    case 0:
+      /* io mux M2 */
+      PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
+      PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
+      break;
+    case 1:
+      /* io mux */
+      // BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
+      // PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
+      break;
+    case 2:
+      /* io mux */
+      BUS_IOC->GPIO0B_IOMUX_SEL_H  = (0xF000UL << 16) | 0x9000;
+      BUS_IOC->GPIO0C_IOMUX_SEL_L  = (0x000FUL << 16) | 0x0009;
+      PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
+      PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+      break;
+    case 3:
+      break;
+    case 4:
+      break;
+    case 5:
+      break;
+    case 6:
+      /* io mux M0 */
+      BUS_IOC->GPIO0C_IOMUX_SEL_H  = (0xF000UL << 16) | 0x9000;
+      BUS_IOC->GPIO0D_IOMUX_SEL_L  = (0x000FUL << 16) | 0x0009;
+      PMU2_IOC->GPIO0C_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
+      PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+      break;
+    default:
+      break;
   }
 }
 
@@ -299,53 +309,53 @@ UsbPortPowerEnable (
   VOID
   )
 {
-  EFI_STATUS Status = EFI_SUCCESS;
-  PCA95XX_PROTOCOL *Pca95xxProtocol;
+  EFI_STATUS        Status = EFI_SUCCESS;
+  PCA95XX_PROTOCOL  *Pca95xxProtocol;
 
   /* On Firefly ITX-3588J this is controlled via the PCA9555. */
-  Status = GetPca9555Protocol(&Pca95xxProtocol);
-  if (EFI_ERROR(Status)) {
+  Status = GetPca9555Protocol (&Pca95xxProtocol);
+  if (EFI_ERROR (Status)) {
     DEBUG ((DEBUG_ERROR, "Failed to get PCA9555! (%d)\n", Status));
   } else {
     /* USB-C */
-    Pca95xxProtocol->GpioProtocol.Set(
-      &Pca95xxProtocol->GpioProtocol,
-      12, /* vbus5v0_typec_pwr_en */
-      GPIO_MODE_OUTPUT_0
-    );
+    Pca95xxProtocol->GpioProtocol.Set (
+                                    &Pca95xxProtocol->GpioProtocol,
+                                    12, /* vbus5v0_typec_pwr_en */
+                                    GPIO_MODE_OUTPUT_0
+                                    );
 
-    gBS->Stall(1200000);
+    gBS->Stall (1200000);
 
-    Pca95xxProtocol->GpioProtocol.Set(
-      &Pca95xxProtocol->GpioProtocol,
-      12, /* vbus5v0_typec_pwr_en */
-      GPIO_MODE_OUTPUT_1
-    );
+    Pca95xxProtocol->GpioProtocol.Set (
+                                    &Pca95xxProtocol->GpioProtocol,
+                                    12, /* vbus5v0_typec_pwr_en */
+                                    GPIO_MODE_OUTPUT_1
+                                    );
 
     /* other USB stuff */
-    Pca95xxProtocol->GpioProtocol.Set(
-      &Pca95xxProtocol->GpioProtocol,
-      5, /* vcc5v0_host */
-      GPIO_MODE_OUTPUT_1
-    );
+    Pca95xxProtocol->GpioProtocol.Set (
+                                    &Pca95xxProtocol->GpioProtocol,
+                                    5, /* vcc5v0_host */
+                                    GPIO_MODE_OUTPUT_1
+                                    );
 
-    Pca95xxProtocol->GpioProtocol.Set(
-      &Pca95xxProtocol->GpioProtocol,
-      4, /* vcc_hub_reset */
-      GPIO_MODE_OUTPUT_1
-    );
+    Pca95xxProtocol->GpioProtocol.Set (
+                                    &Pca95xxProtocol->GpioProtocol,
+                                    4, /* vcc_hub_reset */
+                                    GPIO_MODE_OUTPUT_1
+                                    );
 
-    Pca95xxProtocol->GpioProtocol.Set(
-      &Pca95xxProtocol->GpioProtocol,
-      6, /* vcc_hub3_reset */
-      GPIO_MODE_OUTPUT_1
-    );
+    Pca95xxProtocol->GpioProtocol.Set (
+                                    &Pca95xxProtocol->GpioProtocol,
+                                    6, /* vcc_hub3_reset */
+                                    GPIO_MODE_OUTPUT_1
+                                    );
 
-    Pca95xxProtocol->GpioProtocol.Set(
-      &Pca95xxProtocol->GpioProtocol,
-      7, /* vcc5v0_host3 */
-      GPIO_MODE_OUTPUT_1
-    );
+    Pca95xxProtocol->GpioProtocol.Set (
+                                    &Pca95xxProtocol->GpioProtocol,
+                                    7, /* vcc5v0_host3 */
+                                    GPIO_MODE_OUTPUT_1
+                                    );
   }
 }
 
@@ -355,22 +365,22 @@ Usb2PhyResume (
   VOID
   )
 {
-  MmioWrite32(0xfd5d0008, 0x20000000);
-  MmioWrite32(0xfd5d4008, 0x20000000);
-  MmioWrite32(0xfd5d8008, 0x20000000);
-  MmioWrite32(0xfd5dc008, 0x20000000);
-  MmioWrite32(0xfd7f0a10, 0x07000700);
-  MmioWrite32(0xfd7f0a10, 0x07000000);
+  MmioWrite32 (0xfd5d0008, 0x20000000);
+  MmioWrite32 (0xfd5d4008, 0x20000000);
+  MmioWrite32 (0xfd5d8008, 0x20000000);
+  MmioWrite32 (0xfd5dc008, 0x20000000);
+  MmioWrite32 (0xfd7f0a10, 0x07000700);
+  MmioWrite32 (0xfd7f0a10, 0x07000000);
 }
 
 VOID
 EFIAPI
 PcieIoInit (
-  UINT32 Segment
+  UINT32  Segment
   )
 {
   /* Set reset and power IO to gpio output mode */
-  if(Segment == PCIE_SEGMENT_PCIE30X4) {
+  if (Segment == PCIE_SEGMENT_PCIE30X4) {
     /* reset */
     GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
     /* vcc3v3_pcie30 */
@@ -381,11 +391,11 @@ PcieIoInit (
 VOID
 EFIAPI
 PciePowerEn (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  if(Segment == PCIE_SEGMENT_PCIE30X4) {
+  if (Segment == PCIE_SEGMENT_PCIE30X4) {
     /* vcc3v3_pcie30 */
     GpioPinWrite (2, GPIO_PIN_PC5, Enable);
   }
@@ -394,21 +404,51 @@ PciePowerEn (
 VOID
 EFIAPI
 PciePeReset (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  if(Segment == PCIE_SEGMENT_PCIE30X4) {
+  if (Segment == PCIE_SEGMENT_PCIE30X4) {
     GpioPinWrite (4, GPIO_PIN_PB6, !Enable);
   }
 }
 
-PWM_DATA pwm_data = {
+VOID
+EFIAPI
+HdmiTxIomux (
+  IN UINT32  Id
+  )
+{
+  switch (Id) {
+    case 0:
+      GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
+      GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
+      GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
+      GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
+      break;
+    case 1:
+      GpioPinSetFunction (3, GPIO_PIN_PC4, 5); // hdmim2_tx1_cec
+      GpioPinSetPull (3, GPIO_PIN_PC4, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA6, 5); // hdmim0_tx1_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA6, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (3, GPIO_PIN_PC6, 5); // hdmim1_tx1_scl
+      GpioPinSetPull (3, GPIO_PIN_PC6, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (3, GPIO_PIN_PC5, 5); // hdmim1_tx1_sda
+      GpioPinSetPull (3, GPIO_PIN_PC5, GPIO_PIN_PULL_NONE);
+      break;
+  }
+}
+
+PWM_DATA  pwm_data = {
   .ControllerID = PWM_CONTROLLER2,
-  .ChannelID = PWM_CHANNEL3,
-  .PeriodNs = 50000,
-  .DutyNs = 50000,
-  .Polarity = TRUE,
+  .ChannelID    = PWM_CHANNEL3,
+  .PeriodNs     = 50000,
+  .DutyNs       = 50000,
+  .Polarity     = TRUE,
 }; // PWM2_CH3
 
 VOID
@@ -417,42 +457,42 @@ PwmFanIoSetup (
   VOID
   )
 {
-  EFI_STATUS Status = EFI_SUCCESS;
-  PCA95XX_PROTOCOL *Pca95xxProtocol;
+  EFI_STATUS        Status = EFI_SUCCESS;
+  PCA95XX_PROTOCOL  *Pca95xxProtocol;
 
-  Status = GetPca9555Protocol(&Pca95xxProtocol);
-  if (EFI_ERROR(Status)) {
+  Status = GetPca9555Protocol (&Pca95xxProtocol);
+  if (EFI_ERROR (Status)) {
     DEBUG ((DEBUG_ERROR, "Failed to get PCA9555! (%d)\n", Status));
   } else {
-    Pca95xxProtocol->GpioProtocol.Set(
-      &Pca95xxProtocol->GpioProtocol,
-      11, /* vcc_fan_pwr_en */
-      GPIO_MODE_OUTPUT_1
-    );
+    Pca95xxProtocol->GpioProtocol.Set (
+                                    &Pca95xxProtocol->GpioProtocol,
+                                    11, /* vcc_fan_pwr_en */
+                                    GPIO_MODE_OUTPUT_1
+                                    );
   }
 }
 
 VOID
 EFIAPI
 PwmFanSetSpeed (
-  IN UINT32 Percentage
+  IN UINT32  Percentage
   )
 {
-  EFI_STATUS Status = EFI_SUCCESS;
-  PCA95XX_PROTOCOL *Pca95xxProtocol;
+  EFI_STATUS        Status = EFI_SUCCESS;
+  PCA95XX_PROTOCOL  *Pca95xxProtocol;
 
-  Status = GetPca9555Protocol(&Pca95xxProtocol);
-  if (EFI_ERROR(Status)) {
+  Status = GetPca9555Protocol (&Pca95xxProtocol);
+  if (EFI_ERROR (Status)) {
     DEBUG ((DEBUG_ERROR, "Failed to get PCA9555! (%d)\n", Status));
   } else {
     /* (SS) NB: (TBA?) It doesn't *appear* we can regulate the fan speed,
      *      only power up/down, but I could be wrong
      */
-    Pca95xxProtocol->GpioProtocol.Set(
-      &Pca95xxProtocol->GpioProtocol,
-      11, /* vcc_fan_pwr_en */
-      (Percentage > 0) ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTPUT_0
-    );
+    Pca95xxProtocol->GpioProtocol.Set (
+                                    &Pca95xxProtocol->GpioProtocol,
+                                    11, /* vcc_fan_pwr_en */
+                                    (Percentage > 0) ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTPUT_0
+                                    );
   }
 }
 
@@ -466,7 +506,7 @@ PlatformInitLeds (
   GpioPinWrite (1, GPIO_PIN_PB3, TRUE);
   GpioPinSetDirection (1, GPIO_PIN_PB3, GPIO_PIN_OUTPUT);
 
-#if 0
+ #if 0
   /* Red off, Green for status, Blue for power */
   GpioPinWrite (3, GPIO_PIN_PB2, FALSE);
   GpioPinSetDirection (3, GPIO_PIN_PB2, GPIO_PIN_OUTPUT);
@@ -474,43 +514,45 @@ PlatformInitLeds (
   GpioPinSetDirection (3, GPIO_PIN_PC0, GPIO_PIN_OUTPUT);
   GpioPinWrite (1, GPIO_PIN_PD5, TRUE);
   GpioPinSetDirection (1, GPIO_PIN_PD5, GPIO_PIN_OUTPUT);
-#endif
+ #endif
 }
 
 VOID
 EFIAPI
 PlatformSetStatusLed (
-  IN BOOLEAN Enable
+  IN BOOLEAN  Enable
   )
 {
   /* (SS) does not seem to work and causes errors on I2C complaining
    * about something being too high
    */
-#if 0
-  EFI_STATUS Status = EFI_SUCCESS;
-  PCA95XX_PROTOCOL *Pca95xxProtocol;
+ #if 0
+  EFI_STATUS        Status = EFI_SUCCESS;
+  PCA95XX_PROTOCOL  *Pca95xxProtocol;
 
   /* On Firefly ITX-3588J this is controlled via the PCA9555. */
-  Status = GetPca9555Protocol(&Pca95xxProtocol);
-  if (EFI_ERROR(Status)) {
+  Status = GetPca9555Protocol (&Pca95xxProtocol);
+  if (EFI_ERROR (Status)) {
     DEBUG ((DEBUG_ERROR, "Failed to get PCA9555! (%d)\n", Status));
   } else {
-    Pca95xxProtocol->GpioProtocol.Set(
-      &Pca95xxProtocol->GpioProtocol,
-      3, /* user_led */
-      Enable ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTPUT_0
-    );
+    Pca95xxProtocol->GpioProtocol.Set (
+                                    &Pca95xxProtocol->GpioProtocol,
+                                    3, /* user_led */
+                                    Enable ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTPUT_0
+                                    );
   }
-#endif
+
+ #endif
 }
 
 CONST EFI_GUID *
 EFIAPI
 PlatformGetDtbFileGuid (
-  IN UINT32 CompatMode
+  IN UINT32  CompatMode
   )
 {
-  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+  STATIC CONST EFI_GUID  VendorDtbFileGuid = {
+    // DeviceTree/Vendor.inf
     0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
   };
 
@@ -528,5 +570,4 @@ PlatformEarlyInit (
   VOID
   )
 {
-
 }

edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -18,29 +18,29 @@
 #include <VarStoreData.h>
 #include <Library/UefiBootServicesTableLib.h>
 
-static struct regulator_init_data rk806_init_data[] = {
+static struct regulator_init_data  rk806_init_data[] = {
   /* Master PMIC */
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
- // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK4,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK5,  850000),
+  // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK7,  2000000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK8,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK10, 1800000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO2,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO4,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO5,  750000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO1,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO2,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO3,  1200000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO4,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO5,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO6,  1800000),
 
   /* No dual PMICs on this platform */
 };
@@ -52,9 +52,9 @@ SdmmcIoMux (
   )
 {
   /* sdmmc0 iomux (microSD socket) */
-  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
-  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
-  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+  BUS_IOC->GPIO4D_IOMUX_SEL_L  = (0xFFFFUL << 16) | (0x1111); // SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H  = (0x00FFUL << 16) | (0x0011); // SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); // SDMMC_DET
 }
 
 VOID
@@ -64,14 +64,14 @@ SdhciEmmcIoMux (
   )
 {
   /* sdmmc0 iomux */
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); // EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
 }
 
-#define NS_CRU_BASE         0xFD7C0000
-#define CRU_CLKSEL_CON59    0x03EC
-#define CRU_CLKSEL_CON78    0x0438
+#define NS_CRU_BASE       0xFD7C0000
+#define CRU_CLKSEL_CON59  0x03EC
+#define CRU_CLKSEL_CON78  0x0438
 
 VOID
 EFIAPI
@@ -80,11 +80,11 @@ Rk806SpiIomux (
   )
 {
   /* io mux */
-  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
-  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  // BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  // BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
   PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
   PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+  MmioWrite32 (NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
 }
 
 VOID
@@ -93,24 +93,27 @@ Rk806Configure (
   VOID
   )
 {
-  UINTN RegCfgIndex;
+  UINTN  RegCfgIndex;
 
-  RK806Init();
+  RK806Init ();
 
-  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
-    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
+    RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
+  }
 }
 
 VOID
 EFIAPI
 SetCPULittleVoltage (
-  IN UINT32 Microvolts
+  IN UINT32  Microvolts
   )
 {
-  struct regulator_init_data Rk806CpuLittleSupply =
-        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+  struct regulator_init_data  Rk806CpuLittleSupply =
+    RK8XX_VOLTAGE_INIT (MASTER_BUCK2, Microvolts);
 
-  RK806RegulatorInit(Rk806CpuLittleSupply);
+  RK806RegulatorInit (Rk806CpuLittleSupply);
 }
 
 VOID
@@ -120,31 +123,33 @@ NorFspiIomux (
   )
 {
   /* io mux */
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
-             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
-#define FSPI_M1
-#if defined(FSPI_M0)
-   /*FSPI M0*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
-#elif defined(FSPI_M1)
+  MmioWrite32 (
+    NS_CRU_BASE + CRU_CLKSEL_CON78,
+    (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)
+    );
+  #define FSPI_M1
+ #if defined (FSPI_M0)
+  /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0);   // FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222);     // FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); // FSPI_CS0N_M0
+ #elif defined (FSPI_M1)
   /*FSPI M1*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
-#else
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); // FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); // FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3);         // FSPI_CS0N_M1
+ #else
   /*FSPI M2*/
-  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
-  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
-  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
-#endif
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); // [FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50);     // FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2);         // FSPI_CS0_M2
+ #endif
 }
 
 VOID
 EFIAPI
 GmacIomux (
-  IN UINT32 Id
+  IN UINT32  Id
   )
 {
   switch (Id) {
@@ -184,51 +189,51 @@ GmacIoPhyReset (
 VOID
 EFIAPI
 NorFspiEnableClock (
-  UINT32 *CruBase
+  UINT32  *CruBase
   )
 {
-  UINTN BaseAddr = (UINTN) CruBase;
+  UINTN  BaseAddr = (UINTN)CruBase;
 
-  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+  MmioWrite32 (BaseAddr + 0x087C, 0x0E000000);
 }
 
 VOID
 EFIAPI
 I2cIomux (
-   UINT32 id
+  UINT32  id
   )
 {
   switch (id) {
-  case 0:
-    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
-    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
-    break;
-  case 1:
-    break;
-  case 2:
-    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
-    break;
-  case 3:
-    GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0
-    GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0
-    break;
-  case 4:
-    GpioPinSetFunction(1, GPIO_PIN_PA3, 9); //i2c4_scl_m3
-    GpioPinSetFunction(1, GPIO_PIN_PA2, 9); //i2c4_sda_m3
-    break;
-  case 5:
-    break;
-  case 6:
-    GpioPinSetFunction(4, GPIO_PIN_PB1, 9); //i2c6_scl_m3
-    GpioPinSetFunction(4, GPIO_PIN_PB0, 9); //i2c6_sda_m3
-    break;
-  case 7:
-    GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0
-    GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0
-    break;
-  default:
-    break;
+    case 0:
+      GpioPinSetFunction (0, GPIO_PIN_PD1, 3); // i2c0_scl_m2
+      GpioPinSetFunction (0, GPIO_PIN_PD2, 3); // i2c0_sda_m2
+      break;
+    case 1:
+      break;
+    case 2:
+      GpioPinSetFunction (0, GPIO_PIN_PB7, 9); // i2c2_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC0, 9); // i2c2_sda_m0
+      break;
+    case 3:
+      GpioPinSetFunction (1, GPIO_PIN_PC1, 9); // i2c3_scl_m0
+      GpioPinSetFunction (1, GPIO_PIN_PC0, 9); // i2c3_sda_m0
+      break;
+    case 4:
+      GpioPinSetFunction (1, GPIO_PIN_PA3, 9); // i2c4_scl_m3
+      GpioPinSetFunction (1, GPIO_PIN_PA2, 9); // i2c4_sda_m3
+      break;
+    case 5:
+      break;
+    case 6:
+      GpioPinSetFunction (4, GPIO_PIN_PB1, 9); // i2c6_scl_m3
+      GpioPinSetFunction (4, GPIO_PIN_PB0, 9); // i2c6_sda_m3
+      break;
+    case 7:
+      GpioPinSetFunction (1, GPIO_PIN_PD0, 9); // i2c7_scl_m0
+      GpioPinSetFunction (1, GPIO_PIN_PD1, 9); // i2c7_sda_m0
+      break;
+    default:
+      break;
   }
 }
 
@@ -238,7 +243,7 @@ UsbPortPowerEnable (
   VOID
   )
 {
-  DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n"));
+  DEBUG ((DEBUG_INFO, "UsbPortPowerEnable called\n"));
 
   /* Enable USB-C VBUS */
   GpioPinWrite (1, GPIO_PIN_PB1, TRUE);
@@ -260,22 +265,23 @@ Usb2PhyResume (
   VOID
   )
 {
-  MmioWrite32(0xfd5d0008, 0x20000000);
-  MmioWrite32(0xfd5d4008, 0x20000000);
-  MmioWrite32(0xfd5d8008, 0x20000000);
-  MmioWrite32(0xfd5dc008, 0x20000000);
-  MmioWrite32(0xfd7f0a10, 0x07000700);
-  MmioWrite32(0xfd7f0a10, 0x07000000);
+  MmioWrite32 (0xfd5d0008, 0x20000000);
+  MmioWrite32 (0xfd5d4008, 0x20000000);
+  MmioWrite32 (0xfd5d8008, 0x20000000);
+  MmioWrite32 (0xfd5dc008, 0x20000000);
+  MmioWrite32 (0xfd7f0a10, 0x07000700);
+  MmioWrite32 (0xfd7f0a10, 0x07000000);
 }
 
 VOID
 EFIAPI
 PcieIoInit (
-  UINT32 Segment
+  UINT32  Segment
   )
 {
   /* Set reset and power IO to gpio output mode */
-  if(Segment == PCIE_SEGMENT_PCIE20L2) { // M.2 M Key
+  if (Segment == PCIE_SEGMENT_PCIE20L2) {
+    // M.2 M Key
     /* reset */
     GpioPinSetDirection (3, GPIO_PIN_PD1, GPIO_PIN_OUTPUT);
     /* vcc3v3_pcie20 */
@@ -286,11 +292,11 @@ PcieIoInit (
 VOID
 EFIAPI
 PciePowerEn (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  if(Segment == PCIE_SEGMENT_PCIE20L2) {
+  if (Segment == PCIE_SEGMENT_PCIE20L2) {
     /* vcc3v3_pcie20 */
     GpioPinWrite (1, GPIO_PIN_PD7, Enable);
   }
@@ -299,21 +305,41 @@ PciePowerEn (
 VOID
 EFIAPI
 PciePeReset (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  if(Segment == PCIE_SEGMENT_PCIE20L2) {
+  if (Segment == PCIE_SEGMENT_PCIE20L2) {
     GpioPinWrite (3, GPIO_PIN_PD1, !Enable);
   }
 }
 
-PWM_DATA pwm_data = {
+VOID
+EFIAPI
+HdmiTxIomux (
+  IN UINT32  Id
+  )
+{
+  switch (Id) {
+    case 0:
+      GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
+      GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
+      GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
+      GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
+      break;
+  }
+}
+
+PWM_DATA  pwm_data = {
   .ControllerID = PWM_CONTROLLER2,
-  .ChannelID = PWM_CHANNEL3,
-  .PeriodNs = 50000,
-  .DutyNs = 50000,
-  .Polarity = TRUE,
+  .ChannelID    = PWM_CHANNEL3,
+  .PeriodNs     = 50000,
+  .DutyNs       = 50000,
+  .Polarity     = TRUE,
 }; // PWM2_CH3
 
 VOID
@@ -330,7 +356,7 @@ PwmFanIoSetup (
 VOID
 EFIAPI
 PwmFanSetSpeed (
-  IN UINT32 Percentage
+  IN UINT32  Percentage
   )
 {
   pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100;
@@ -355,7 +381,7 @@ PlatformInitLeds (
 VOID
 EFIAPI
 PlatformSetStatusLed (
-  IN BOOLEAN Enable
+  IN BOOLEAN  Enable
   )
 {
   GpioPinWrite (3, GPIO_PIN_PC0, Enable);
@@ -364,10 +390,11 @@ PlatformSetStatusLed (
 CONST EFI_GUID *
 EFIAPI
 PlatformGetDtbFileGuid (
-  IN UINT32 CompatMode
+  IN UINT32  CompatMode
   )
 {
-  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+  STATIC CONST EFI_GUID  VendorDtbFileGuid = {
+    // DeviceTree/Vendor.inf
     0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
   };
 
@@ -385,5 +412,5 @@ PlatformEarlyInit (
   VOID
   )
 {
-  GpioPinSetFunction(1, GPIO_PIN_PA6, 0); //jdet
+  GpioPinSetFunction (1, GPIO_PIN_PA6, 0); // jdet
 }

edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc.inc

@@ -57,13 +57,6 @@
   gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
   gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x2
 
-  #
-  # CPU Performance default values
-  #
-  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-
   #
   # PCIe/SATA/USB Combo PIPE PHY support flags and default values
   #
@@ -94,6 +87,14 @@
   #
   gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE
 
+  #
+  # Display support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
+    VOP_OUTPUT_IF_HDMI0,
+    VOP_OUTPUT_IF_DP0
+  })}
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.

edk2-rockchip/Platform/FriendlyElec/Drivers/LogoDxe/Logo.c

@@ -19,15 +19,15 @@
 #include <Library/DebugLib.h>
 
 typedef struct {
-  EFI_IMAGE_ID                          ImageId;
-  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
-  INTN                                  OffsetX;
-  INTN                                  OffsetY;
+  EFI_IMAGE_ID                             ImageId;
+  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE    Attribute;
+  INTN                                     OffsetX;
+  INTN                                     OffsetY;
 } LOGO_ENTRY;
 
-STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
-STATIC EFI_HII_HANDLE            mHiiHandle;
-STATIC LOGO_ENTRY                mLogos[] = {
+STATIC EFI_HII_IMAGE_EX_PROTOCOL  *mHiiImageEx;
+STATIC EFI_HII_HANDLE             mHiiHandle;
+STATIC LOGO_ENTRY                 mLogos[] = {
   {
     IMAGE_TOKEN (IMG_LOGO),
     EdkiiPlatformLogoDisplayAttributeCenter,
@@ -53,18 +53,19 @@ STATIC
 EFI_STATUS
 EFIAPI
 GetImage (
-  IN     EDKII_PLATFORM_LOGO_PROTOCOL          *This,
-  IN OUT UINT32                                *Instance,
-     OUT EFI_IMAGE_INPUT                       *Image,
-     OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
-     OUT INTN                                  *OffsetX,
-     OUT INTN                                  *OffsetY
+  IN     EDKII_PLATFORM_LOGO_PROTOCOL        *This,
+  IN OUT UINT32                              *Instance,
+  OUT EFI_IMAGE_INPUT                        *Image,
+  OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE  *Attribute,
+  OUT INTN                                   *OffsetX,
+  OUT INTN                                   *OffsetY
   )
 {
-  UINT32 Current;
+  UINT32  Current;
 
-  if (Instance == NULL || Image == NULL ||
-      Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
+  if ((Instance == NULL) || (Image == NULL) ||
+      (Attribute == NULL) || (OffsetX == NULL) || (OffsetY == NULL))
+  {
     return EFI_INVALID_PARAMETER;
   }
 
@@ -78,11 +79,15 @@ GetImage (
   *OffsetX   = mLogos[Current].OffsetX;
   *OffsetY   = mLogos[Current].OffsetY;
 
-  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
-                        mLogos[Current].ImageId, Image);
+  return mHiiImageEx->GetImageEx (
+                        mHiiImageEx,
+                        mHiiHandle,
+                        mLogos[Current].ImageId,
+                        Image
+                        );
 }
 
-STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+STATIC EDKII_PLATFORM_LOGO_PROTOCOL  mPlatformLogo = {
   GetImage
 };
 
@@ -101,44 +106,66 @@ STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
 EFI_STATUS
 EFIAPI
 InitializeLogo (
-  IN EFI_HANDLE               ImageHandle,
-  IN EFI_SYSTEM_TABLE         *SystemTable
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
-  EFI_STATUS                  Status;
-  EFI_HII_PACKAGE_LIST_HEADER *PackageList;
-  EFI_HII_DATABASE_PROTOCOL   *HiiDatabase;
-  EFI_HANDLE                  Handle;
+  EFI_STATUS                   Status;
+  EFI_HII_PACKAGE_LIST_HEADER  *PackageList;
+  EFI_HII_DATABASE_PROTOCOL    *HiiDatabase;
+  EFI_HANDLE                   Handle;
 
-  Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
-                  (VOID **) &HiiDatabase);
+  Status = gBS->LocateProtocol (
+                  &gEfiHiiDatabaseProtocolGuid,
+                  NULL,
+                  (VOID **)&HiiDatabase
+                  );
   ASSERT_EFI_ERROR (Status);
 
-  Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
-                  (VOID **) &mHiiImageEx);
+  Status = gBS->LocateProtocol (
+                  &gEfiHiiImageExProtocolGuid,
+                  NULL,
+                  (VOID **)&mHiiImageEx
+                  );
   ASSERT_EFI_ERROR (Status);
 
   //
   // Retrieve HII package list from ImageHandle
   //
-  Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
-                  (VOID **) &PackageList, ImageHandle, NULL,
-                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+  Status = gBS->OpenProtocol (
+                  ImageHandle,
+                  &gEfiHiiPackageListProtocolGuid,
+                  (VOID **)&PackageList,
+                  ImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
   if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR,
-      "HII Image Package with logo not found in PE/COFF resource section\n"));
+    DEBUG ((
+      DEBUG_ERROR,
+      "HII Image Package with logo not found in PE/COFF resource section\n"
+      ));
     return Status;
   }
 
   //
   // Publish HII package list to HII Database.
   //
-  Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
-                          &mHiiHandle);
+  Status = HiiDatabase->NewPackageList (
+                          HiiDatabase,
+                          PackageList,
+                          NULL,
+                          &mHiiHandle
+                          );
   if (!EFI_ERROR (Status)) {
     Handle = NULL;
-    Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
-                    &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
+    Status = gBS->InstallMultipleProtocolInterfaces (
+                    &Handle,
+                    &gEdkiiPlatformLogoProtocolGuid,
+                    &mPlatformLogo,
+                    NULL
+                    );
   }
+
   return Status;
 }

edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/DeviceTree/Mainline.inf

@@ -14,7 +14,7 @@
   VERSION_STRING                 = 1.0
 
 [Sources]
-  devicetree/mainline/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588-nas.dts
+  devicetree/mainline/rk3588-friendlyelec-cm3588-nas-fixup.dts
 
 [Packages]
   MdePkg/MdePkg.dec

edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -17,29 +17,29 @@
 #include <Soc.h>
 #include <VarStoreData.h>
 
-static struct regulator_init_data rk806_init_data[] = {
+static struct regulator_init_data  rk806_init_data[] = {
   /* Master PMIC */
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
-  //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK4,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK5,  850000),
+  // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK7,  2000000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK8,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK10, 1800000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO2,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO4,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO5,  750000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO1,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO2,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO3,  1200000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO4,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO5,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO6,  1800000),
 
   /* No dual PMICs on this platform */
 };
@@ -51,9 +51,9 @@ SdmmcIoMux (
   )
 {
   /* sdmmc0 iomux (microSD socket) */
-  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
-  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
-  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+  BUS_IOC->GPIO4D_IOMUX_SEL_L  = (0xFFFFUL << 16) | (0x1111); // SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H  = (0x00FFUL << 16) | (0x0011); // SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); // SDMMC_DET
 }
 
 VOID
@@ -63,14 +63,14 @@ SdhciEmmcIoMux (
   )
 {
   /* sdhci0 iomux (eMMC socket) */
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); // EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
 }
 
-#define NS_CRU_BASE         0xFD7C0000
-#define CRU_CLKSEL_CON59    0x03EC
-#define CRU_CLKSEL_CON78    0x0438
+#define NS_CRU_BASE       0xFD7C0000
+#define CRU_CLKSEL_CON59  0x03EC
+#define CRU_CLKSEL_CON78  0x0438
 
 VOID
 EFIAPI
@@ -79,11 +79,11 @@ Rk806SpiIomux (
   )
 {
   /* io mux */
-  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
-  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  // BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  // BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
   PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
   PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+  MmioWrite32 (NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
 }
 
 VOID
@@ -92,24 +92,27 @@ Rk806Configure (
   VOID
   )
 {
-  UINTN RegCfgIndex;
+  UINTN  RegCfgIndex;
 
-  RK806Init();
+  RK806Init ();
 
-  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
-    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
+    RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
+  }
 }
 
 VOID
 EFIAPI
 SetCPULittleVoltage (
-  IN UINT32 Microvolts
+  IN UINT32  Microvolts
   )
 {
-  struct regulator_init_data Rk806CpuLittleSupply =
-        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+  struct regulator_init_data  Rk806CpuLittleSupply =
+    RK8XX_VOLTAGE_INIT (MASTER_BUCK2, Microvolts);
 
-  RK806RegulatorInit(Rk806CpuLittleSupply);
+  RK806RegulatorInit (Rk806CpuLittleSupply);
 }
 
 VOID
@@ -119,31 +122,33 @@ NorFspiIomux (
   )
 {
   /* io mux */
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
-             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
-#define FSPI_M1
-#if defined(FSPI_M0)
-   /*FSPI M0*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
-#elif defined(FSPI_M1)
+  MmioWrite32 (
+    NS_CRU_BASE + CRU_CLKSEL_CON78,
+    (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)
+    );
+  #define FSPI_M1
+ #if defined (FSPI_M0)
+  /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0);   // FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222);     // FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); // FSPI_CS0N_M0
+ #elif defined (FSPI_M1)
   /*FSPI M1*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
-#else
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); // FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); // FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3);         // FSPI_CS0N_M1
+ #else
   /*FSPI M2*/
-  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
-  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
-  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
-#endif
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); // [FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50);     // FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2);         // FSPI_CS0_M2
+ #endif
 }
 
 VOID
 EFIAPI
 GmacIomux (
-  IN UINT32 Id
+  IN UINT32  Id
   )
 {
   /* No GMAC here */
@@ -152,51 +157,51 @@ GmacIomux (
 VOID
 EFIAPI
 NorFspiEnableClock (
-  UINT32 *CruBase
+  UINT32  *CruBase
   )
 {
-  UINTN BaseAddr = (UINTN) CruBase;
+  UINTN  BaseAddr = (UINTN)CruBase;
 
-  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+  MmioWrite32 (BaseAddr + 0x087C, 0x0E000000);
 }
 
 VOID
 EFIAPI
 I2cIomux (
-   UINT32 id
+  UINT32  id
   )
 {
   switch (id) {
-  case 0:
-    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
-    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
-    break;
-  case 1:
-    break;
-  case 2:
-    break;
-  case 3:
-    break;
-  case 4:
-    GpioPinSetFunction(1, GPIO_PIN_PA3, 9); //i2c4_scl_m3
-    GpioPinSetFunction(1, GPIO_PIN_PA2, 9); //i2c4_sda_m3
-    break;
-  case 5:
-    GpioPinSetFunction(3, GPIO_PIN_PC7, 9); //i2c5_scl_m0
-    GpioPinSetFunction(3, GPIO_PIN_PD0, 9); //i2c5_sda_m0
-    break;
-  case 6:
-    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
-    break;
-  case 7:
-    break;
-  case 8:
-    GpioPinSetFunction(1, GPIO_PIN_PD6, 9); //i2c8_scl_m2
-    GpioPinSetFunction(1, GPIO_PIN_PD7, 9); //i2c8_sda_m2
-    break;
-  default:
-    break;
+    case 0:
+      GpioPinSetFunction (0, GPIO_PIN_PD1, 3); // i2c0_scl_m2
+      GpioPinSetFunction (0, GPIO_PIN_PD2, 3); // i2c0_sda_m2
+      break;
+    case 1:
+      break;
+    case 2:
+      break;
+    case 3:
+      break;
+    case 4:
+      GpioPinSetFunction (1, GPIO_PIN_PA3, 9); // i2c4_scl_m3
+      GpioPinSetFunction (1, GPIO_PIN_PA2, 9); // i2c4_sda_m3
+      break;
+    case 5:
+      GpioPinSetFunction (3, GPIO_PIN_PC7, 9); // i2c5_scl_m0
+      GpioPinSetFunction (3, GPIO_PIN_PD0, 9); // i2c5_sda_m0
+      break;
+    case 6:
+      GpioPinSetFunction (0, GPIO_PIN_PD0, 9); // i2c6_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC7, 9); // i2c6_sda_m0
+      break;
+    case 7:
+      break;
+    case 8:
+      GpioPinSetFunction (1, GPIO_PIN_PD6, 9); // i2c8_scl_m2
+      GpioPinSetFunction (1, GPIO_PIN_PD7, 9); // i2c8_sda_m2
+      break;
+    default:
+      break;
   }
 }
 
@@ -206,7 +211,8 @@ UsbPortPowerEnable (
   VOID
   )
 {
-  DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n"));
+  DEBUG ((DEBUG_INFO, "UsbPortPowerEnable called\n"));
+
   /* The "pinctrl/usb" section in the dts lists three _en pins for power.
      They appear to correspond to the three usb ports on the NAS carrier board. */
   GpioPinWrite (1, GPIO_PIN_PA4, TRUE);
@@ -231,22 +237,22 @@ Usb2PhyResume (
   VOID
   )
 {
-  MmioWrite32(0xfd5d0008, 0x20000000);
-  MmioWrite32(0xfd5d4008, 0x20000000);
-  MmioWrite32(0xfd5d8008, 0x20000000);
-  MmioWrite32(0xfd5dc008, 0x20000000);
-  MmioWrite32(0xfd7f0a10, 0x07000700);
-  MmioWrite32(0xfd7f0a10, 0x07000000);
+  MmioWrite32 (0xfd5d0008, 0x20000000);
+  MmioWrite32 (0xfd5d4008, 0x20000000);
+  MmioWrite32 (0xfd5d8008, 0x20000000);
+  MmioWrite32 (0xfd5dc008, 0x20000000);
+  MmioWrite32 (0xfd7f0a10, 0x07000700);
+  MmioWrite32 (0xfd7f0a10, 0x07000000);
 }
 
 VOID
 EFIAPI
 PcieIoInit (
-  UINT32 Segment
+  UINT32  Segment
   )
 {
   /* Set reset and power IO to gpio output mode */
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4:
       GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
       break;
@@ -259,7 +265,7 @@ PcieIoInit (
     case PCIE_SEGMENT_PCIE20L1: // m.2 a+e key
       GpioPinSetDirection (4, GPIO_PIN_PA2, GPIO_PIN_OUTPUT);
       break;
-    case PCIE_SEGMENT_PCIE20L2: //rtl8152b
+    case PCIE_SEGMENT_PCIE20L2: // rtl8152b
       GpioPinSetDirection (4, GPIO_PIN_PA4, GPIO_PIN_OUTPUT);
       break;
     default:
@@ -270,13 +276,13 @@ PcieIoInit (
 VOID
 EFIAPI
 PciePowerEn (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
   /* output high to enable power */
 
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4:
       break;
     case PCIE_SEGMENT_PCIE20L0:
@@ -293,11 +299,11 @@ PciePowerEn (
 VOID
 EFIAPI
 PciePeReset (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4:
       GpioPinWrite (4, GPIO_PIN_PB6, !Enable);
       break;
@@ -318,12 +324,42 @@ PciePeReset (
   }
 }
 
-PWM_DATA pwm_data = {
+VOID
+EFIAPI
+HdmiTxIomux (
+  IN UINT32  Id
+  )
+{
+  switch (Id) {
+    case 0:
+      GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
+      GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
+      GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
+      GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
+      break;
+    case 1:
+      GpioPinSetFunction (3, GPIO_PIN_PC4, 5); // hdmim2_tx1_cec
+      GpioPinSetPull (3, GPIO_PIN_PC4, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA6, 5); // hdmim0_tx1_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA6, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (3, GPIO_PIN_PC6, 5); // hdmim1_tx1_scl
+      GpioPinSetPull (3, GPIO_PIN_PC6, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (3, GPIO_PIN_PC5, 5); // hdmim1_tx1_sda
+      GpioPinSetPull (3, GPIO_PIN_PC5, GPIO_PIN_PULL_NONE);
+      break;
+  }
+}
+
+PWM_DATA  pwm_data = {
   .ControllerID = PWM_CONTROLLER0,
-  .ChannelID = PWM_CHANNEL1,
-  .PeriodNs = 4000000,
-  .DutyNs = 4000000,
-  .Polarity = FALSE,
+  .ChannelID    = PWM_CHANNEL1,
+  .PeriodNs     = 4000000,
+  .DutyNs       = 4000000,
+  .Polarity     = FALSE,
 }; // PWM0_CH1
 
 VOID
@@ -340,14 +376,13 @@ PwmFanIoSetup (
 VOID
 EFIAPI
 PwmFanSetSpeed (
-  IN UINT32 Percentage
+  IN UINT32  Percentage
   )
 {
   pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100;
   RkPwmSetConfig (&pwm_data);
 }
 
-
 VOID
 EFIAPI
 PlatformInitLeds (
@@ -362,7 +397,7 @@ PlatformInitLeds (
 VOID
 EFIAPI
 PlatformSetStatusLed (
-  IN BOOLEAN Enable
+  IN BOOLEAN  Enable
   )
 {
   GpioPinWrite (1, GPIO_PIN_PC6, Enable);
@@ -371,13 +406,15 @@ PlatformSetStatusLed (
 CONST EFI_GUID *
 EFIAPI
 PlatformGetDtbFileGuid (
-  IN UINT32 CompatMode
+  IN UINT32  CompatMode
   )
 {
-  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+  STATIC CONST EFI_GUID  VendorDtbFileGuid = {
+    // DeviceTree/Vendor.inf
     0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
   };
-  STATIC CONST EFI_GUID MainlineDtbFileGuid = {       // DeviceTree/Mainline.inf
+  STATIC CONST EFI_GUID  MainlineDtbFileGuid = {
+    // DeviceTree/Mainline.inf
     0x84492e97, 0xa10f, 0x49a7, { 0x85, 0xe9, 0x02, 0x5d, 0x19, 0x66, 0xb3, 0x43 }
   };
 

edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/NanoPC-CM3588-NAS.dsc

@@ -28,6 +28,9 @@
   FLASH_DEFINITION               = Silicon/Rockchip/RK3588/RK3588.fdf
   RK_PLATFORM_FVMAIN_MODULES     = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc
 
+  # GMAC is not exposed
+  DEFINE RK3588_GMAC_ENABLE = FALSE
+
   #
   # HYM8563 RTC support
   # I2C location configured by PCDs below.
@@ -72,19 +75,15 @@
   gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
   gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6
 
-  #
-  # CPU Performance default values
-  #
-  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-
   #
   # PCIe/SATA/USB Combo PIPE PHY support flags and default values
   # NanoPC CM3588 has one 2.5 GBE wired to the first PCIE2 port
   #
+  gRK3588TokenSpaceGuid.PcdPcie30PhyModeDefault|$(PCIE30_PHY_MODE_NABIBI)
+  gRK3588TokenSpaceGuid.PcdPcie30x2Supported|TRUE
   gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|FALSE
   gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE)
+  gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3)
 
   #
   # USB/DP Combo PHY support flags and default values
@@ -104,6 +103,15 @@
   #
   gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
 
+  #
+  # Display support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
+    VOP_OUTPUT_IF_HDMI0,
+    VOP_OUTPUT_IF_HDMI1,
+    VOP_OUTPUT_IF_DP0
+  })}
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.

edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/DeviceTree/Mainline.inf

@@ -14,7 +14,7 @@
   VERSION_STRING                 = 1.0
 
 [Sources]
-  devicetree/mainline/upstream/src/arm64/rockchip/rk3588-nanopc-t6.dts
+  devicetree/mainline/rk3588-nanopc-t6-fixup.dts
 
 [Packages]
   MdePkg/MdePkg.dec

edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -16,29 +16,29 @@
 #include <Soc.h>
 #include <VarStoreData.h>
 
-static struct regulator_init_data rk806_init_data[] = {
+static struct regulator_init_data  rk806_init_data[] = {
   /* Master PMIC */
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
-  //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK4,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK5,  850000),
+  // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK7,  2000000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK8,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK10, 1800000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO2,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO4,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO5,  750000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO1,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO2,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO3,  1200000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO4,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO5,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO6,  1800000),
 
   /* No dual PMICs on this platform */
 };
@@ -50,9 +50,9 @@ SdmmcIoMux (
   )
 {
   /* sdmmc0 iomux (microSD socket) */
-  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
-  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
-  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+  BUS_IOC->GPIO4D_IOMUX_SEL_L  = (0xFFFFUL << 16) | (0x1111); // SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H  = (0x00FFUL << 16) | (0x0011); // SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); // SDMMC_DET
 }
 
 VOID
@@ -62,14 +62,14 @@ SdhciEmmcIoMux (
   )
 {
   /* sdhci0 iomux (eMMC socket) */
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); // EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
 }
 
-#define NS_CRU_BASE         0xFD7C0000
-#define CRU_CLKSEL_CON59    0x03EC
-#define CRU_CLKSEL_CON78    0x0438
+#define NS_CRU_BASE       0xFD7C0000
+#define CRU_CLKSEL_CON59  0x03EC
+#define CRU_CLKSEL_CON78  0x0438
 
 VOID
 EFIAPI
@@ -78,11 +78,11 @@ Rk806SpiIomux (
   )
 {
   /* io mux */
-  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
-  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  // BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  // BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
   PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
   PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+  MmioWrite32 (NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
 }
 
 VOID
@@ -91,24 +91,27 @@ Rk806Configure (
   VOID
   )
 {
-  UINTN RegCfgIndex;
+  UINTN  RegCfgIndex;
 
-  RK806Init();
+  RK806Init ();
 
-  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
-    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
+    RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
+  }
 }
 
 VOID
 EFIAPI
 SetCPULittleVoltage (
-  IN UINT32 Microvolts
+  IN UINT32  Microvolts
   )
 {
-  struct regulator_init_data Rk806CpuLittleSupply =
-        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+  struct regulator_init_data  Rk806CpuLittleSupply =
+    RK8XX_VOLTAGE_INIT (MASTER_BUCK2, Microvolts);
 
-  RK806RegulatorInit(Rk806CpuLittleSupply);
+  RK806RegulatorInit (Rk806CpuLittleSupply);
 }
 
 VOID
@@ -118,31 +121,33 @@ NorFspiIomux (
   )
 {
   /* io mux */
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
-             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
-#define FSPI_M1
-#if defined(FSPI_M0)
-   /*FSPI M0*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
-#elif defined(FSPI_M1)
+  MmioWrite32 (
+    NS_CRU_BASE + CRU_CLKSEL_CON78,
+    (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)
+    );
+  #define FSPI_M1
+ #if defined (FSPI_M0)
+  /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0);   // FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222);     // FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); // FSPI_CS0N_M0
+ #elif defined (FSPI_M1)
   /*FSPI M1*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
-#else
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); // FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); // FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3);         // FSPI_CS0N_M1
+ #else
   /*FSPI M2*/
-  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
-  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
-  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
-#endif
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); // [FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50);     // FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2);         // FSPI_CS0_M2
+ #endif
 }
 
 VOID
 EFIAPI
 GmacIomux (
-  IN UINT32 Id
+  IN UINT32  Id
   )
 {
   /* No GMAC here */
@@ -151,47 +156,47 @@ GmacIomux (
 VOID
 EFIAPI
 NorFspiEnableClock (
-  UINT32 *CruBase
+  UINT32  *CruBase
   )
 {
-  UINTN BaseAddr = (UINTN) CruBase;
+  UINTN  BaseAddr = (UINTN)CruBase;
 
-  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+  MmioWrite32 (BaseAddr + 0x087C, 0x0E000000);
 }
 
 VOID
 EFIAPI
 I2cIomux (
-   UINT32 id
+  UINT32  id
   )
 {
   switch (id) {
-  case 0:
-    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
-    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
-    break;
-  case 1:
-    break;
-  case 2:
-    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
-    break;
-  case 3:
-    GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0
-    GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0
-    break;
-  case 4:
-    break;
-  case 5:
-    break;
-  case 6:
-    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
-    break;
-  case 7:
-    break;
-  default:
-    break;
+    case 0:
+      GpioPinSetFunction (0, GPIO_PIN_PD1, 3); // i2c0_scl_m2
+      GpioPinSetFunction (0, GPIO_PIN_PD2, 3); // i2c0_sda_m2
+      break;
+    case 1:
+      break;
+    case 2:
+      GpioPinSetFunction (0, GPIO_PIN_PB7, 9); // i2c2_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC0, 9); // i2c2_sda_m0
+      break;
+    case 3:
+      GpioPinSetFunction (1, GPIO_PIN_PC1, 9); // i2c3_scl_m0
+      GpioPinSetFunction (1, GPIO_PIN_PC0, 9); // i2c3_sda_m0
+      break;
+    case 4:
+      break;
+    case 5:
+      break;
+    case 6:
+      GpioPinSetFunction (0, GPIO_PIN_PD0, 9); // i2c6_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC7, 9); // i2c6_sda_m0
+      break;
+    case 7:
+      break;
+    default:
+      break;
   }
 }
 
@@ -201,7 +206,7 @@ UsbPortPowerEnable (
   VOID
   )
 {
-  DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n"));
+  DEBUG ((DEBUG_INFO, "UsbPortPowerEnable called\n"));
   /* Set GPIO4 PB0 (USB_HOST_PWREN) output high to power USB ports */
   GpioPinWrite (4, GPIO_PIN_PB0, TRUE);
   GpioPinSetDirection (4, GPIO_PIN_PB0, GPIO_PIN_OUTPUT);
@@ -228,22 +233,22 @@ Usb2PhyResume (
   VOID
   )
 {
-  MmioWrite32(0xfd5d0008, 0x20000000);
-  MmioWrite32(0xfd5d4008, 0x20000000);
-  MmioWrite32(0xfd5d8008, 0x20000000);
-  MmioWrite32(0xfd5dc008, 0x20000000);
-  MmioWrite32(0xfd7f0a10, 0x07000700);
-  MmioWrite32(0xfd7f0a10, 0x07000000);
+  MmioWrite32 (0xfd5d0008, 0x20000000);
+  MmioWrite32 (0xfd5d4008, 0x20000000);
+  MmioWrite32 (0xfd5d8008, 0x20000000);
+  MmioWrite32 (0xfd5dc008, 0x20000000);
+  MmioWrite32 (0xfd7f0a10, 0x07000700);
+  MmioWrite32 (0xfd7f0a10, 0x07000000);
 }
 
 VOID
 EFIAPI
 PcieIoInit (
-  UINT32 Segment
+  UINT32  Segment
   )
 {
   /* Set reset and power IO to gpio output mode */
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4:
       GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
       GpioPinSetDirection (2, GPIO_PIN_PC5, GPIO_PIN_OUTPUT);
@@ -255,7 +260,7 @@ PcieIoInit (
       GpioPinSetDirection (4, GPIO_PIN_PC2, GPIO_PIN_OUTPUT);
       GpioPinSetDirection (4, GPIO_PIN_PA2, GPIO_PIN_OUTPUT);
       break;
-    case PCIE_SEGMENT_PCIE20L2: //rtl8152b
+    case PCIE_SEGMENT_PCIE20L2: // rtl8152b
       GpioPinSetDirection (4, GPIO_PIN_PA4, GPIO_PIN_OUTPUT);
       break;
     default:
@@ -266,13 +271,13 @@ PcieIoInit (
 VOID
 EFIAPI
 PciePowerEn (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
   /* output high to enable power */
 
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4:
       GpioPinWrite (2, GPIO_PIN_PC5, Enable);
       break;
@@ -291,11 +296,11 @@ PciePowerEn (
 VOID
 EFIAPI
 PciePeReset (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4:
       GpioPinWrite (4, GPIO_PIN_PB6, !Enable);
       break;
@@ -313,6 +318,36 @@ PciePeReset (
   }
 }
 
+VOID
+EFIAPI
+HdmiTxIomux (
+  IN UINT32  Id
+  )
+{
+  switch (Id) {
+    case 0:
+      GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
+      GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
+      GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
+      GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
+      break;
+    case 1:
+      GpioPinSetFunction (3, GPIO_PIN_PC4, 5); // hdmim2_tx1_cec
+      GpioPinSetPull (3, GPIO_PIN_PC4, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA6, 5); // hdmim0_tx1_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA6, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (3, GPIO_PIN_PC6, 5); // hdmim1_tx1_scl
+      GpioPinSetPull (3, GPIO_PIN_PC6, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (3, GPIO_PIN_PC5, 5); // hdmim1_tx1_sda
+      GpioPinSetPull (3, GPIO_PIN_PC5, GPIO_PIN_PULL_NONE);
+      break;
+  }
+}
+
 VOID
 EFIAPI
 PwmFanIoSetup (
@@ -324,7 +359,7 @@ PwmFanIoSetup (
 VOID
 EFIAPI
 PwmFanSetSpeed (
-  IN UINT32 Percentage
+  IN UINT32  Percentage
   )
 {
 }
@@ -343,7 +378,7 @@ PlatformInitLeds (
 VOID
 EFIAPI
 PlatformSetStatusLed (
-  IN BOOLEAN Enable
+  IN BOOLEAN  Enable
   )
 {
   GpioPinWrite (2, GPIO_PIN_PB7, Enable);
@@ -352,13 +387,15 @@ PlatformSetStatusLed (
 CONST EFI_GUID *
 EFIAPI
 PlatformGetDtbFileGuid (
-  IN UINT32 CompatMode
+  IN UINT32  CompatMode
   )
 {
-  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+  STATIC CONST EFI_GUID  VendorDtbFileGuid = {
+    // DeviceTree/Vendor.inf
     0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
   };
-  STATIC CONST EFI_GUID MainlineDtbFileGuid = {       // DeviceTree/Mainline.inf
+  STATIC CONST EFI_GUID  MainlineDtbFileGuid = {
+    // DeviceTree/Mainline.inf
     0x84492e97, 0xa10f, 0x49a7, { 0x85, 0xe9, 0x02, 0x5d, 0x19, 0x66, 0xb3, 0x43 }
   };
 
@@ -379,5 +416,5 @@ PlatformEarlyInit (
   )
 {
   // Configure various things specific to this platform
-  GpioPinSetFunction(1, GPIO_PIN_PC4, 0); //jdet
+  GpioPinSetFunction (1, GPIO_PIN_PC4, 0); // jdet
 }

edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/NanoPC-T6.dsc

@@ -28,6 +28,9 @@
   FLASH_DEFINITION               = Silicon/Rockchip/RK3588/RK3588.fdf
   RK_PLATFORM_FVMAIN_MODULES     = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc
 
+  # GMAC is not exposed
+  DEFINE RK3588_GMAC_ENABLE = FALSE
+
   #
   # HYM8563 RTC support
   # I2C location configured by PCDs below.
@@ -72,13 +75,6 @@
   gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
   gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6
 
-  #
-  # CPU Performance default values
-  #
-  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-
   #
   # PCIe/SATA/USB Combo PIPE PHY support flags and default values
   # NanoPC T6 has two 2.5 GBE wired to the first two PCIE2 ports, while the third one is wired to m.2 a+e key
@@ -103,6 +99,15 @@
   #
   gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE
 
+  #
+  # Display support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
+    VOP_OUTPUT_IF_HDMI0,
+    VOP_OUTPUT_IF_HDMI1,
+    VOP_OUTPUT_IF_DP0
+  })}
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.

edk2-rockchip/Platform/FriendlyElec/NanoPi-M6/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -16,29 +16,29 @@
 #include <Soc.h>
 #include <VarStoreData.h>
 
-static struct regulator_init_data rk806_init_data[] = {
+static struct regulator_init_data  rk806_init_data[] = {
   /* Master PMIC */
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
-  //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK4,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK5,  850000),
+  // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK7,  2000000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK8,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK10, 1800000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO2,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO4,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO5,  750000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO1,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO2,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO3,  1200000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO4,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO5,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO6,  1800000),
   /* No dual PMICs on this platform */
 };
 
@@ -49,9 +49,9 @@ SdmmcIoMux (
   )
 {
   /* sdmmc0 iomux (microSD socket) */
-  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
-  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
-  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+  BUS_IOC->GPIO4D_IOMUX_SEL_L  = (0xFFFFUL << 16) | (0x1111); // SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H  = (0x00FFUL << 16) | (0x0011); // SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); // SDMMC_DET
 }
 
 VOID
@@ -61,14 +61,14 @@ SdhciEmmcIoMux (
   )
 {
   /* sdhci0 iomux (eMMC socket) */
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); // EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
 }
 
-#define NS_CRU_BASE         0xFD7C0000
-#define CRU_CLKSEL_CON59    0x03EC
-#define CRU_CLKSEL_CON78    0x0438
+#define NS_CRU_BASE       0xFD7C0000
+#define CRU_CLKSEL_CON59  0x03EC
+#define CRU_CLKSEL_CON78  0x0438
 
 VOID
 EFIAPI
@@ -77,11 +77,11 @@ Rk806SpiIomux (
   )
 {
   /* io mux */
-  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
-  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  // BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  // BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
   PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
   PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+  MmioWrite32 (NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
 }
 
 VOID
@@ -90,24 +90,27 @@ Rk806Configure (
   VOID
   )
 {
-  UINTN RegCfgIndex;
+  UINTN  RegCfgIndex;
 
-  RK806Init();
+  RK806Init ();
 
-  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
-    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
+    RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
+  }
 }
 
 VOID
 EFIAPI
 SetCPULittleVoltage (
-  IN UINT32 Microvolts
+  IN UINT32  Microvolts
   )
 {
-  struct regulator_init_data Rk806CpuLittleSupply =
-        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+  struct regulator_init_data  Rk806CpuLittleSupply =
+    RK8XX_VOLTAGE_INIT (MASTER_BUCK2, Microvolts);
 
-  RK806RegulatorInit(Rk806CpuLittleSupply);
+  RK806RegulatorInit (Rk806CpuLittleSupply);
 }
 
 VOID
@@ -123,7 +126,7 @@ NorFspiIomux (
 VOID
 EFIAPI
 GmacIomux (
-  IN UINT32 Id
+  IN UINT32  Id
   )
 {
   switch (Id) {
@@ -163,47 +166,47 @@ GmacIoPhyReset (
 VOID
 EFIAPI
 NorFspiEnableClock (
-  UINT32 *CruBase
+  UINT32  *CruBase
   )
 {
-  UINTN BaseAddr = (UINTN) CruBase;
+  UINTN  BaseAddr = (UINTN)CruBase;
 
-  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+  MmioWrite32 (BaseAddr + 0x087C, 0x0E000000);
 }
 
 VOID
 EFIAPI
 I2cIomux (
-   UINT32 id
+  UINT32  id
   )
 {
   switch (id) {
-  case 0:
-    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
-    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
-    break;
-  case 1:
-    break;
-  case 2:
-    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
-    break;
-  case 3:
-    GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0
-    GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0
-    break;
-  case 4:
-    break;
-  case 5:
-    break;
-  case 6:
-    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
-    break;
-  case 7:
-    break;
-  default:
-    break;
+    case 0:
+      GpioPinSetFunction (0, GPIO_PIN_PD1, 3); // i2c0_scl_m2
+      GpioPinSetFunction (0, GPIO_PIN_PD2, 3); // i2c0_sda_m2
+      break;
+    case 1:
+      break;
+    case 2:
+      GpioPinSetFunction (0, GPIO_PIN_PB7, 9); // i2c2_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC0, 9); // i2c2_sda_m0
+      break;
+    case 3:
+      GpioPinSetFunction (1, GPIO_PIN_PC1, 9); // i2c3_scl_m0
+      GpioPinSetFunction (1, GPIO_PIN_PC0, 9); // i2c3_sda_m0
+      break;
+    case 4:
+      break;
+    case 5:
+      break;
+    case 6:
+      GpioPinSetFunction (0, GPIO_PIN_PD0, 9); // i2c6_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC7, 9); // i2c6_sda_m0
+      break;
+    case 7:
+      break;
+    default:
+      break;
   }
 }
 
@@ -213,7 +216,7 @@ UsbPortPowerEnable (
   VOID
   )
 {
-  DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n"));
+  DEBUG ((DEBUG_INFO, "UsbPortPowerEnable called\n"));
   /* Set GPIO4 PB5 (USB_HOST_PWREN) output high to power USB ports */
   GpioPinWrite (4, GPIO_PIN_PB5, TRUE);
   GpioPinSetDirection (4, GPIO_PIN_PB5, GPIO_PIN_OUTPUT);
@@ -241,22 +244,22 @@ Usb2PhyResume (
   VOID
   )
 {
-  MmioWrite32(0xfd5d0008, 0x20000000);
-  MmioWrite32(0xfd5d4008, 0x20000000);
-  MmioWrite32(0xfd5d8008, 0x20000000);
-  MmioWrite32(0xfd5dc008, 0x20000000);
-  MmioWrite32(0xfd7f0a10, 0x07000700);
-  MmioWrite32(0xfd7f0a10, 0x07000000);
+  MmioWrite32 (0xfd5d0008, 0x20000000);
+  MmioWrite32 (0xfd5d4008, 0x20000000);
+  MmioWrite32 (0xfd5d8008, 0x20000000);
+  MmioWrite32 (0xfd5dc008, 0x20000000);
+  MmioWrite32 (0xfd7f0a10, 0x07000700);
+  MmioWrite32 (0xfd7f0a10, 0x07000000);
 }
 
 VOID
 EFIAPI
 PcieIoInit (
-  UINT32 Segment
+  UINT32  Segment
   )
 {
   /* Set reset and power IO to gpio output mode */
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE20L1: // RTL8152BG
       // GPIO1_A7_u - PCIE20x1_1_PERSTn_M2
       GpioPinSetDirection (1, GPIO_PIN_PA7, GPIO_PIN_OUTPUT);
@@ -273,8 +276,8 @@ PcieIoInit (
 VOID
 EFIAPI
 PciePowerEn (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
   /* nothing to power on */
@@ -283,11 +286,11 @@ PciePowerEn (
 VOID
 EFIAPI
 PciePeReset (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE20L1:
       GpioPinWrite (1, GPIO_PIN_PA7, !Enable);
       break;
@@ -299,6 +302,26 @@ PciePeReset (
   }
 }
 
+VOID
+EFIAPI
+HdmiTxIomux (
+  IN UINT32  Id
+  )
+{
+  switch (Id) {
+    case 0:
+      GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
+      GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
+      GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
+      GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
+      break;
+  }
+}
+
 VOID
 EFIAPI
 PwmFanIoSetup (
@@ -310,7 +333,7 @@ PwmFanIoSetup (
 VOID
 EFIAPI
 PwmFanSetSpeed (
-  IN UINT32 Percentage
+  IN UINT32  Percentage
   )
 {
 }
@@ -329,7 +352,7 @@ PlatformInitLeds (
 VOID
 EFIAPI
 PlatformSetStatusLed (
-  IN BOOLEAN Enable
+  IN BOOLEAN  Enable
   )
 {
   GpioPinWrite (1, GPIO_PIN_PC1, Enable);
@@ -338,10 +361,11 @@ PlatformSetStatusLed (
 CONST EFI_GUID *
 EFIAPI
 PlatformGetDtbFileGuid (
-  IN UINT32 CompatMode
+  IN UINT32  CompatMode
   )
 {
-  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+  STATIC CONST EFI_GUID  VendorDtbFileGuid = {
+    // DeviceTree/Vendor.inf
     0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
   };
 

edk2-rockchip/Platform/FriendlyElec/NanoPi-M6/NanoPi-M6.dsc

@@ -74,13 +74,6 @@
   gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
   gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6
 
-  #
-  # CPU Performance default values
-  #
-  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-
   #
   # PCIe/SATA/USB Combo PIPE PHY support flags and default values
   #
@@ -101,6 +94,13 @@
   gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE
   gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x42
 
+  #
+  # Display support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
+    VOP_OUTPUT_IF_HDMI0
+  })}
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.

edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/DeviceTree/Mainline.inf

@@ -14,7 +14,7 @@
   VERSION_STRING                 = 1.0
 
 [Sources]
-  devicetree/mainline/upstream/src/arm64/rockchip/rk3588s-nanopi-r6c.dts
+  devicetree/mainline/rk3588s-nanopi-r6c-fixup.dts
 
 [Packages]
   MdePkg/MdePkg.dec

edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -16,29 +16,29 @@
 #include <Soc.h>
 #include <VarStoreData.h>
 
-static struct regulator_init_data rk806_init_data[] = {
+static struct regulator_init_data  rk806_init_data[] = {
   /* Master PMIC */
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
-  //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK4,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK5,  850000),
+  // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK7,  2000000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK8,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK10, 1800000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO2,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO4,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO5,  750000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO1,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO2,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO3,  1200000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO4,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO5,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO6,  1800000),
   /* No dual PMICs on this platform */
 };
 
@@ -49,9 +49,9 @@ SdmmcIoMux (
   )
 {
   /* sdmmc0 iomux (microSD socket) */
-  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
-  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
-  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+  BUS_IOC->GPIO4D_IOMUX_SEL_L  = (0xFFFFUL << 16) | (0x1111); // SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H  = (0x00FFUL << 16) | (0x0011); // SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); // SDMMC_DET
 }
 
 VOID
@@ -61,14 +61,14 @@ SdhciEmmcIoMux (
   )
 {
   /* sdhci0 iomux (eMMC socket) */
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); // EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
 }
 
-#define NS_CRU_BASE         0xFD7C0000
-#define CRU_CLKSEL_CON59    0x03EC
-#define CRU_CLKSEL_CON78    0x0438
+#define NS_CRU_BASE       0xFD7C0000
+#define CRU_CLKSEL_CON59  0x03EC
+#define CRU_CLKSEL_CON78  0x0438
 
 VOID
 EFIAPI
@@ -77,11 +77,11 @@ Rk806SpiIomux (
   )
 {
   /* io mux */
-  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
-  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  // BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  // BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
   PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
   PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+  MmioWrite32 (NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
 }
 
 VOID
@@ -90,24 +90,27 @@ Rk806Configure (
   VOID
   )
 {
-  UINTN RegCfgIndex;
+  UINTN  RegCfgIndex;
 
-  RK806Init();
+  RK806Init ();
 
-  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
-    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
+    RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
+  }
 }
 
 VOID
 EFIAPI
 SetCPULittleVoltage (
-  IN UINT32 Microvolts
+  IN UINT32  Microvolts
   )
 {
-  struct regulator_init_data Rk806CpuLittleSupply =
-        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+  struct regulator_init_data  Rk806CpuLittleSupply =
+    RK8XX_VOLTAGE_INIT (MASTER_BUCK2, Microvolts);
 
-  RK806RegulatorInit(Rk806CpuLittleSupply);
+  RK806RegulatorInit (Rk806CpuLittleSupply);
 }
 
 VOID
@@ -123,7 +126,7 @@ NorFspiIomux (
 VOID
 EFIAPI
 GmacIomux (
-  IN UINT32 Id
+  IN UINT32  Id
   )
 {
   switch (Id) {
@@ -163,47 +166,47 @@ GmacIoPhyReset (
 VOID
 EFIAPI
 NorFspiEnableClock (
-  UINT32 *CruBase
+  UINT32  *CruBase
   )
 {
-  UINTN BaseAddr = (UINTN) CruBase;
+  UINTN  BaseAddr = (UINTN)CruBase;
 
-  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+  MmioWrite32 (BaseAddr + 0x087C, 0x0E000000);
 }
 
 VOID
 EFIAPI
 I2cIomux (
-   UINT32 id
+  UINT32  id
   )
 {
   switch (id) {
-  case 0:
-    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
-    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
-    break;
-  case 1:
-    break;
-  case 2:
-    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
-    break;
-  case 3:
-    GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0
-    GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0
-    break;
-  case 4:
-    break;
-  case 5:
-    break;
-  case 6:
-    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
-    break;
-  case 7:
-    break;
-  default:
-    break;
+    case 0:
+      GpioPinSetFunction (0, GPIO_PIN_PD1, 3); // i2c0_scl_m2
+      GpioPinSetFunction (0, GPIO_PIN_PD2, 3); // i2c0_sda_m2
+      break;
+    case 1:
+      break;
+    case 2:
+      GpioPinSetFunction (0, GPIO_PIN_PB7, 9); // i2c2_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC0, 9); // i2c2_sda_m0
+      break;
+    case 3:
+      GpioPinSetFunction (1, GPIO_PIN_PC1, 9); // i2c3_scl_m0
+      GpioPinSetFunction (1, GPIO_PIN_PC0, 9); // i2c3_sda_m0
+      break;
+    case 4:
+      break;
+    case 5:
+      break;
+    case 6:
+      GpioPinSetFunction (0, GPIO_PIN_PD0, 9); // i2c6_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC7, 9); // i2c6_sda_m0
+      break;
+    case 7:
+      break;
+    default:
+      break;
   }
 }
 
@@ -213,7 +216,7 @@ UsbPortPowerEnable (
   VOID
   )
 {
-  DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n"));
+  DEBUG ((DEBUG_INFO, "UsbPortPowerEnable called\n"));
   /* Set GPIO4 PB5 (USB_HOST_PWREN) output high to power USB ports */
   GpioPinWrite (4, GPIO_PIN_PB5, TRUE);
   GpioPinSetDirection (4, GPIO_PIN_PB5, GPIO_PIN_OUTPUT);
@@ -241,22 +244,22 @@ Usb2PhyResume (
   VOID
   )
 {
-  MmioWrite32(0xfd5d0008, 0x20000000);
-  MmioWrite32(0xfd5d4008, 0x20000000);
-  MmioWrite32(0xfd5d8008, 0x20000000);
-  MmioWrite32(0xfd5dc008, 0x20000000);
-  MmioWrite32(0xfd7f0a10, 0x07000700);
-  MmioWrite32(0xfd7f0a10, 0x07000000);
+  MmioWrite32 (0xfd5d0008, 0x20000000);
+  MmioWrite32 (0xfd5d4008, 0x20000000);
+  MmioWrite32 (0xfd5d8008, 0x20000000);
+  MmioWrite32 (0xfd5dc008, 0x20000000);
+  MmioWrite32 (0xfd7f0a10, 0x07000700);
+  MmioWrite32 (0xfd7f0a10, 0x07000000);
 }
 
 VOID
 EFIAPI
 PcieIoInit (
-  UINT32 Segment
+  UINT32  Segment
   )
 {
   /* Set reset and power IO to gpio output mode */
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE20L1: // RTL8152BG
       // GPIO1_A7_u - PCIE20x1_1_PERSTn_M2
       GpioPinSetDirection (1, GPIO_PIN_PA7, GPIO_PIN_OUTPUT);
@@ -273,8 +276,8 @@ PcieIoInit (
 VOID
 EFIAPI
 PciePowerEn (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
   /* nothing to power on */
@@ -283,11 +286,11 @@ PciePowerEn (
 VOID
 EFIAPI
 PciePeReset (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE20L1:
       GpioPinWrite (1, GPIO_PIN_PA7, !Enable);
       break;
@@ -299,6 +302,26 @@ PciePeReset (
   }
 }
 
+VOID
+EFIAPI
+HdmiTxIomux (
+  IN UINT32  Id
+  )
+{
+  switch (Id) {
+    case 0:
+      GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
+      GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
+      GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
+      GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
+      break;
+  }
+}
+
 VOID
 EFIAPI
 PwmFanIoSetup (
@@ -310,7 +333,7 @@ PwmFanIoSetup (
 VOID
 EFIAPI
 PwmFanSetSpeed (
-  IN UINT32 Percentage
+  IN UINT32  Percentage
   )
 {
 }
@@ -329,7 +352,7 @@ PlatformInitLeds (
 VOID
 EFIAPI
 PlatformSetStatusLed (
-  IN BOOLEAN Enable
+  IN BOOLEAN  Enable
   )
 {
   GpioPinWrite (1, GPIO_PIN_PC1, Enable);
@@ -338,13 +361,15 @@ PlatformSetStatusLed (
 CONST EFI_GUID *
 EFIAPI
 PlatformGetDtbFileGuid (
-  IN UINT32 CompatMode
+  IN UINT32  CompatMode
   )
 {
-  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+  STATIC CONST EFI_GUID  VendorDtbFileGuid = {
+    // DeviceTree/Vendor.inf
     0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
   };
-  STATIC CONST EFI_GUID MainlineDtbFileGuid = {       // DeviceTree/Mainline.inf
+  STATIC CONST EFI_GUID  MainlineDtbFileGuid = {
+    // DeviceTree/Mainline.inf
     0x84492e97, 0xa10f, 0x49a7, { 0x85, 0xe9, 0x02, 0x5d, 0x19, 0x66, 0xb3, 0x43 }
   };
 

edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/NanoPi-R6C.dsc

@@ -73,13 +73,6 @@
   gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
   gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6
 
-  #
-  # CPU Performance default values
-  #
-  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-
   #
   # PCIe/SATA/USB Combo PIPE PHY support flags and default values
   #
@@ -100,6 +93,13 @@
   gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE
   gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x42
 
+  #
+  # Display support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
+    VOP_OUTPUT_IF_HDMI0
+  })}
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.

edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/DeviceTree/Mainline.inf

@@ -14,7 +14,7 @@
   VERSION_STRING                 = 1.0
 
 [Sources]
-  devicetree/mainline/upstream/src/arm64/rockchip/rk3588s-nanopi-r6s.dts
+  devicetree/mainline/rk3588s-nanopi-r6s-fixup.dts
 
 [Packages]
   MdePkg/MdePkg.dec

edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -16,29 +16,29 @@
 #include <Soc.h>
 #include <VarStoreData.h>
 
-static struct regulator_init_data rk806_init_data[] = {
+static struct regulator_init_data  rk806_init_data[] = {
   /* Master PMIC */
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
-  //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK4,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK5,  850000),
+  // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK7,  2000000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK8,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK10, 1800000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO2,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO4,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO5,  750000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO1,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO2,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO3,  1200000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO4,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO5,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO6,  1800000),
   /* No dual PMICs on this platform */
 };
 
@@ -49,9 +49,9 @@ SdmmcIoMux (
   )
 {
   /* sdmmc0 iomux (microSD socket) */
-  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
-  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
-  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+  BUS_IOC->GPIO4D_IOMUX_SEL_L  = (0xFFFFUL << 16) | (0x1111); // SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H  = (0x00FFUL << 16) | (0x0011); // SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); // SDMMC_DET
 }
 
 VOID
@@ -64,9 +64,9 @@ SdhciEmmcIoMux (
   /* Do not override, set by earlier boot stages. */
 }
 
-#define NS_CRU_BASE         0xFD7C0000
-#define CRU_CLKSEL_CON59    0x03EC
-#define CRU_CLKSEL_CON78    0x0438
+#define NS_CRU_BASE       0xFD7C0000
+#define CRU_CLKSEL_CON59  0x03EC
+#define CRU_CLKSEL_CON78  0x0438
 
 VOID
 EFIAPI
@@ -75,11 +75,11 @@ Rk806SpiIomux (
   )
 {
   /* io mux */
-  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
-  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  // BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  // BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
   PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
   PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+  MmioWrite32 (NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
 }
 
 VOID
@@ -88,24 +88,27 @@ Rk806Configure (
   VOID
   )
 {
-  UINTN RegCfgIndex;
+  UINTN  RegCfgIndex;
 
-  RK806Init();
+  RK806Init ();
 
-  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
-    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
+    RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
+  }
 }
 
 VOID
 EFIAPI
 SetCPULittleVoltage (
-  IN UINT32 Microvolts
+  IN UINT32  Microvolts
   )
 {
-  struct regulator_init_data Rk806CpuLittleSupply =
-        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+  struct regulator_init_data  Rk806CpuLittleSupply =
+    RK8XX_VOLTAGE_INIT (MASTER_BUCK2, Microvolts);
 
-  RK806RegulatorInit(Rk806CpuLittleSupply);
+  RK806RegulatorInit (Rk806CpuLittleSupply);
 }
 
 VOID
@@ -121,7 +124,7 @@ NorFspiIomux (
 VOID
 EFIAPI
 GmacIomux (
-  IN UINT32 Id
+  IN UINT32  Id
   )
 {
   switch (Id) {
@@ -161,47 +164,47 @@ GmacIoPhyReset (
 VOID
 EFIAPI
 NorFspiEnableClock (
-  UINT32 *CruBase
+  UINT32  *CruBase
   )
 {
-  UINTN BaseAddr = (UINTN) CruBase;
+  UINTN  BaseAddr = (UINTN)CruBase;
 
-  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+  MmioWrite32 (BaseAddr + 0x087C, 0x0E000000);
 }
 
 VOID
 EFIAPI
 I2cIomux (
-   UINT32 id
+  UINT32  id
   )
 {
   switch (id) {
-  case 0:
-    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
-    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
-    break;
-  case 1:
-    break;
-  case 2:
-    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
-    break;
-  case 3:
-    GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0
-    GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0
-    break;
-  case 4:
-    break;
-  case 5:
-    break;
-  case 6:
-    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
-    break;
-  case 7:
-    break;
-  default:
-    break;
+    case 0:
+      GpioPinSetFunction (0, GPIO_PIN_PD1, 3); // i2c0_scl_m2
+      GpioPinSetFunction (0, GPIO_PIN_PD2, 3); // i2c0_sda_m2
+      break;
+    case 1:
+      break;
+    case 2:
+      GpioPinSetFunction (0, GPIO_PIN_PB7, 9); // i2c2_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC0, 9); // i2c2_sda_m0
+      break;
+    case 3:
+      GpioPinSetFunction (1, GPIO_PIN_PC1, 9); // i2c3_scl_m0
+      GpioPinSetFunction (1, GPIO_PIN_PC0, 9); // i2c3_sda_m0
+      break;
+    case 4:
+      break;
+    case 5:
+      break;
+    case 6:
+      GpioPinSetFunction (0, GPIO_PIN_PD0, 9); // i2c6_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC7, 9); // i2c6_sda_m0
+      break;
+    case 7:
+      break;
+    default:
+      break;
   }
 }
 
@@ -211,7 +214,7 @@ UsbPortPowerEnable (
   VOID
   )
 {
-  DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n"));
+  DEBUG ((DEBUG_INFO, "UsbPortPowerEnable called\n"));
 
   /* Set GPIO4 PB5 (USB_HOST_PWREN) output high to power USB ports */
   GpioPinSetDirection (4, GPIO_PIN_PB5, GPIO_PIN_OUTPUT);
@@ -228,22 +231,22 @@ Usb2PhyResume (
   VOID
   )
 {
-  MmioWrite32(0xfd5d0008, 0x20000000);
-  MmioWrite32(0xfd5d4008, 0x20000000);
-  MmioWrite32(0xfd5d8008, 0x20000000);
-  MmioWrite32(0xfd5dc008, 0x20000000);
-  MmioWrite32(0xfd7f0a10, 0x07000700);
-  MmioWrite32(0xfd7f0a10, 0x07000000);
+  MmioWrite32 (0xfd5d0008, 0x20000000);
+  MmioWrite32 (0xfd5d4008, 0x20000000);
+  MmioWrite32 (0xfd5d8008, 0x20000000);
+  MmioWrite32 (0xfd5dc008, 0x20000000);
+  MmioWrite32 (0xfd7f0a10, 0x07000700);
+  MmioWrite32 (0xfd7f0a10, 0x07000000);
 }
 
 VOID
 EFIAPI
 PcieIoInit (
-  UINT32 Segment
+  UINT32  Segment
   )
 {
   /* found info from nanopi r6s dtb */
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE20L1: // rtl8152b
       // PCIE20x1_1_PERSTn_M2
       GpioPinSetDirection (1, GPIO_PIN_PA7, GPIO_PIN_OUTPUT);
@@ -260,8 +263,8 @@ PcieIoInit (
 VOID
 EFIAPI
 PciePowerEn (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
   /* nothing to power on */
@@ -270,11 +273,11 @@ PciePowerEn (
 VOID
 EFIAPI
 PciePeReset (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE20L1: // rtl8152b
       GpioPinWrite (1, GPIO_PIN_PA7, !Enable);
       break;
@@ -286,6 +289,26 @@ PciePeReset (
   }
 }
 
+VOID
+EFIAPI
+HdmiTxIomux (
+  IN UINT32  Id
+  )
+{
+  switch (Id) {
+    case 0:
+      GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
+      GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
+      GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
+      GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
+      break;
+  }
+}
+
 VOID
 EFIAPI
 PwmFanIoSetup (
@@ -297,7 +320,7 @@ PwmFanIoSetup (
 VOID
 EFIAPI
 PwmFanSetSpeed (
-  IN UINT32 Percentage
+  IN UINT32  Percentage
   )
 {
 }
@@ -316,7 +339,7 @@ PlatformInitLeds (
 VOID
 EFIAPI
 PlatformSetStatusLed (
-  IN BOOLEAN Enable
+  IN BOOLEAN  Enable
   )
 {
   GpioPinWrite (1, GPIO_PIN_PC1, Enable);
@@ -325,13 +348,15 @@ PlatformSetStatusLed (
 CONST EFI_GUID *
 EFIAPI
 PlatformGetDtbFileGuid (
-  IN UINT32 CompatMode
+  IN UINT32  CompatMode
   )
 {
-  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+  STATIC CONST EFI_GUID  VendorDtbFileGuid = {
+    // DeviceTree/Vendor.inf
     0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
   };
-  STATIC CONST EFI_GUID MainlineDtbFileGuid = {       // DeviceTree/Mainline.inf
+  STATIC CONST EFI_GUID  MainlineDtbFileGuid = {
+    // DeviceTree/Mainline.inf
     0x84492e97, 0xa10f, 0x49a7, { 0x85, 0xe9, 0x02, 0x5d, 0x19, 0x66, 0xb3, 0x43 }
   };
 

edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/NanoPi-R6S.dsc

@@ -72,13 +72,6 @@
   gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
   gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6
 
-  #
-  # CPU Performance default values
-  #
-  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-
   #
   # PCIe/SATA/USB Combo PIPE PHY support flags and default values
   #
@@ -99,6 +92,13 @@
   gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE
   gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x42
 
+  #
+  # Display support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
+    VOP_OUTPUT_IF_HDMI0
+  })}
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.

edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Drivers/LogoDxe/Logo.c

@@ -19,15 +19,15 @@
 #include <Library/DebugLib.h>
 
 typedef struct {
-  EFI_IMAGE_ID                          ImageId;
-  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
-  INTN                                  OffsetX;
-  INTN                                  OffsetY;
+  EFI_IMAGE_ID                             ImageId;
+  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE    Attribute;
+  INTN                                     OffsetX;
+  INTN                                     OffsetY;
 } LOGO_ENTRY;
 
-STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
-STATIC EFI_HII_HANDLE            mHiiHandle;
-STATIC LOGO_ENTRY                mLogos[] = {
+STATIC EFI_HII_IMAGE_EX_PROTOCOL  *mHiiImageEx;
+STATIC EFI_HII_HANDLE             mHiiHandle;
+STATIC LOGO_ENTRY                 mLogos[] = {
   {
     IMAGE_TOKEN (IMG_LOGO),
     EdkiiPlatformLogoDisplayAttributeCenter,
@@ -53,18 +53,19 @@ STATIC
 EFI_STATUS
 EFIAPI
 GetImage (
-  IN     EDKII_PLATFORM_LOGO_PROTOCOL          *This,
-  IN OUT UINT32                                *Instance,
-     OUT EFI_IMAGE_INPUT                       *Image,
-     OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
-     OUT INTN                                  *OffsetX,
-     OUT INTN                                  *OffsetY
+  IN     EDKII_PLATFORM_LOGO_PROTOCOL        *This,
+  IN OUT UINT32                              *Instance,
+  OUT EFI_IMAGE_INPUT                        *Image,
+  OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE  *Attribute,
+  OUT INTN                                   *OffsetX,
+  OUT INTN                                   *OffsetY
   )
 {
-  UINT32 Current;
+  UINT32  Current;
 
-  if (Instance == NULL || Image == NULL ||
-      Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
+  if ((Instance == NULL) || (Image == NULL) ||
+      (Attribute == NULL) || (OffsetX == NULL) || (OffsetY == NULL))
+  {
     return EFI_INVALID_PARAMETER;
   }
 
@@ -78,11 +79,15 @@ GetImage (
   *OffsetX   = mLogos[Current].OffsetX;
   *OffsetY   = mLogos[Current].OffsetY;
 
-  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
-                        mLogos[Current].ImageId, Image);
+  return mHiiImageEx->GetImageEx (
+                        mHiiImageEx,
+                        mHiiHandle,
+                        mLogos[Current].ImageId,
+                        Image
+                        );
 }
 
-STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+STATIC EDKII_PLATFORM_LOGO_PROTOCOL  mPlatformLogo = {
   GetImage
 };
 
@@ -101,44 +106,66 @@ STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
 EFI_STATUS
 EFIAPI
 InitializeLogo (
-  IN EFI_HANDLE               ImageHandle,
-  IN EFI_SYSTEM_TABLE         *SystemTable
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
-  EFI_STATUS                  Status;
-  EFI_HII_PACKAGE_LIST_HEADER *PackageList;
-  EFI_HII_DATABASE_PROTOCOL   *HiiDatabase;
-  EFI_HANDLE                  Handle;
+  EFI_STATUS                   Status;
+  EFI_HII_PACKAGE_LIST_HEADER  *PackageList;
+  EFI_HII_DATABASE_PROTOCOL    *HiiDatabase;
+  EFI_HANDLE                   Handle;
 
-  Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
-                  (VOID **) &HiiDatabase);
+  Status = gBS->LocateProtocol (
+                  &gEfiHiiDatabaseProtocolGuid,
+                  NULL,
+                  (VOID **)&HiiDatabase
+                  );
   ASSERT_EFI_ERROR (Status);
 
-  Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
-                  (VOID **) &mHiiImageEx);
+  Status = gBS->LocateProtocol (
+                  &gEfiHiiImageExProtocolGuid,
+                  NULL,
+                  (VOID **)&mHiiImageEx
+                  );
   ASSERT_EFI_ERROR (Status);
 
   //
   // Retrieve HII package list from ImageHandle
   //
-  Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
-                  (VOID **) &PackageList, ImageHandle, NULL,
-                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+  Status = gBS->OpenProtocol (
+                  ImageHandle,
+                  &gEfiHiiPackageListProtocolGuid,
+                  (VOID **)&PackageList,
+                  ImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
   if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR,
-      "HII Image Package with logo not found in PE/COFF resource section\n"));
+    DEBUG ((
+      DEBUG_ERROR,
+      "HII Image Package with logo not found in PE/COFF resource section\n"
+      ));
     return Status;
   }
 
   //
   // Publish HII package list to HII Database.
   //
-  Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
-                          &mHiiHandle);
+  Status = HiiDatabase->NewPackageList (
+                          HiiDatabase,
+                          PackageList,
+                          NULL,
+                          &mHiiHandle
+                          );
   if (!EFI_ERROR (Status)) {
     Handle = NULL;
-    Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
-                    &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
+    Status = gBS->InstallMultipleProtocolInterfaces (
+                    &Handle,
+                    &gEdkiiPlatformLogoProtocolGuid,
+                    &mPlatformLogo,
+                    NULL
+                    );
   }
+
   return Status;
 }

edk2-rockchip/Platform/FydeInnovations/FydetabDuo/FydetabDuo.dsc

@@ -27,6 +27,9 @@
   FLASH_DEFINITION               = Silicon/Rockchip/RK3588/RK3588.fdf
   RK_PLATFORM_FVMAIN_MODULES     = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc
 
+  # GMAC is not exposed
+  DEFINE RK3588_GMAC_ENABLE = FALSE
+
   #
   # HYM8563 RTC support
   # I2C location configured by PCDs below.
@@ -74,13 +77,6 @@
   gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
   gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6
 
-  #
-  # CPU Performance default values
-  #
-  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX)
-  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX)
-  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX)
-
   #
   # PCIe/SATA/USB Combo PIPE PHY support flags and default values
   #
@@ -100,6 +96,15 @@
   # SD card detect signal is inverted
   gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken|TRUE
 
+  #
+  # Display support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
+    VOP_OUTPUT_IF_DP0,
+    VOP_OUTPUT_IF_MIPI0
+  })}
+  gRK3588TokenSpaceGuid.PcdDisplayRotationDefault|90
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.

edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Library/RockchipPlatformLib/CsotDsiPanel.c

@@ -1,6 +1,6 @@
 /** @file
  *
- *  Copyright (c) 2024, Mario Bălănică <mariobalanica02@gmail.com>
+ *  Copyright (c) 2024-2025, Mario Bălănică <mariobalanica02@gmail.com>
  *
  *  SPDX-License-Identifier: BSD-2-Clause-Patent
  *
@@ -130,25 +130,17 @@ STATIC ROCKCHIP_DSI_PANEL_PROTOCOL  mCsotDsiPanel = {
   .InitSequenceLength = ARRAY_SIZE (mCsotDsiInitSequence),
 
   .NativeMode         = {
-    .CrtcId     = 2,
-    .OscFreq    = 275000000,
-    .Horizontal = {
-      .Resolution = 1600,
-      .Sync       = 20,
-      .BackPorch  = 40,
-      .FrontPorch = 60
-    },
-    .Vertical         = {
-      .Resolution = 2560,
-      .Sync       = 4,
-      .BackPorch  = 18,
-      .FrontPorch = 112
-    },
-    .HsyncActive     = 0,
-    .VsyncActive     = 0,
-    .DenActive       = 0,
-    .ClkActive       = 0,
-    .VpsConfigModeID = 1
+    .OscFreq     = 275000,
+    .HActive     = 1600,
+    .HFrontPorch = 60,
+    .HSync       = 20,
+    .HBackPorch  = 40,
+    .HSyncActive = 0,
+    .VActive     = 2560,
+    .VFrontPorch = 112,
+    .VSync       = 4,
+    .VBackPorch  = 18,
+    .VSyncActive = 0,
   },
 
   .Prepare            = CsotDsiPanelPrepare,

edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -17,29 +17,29 @@
 #include <Soc.h>
 #include <VarStoreData.h>
 
-static struct regulator_init_data rk806_init_data[] = {
+static struct regulator_init_data  rk806_init_data[] = {
   /* Master PMIC */
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
- // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK4,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK5,  850000),
+  // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK7,  2000000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK8,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK10, 1800000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO2,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO4,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO5,  750000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO1,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO2,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO3,  1200000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO4,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO5,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO6,  1800000),
 
   /* No dual PMICs on this platform */
 };
@@ -51,9 +51,9 @@ SdmmcIoMux (
   )
 {
   /* sdmmc0 iomux (microSD socket) */
-  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
-  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
-  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+  BUS_IOC->GPIO4D_IOMUX_SEL_L  = (0xFFFFUL << 16) | (0x1111); // SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H  = (0x00FFUL << 16) | (0x0011); // SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); // SDMMC_DET
 }
 
 VOID
@@ -66,9 +66,9 @@ SdhciEmmcIoMux (
   /* Do not override, set by earlier boot stages. */
 }
 
-#define NS_CRU_BASE         0xFD7C0000
-#define CRU_CLKSEL_CON59    0x03EC
-#define CRU_CLKSEL_CON78    0x0438
+#define NS_CRU_BASE       0xFD7C0000
+#define CRU_CLKSEL_CON59  0x03EC
+#define CRU_CLKSEL_CON78  0x0438
 
 VOID
 EFIAPI
@@ -77,11 +77,11 @@ Rk806SpiIomux (
   )
 {
   /* io mux */
-  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
-  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  // BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  // BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
   PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
   PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+  MmioWrite32 (NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
 }
 
 VOID
@@ -90,24 +90,27 @@ Rk806Configure (
   VOID
   )
 {
-  UINTN RegCfgIndex;
+  UINTN  RegCfgIndex;
 
-  RK806Init();
+  RK806Init ();
 
-  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
-    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
+    RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
+  }
 }
 
 VOID
 EFIAPI
 SetCPULittleVoltage (
-  IN UINT32 Microvolts
+  IN UINT32  Microvolts
   )
 {
-  struct regulator_init_data Rk806CpuLittleSupply =
-        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+  struct regulator_init_data  Rk806CpuLittleSupply =
+    RK8XX_VOLTAGE_INIT (MASTER_BUCK2, Microvolts);
 
-  RK806RegulatorInit(Rk806CpuLittleSupply);
+  RK806RegulatorInit (Rk806CpuLittleSupply);
 }
 
 VOID
@@ -123,7 +126,7 @@ NorFspiIomux (
 VOID
 EFIAPI
 GmacIomux (
-  IN UINT32 Id
+  IN UINT32  Id
   )
 {
   /* No GMAC here */
@@ -132,53 +135,53 @@ GmacIomux (
 VOID
 EFIAPI
 NorFspiEnableClock (
-  UINT32 *CruBase
+  UINT32  *CruBase
   )
 {
-  UINTN BaseAddr = (UINTN) CruBase;
+  UINTN  BaseAddr = (UINTN)CruBase;
 
-  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+  MmioWrite32 (BaseAddr + 0x087C, 0x0E000000);
 }
 
 VOID
 EFIAPI
 I2cIomux (
-   UINT32 id
+  UINT32  id
   )
 {
   switch (id) {
-  case 0:
-    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
-    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
-    break;
-  case 1:
-    break;
-  case 2:
-    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
-    break;
-  case 3:
-    GpioPinSetFunction(3, GPIO_PIN_PB7, 9); //i2c3_scl_m1
-    GpioPinSetFunction(3, GPIO_PIN_PC0, 9); //i2c3_sda_m1
-    break;
-  case 4:
-    GpioPinSetFunction(1, GPIO_PIN_PA3, 9); //i2c4_scl_m3
-    GpioPinSetFunction(1, GPIO_PIN_PA2, 9); //i2c4_sda_m3
-    break;
-  case 5:
-    GpioPinSetFunction(1, GPIO_PIN_PB6, 9); //i2c5_scl_m3
-    GpioPinSetFunction(1, GPIO_PIN_PB7, 9); //i2c5_sda_m3
-    break;
-  case 6:
-    GpioPinSetFunction(4, GPIO_PIN_PB1, 9); //i2c6_scl_m3
-    GpioPinSetFunction(4, GPIO_PIN_PB0, 9); //i2c6_sda_m3
-    break;
-  case 7:
-    GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0
-    GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0
-    break;
-  default:
-    break;
+    case 0:
+      GpioPinSetFunction (0, GPIO_PIN_PD1, 3); // i2c0_scl_m2
+      GpioPinSetFunction (0, GPIO_PIN_PD2, 3); // i2c0_sda_m2
+      break;
+    case 1:
+      break;
+    case 2:
+      GpioPinSetFunction (0, GPIO_PIN_PB7, 9); // i2c2_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC0, 9); // i2c2_sda_m0
+      break;
+    case 3:
+      GpioPinSetFunction (3, GPIO_PIN_PB7, 9); // i2c3_scl_m1
+      GpioPinSetFunction (3, GPIO_PIN_PC0, 9); // i2c3_sda_m1
+      break;
+    case 4:
+      GpioPinSetFunction (1, GPIO_PIN_PA3, 9); // i2c4_scl_m3
+      GpioPinSetFunction (1, GPIO_PIN_PA2, 9); // i2c4_sda_m3
+      break;
+    case 5:
+      GpioPinSetFunction (1, GPIO_PIN_PB6, 9); // i2c5_scl_m3
+      GpioPinSetFunction (1, GPIO_PIN_PB7, 9); // i2c5_sda_m3
+      break;
+    case 6:
+      GpioPinSetFunction (4, GPIO_PIN_PB1, 9); // i2c6_scl_m3
+      GpioPinSetFunction (4, GPIO_PIN_PB0, 9); // i2c6_sda_m3
+      break;
+    case 7:
+      GpioPinSetFunction (1, GPIO_PIN_PD0, 9); // i2c7_scl_m0
+      GpioPinSetFunction (1, GPIO_PIN_PD1, 9); // i2c7_sda_m0
+      break;
+    default:
+      break;
   }
 }
 
@@ -188,7 +191,6 @@ UsbPortPowerEnable (
   VOID
   )
 {
-
 }
 
 VOID
@@ -197,22 +199,23 @@ Usb2PhyResume (
   VOID
   )
 {
-  MmioWrite32(0xfd5d0008, 0x20000000);
-  MmioWrite32(0xfd5d4008, 0x20000000);
-  MmioWrite32(0xfd5d8008, 0x20000000);
-  MmioWrite32(0xfd5dc008, 0x20000000);
-  MmioWrite32(0xfd7f0a10, 0x07000700);
-  MmioWrite32(0xfd7f0a10, 0x07000000);
+  MmioWrite32 (0xfd5d0008, 0x20000000);
+  MmioWrite32 (0xfd5d4008, 0x20000000);
+  MmioWrite32 (0xfd5d8008, 0x20000000);
+  MmioWrite32 (0xfd5dc008, 0x20000000);
+  MmioWrite32 (0xfd7f0a10, 0x07000700);
+  MmioWrite32 (0xfd7f0a10, 0x07000000);
 }
 
 VOID
 EFIAPI
 PcieIoInit (
-  UINT32 Segment
+  UINT32  Segment
   )
 {
   /* Set reset to gpio output mode */
-  if(Segment == PCIE_SEGMENT_PCIE20L2) { // AP6275P Wi-Fi
+  if (Segment == PCIE_SEGMENT_PCIE20L2) {
+    // AP6275P Wi-Fi
     GpioPinSetDirection (3, GPIO_PIN_PD1, GPIO_PIN_OUTPUT);
 
     /* wifi_poweren_gpio */
@@ -223,11 +226,11 @@ PcieIoInit (
 VOID
 EFIAPI
 PciePowerEn (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  if(Segment == PCIE_SEGMENT_PCIE20L2) {
+  if (Segment == PCIE_SEGMENT_PCIE20L2) {
     /* wifi_poweren_gpio */
     GpioPinWrite (0, GPIO_PIN_PC7, Enable);
   }
@@ -236,31 +239,37 @@ PciePowerEn (
 VOID
 EFIAPI
 PciePeReset (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  if(Segment == PCIE_SEGMENT_PCIE20L2) {
+  if (Segment == PCIE_SEGMENT_PCIE20L2) {
     GpioPinWrite (3, GPIO_PIN_PD1, !Enable);
   }
 }
 
+VOID
+EFIAPI
+HdmiTxIomux (
+  IN UINT32  Id
+  )
+{
+}
+
 VOID
 EFIAPI
 PwmFanIoSetup (
   VOID
   )
 {
-
 }
 
 VOID
 EFIAPI
 PwmFanSetSpeed (
-  IN UINT32 Percentage
+  IN UINT32  Percentage
   )
 {
-
 }
 
 VOID
@@ -276,7 +285,7 @@ PlatformInitLeds (
 VOID
 EFIAPI
 PlatformSetStatusLed (
-  IN BOOLEAN Enable
+  IN BOOLEAN  Enable
   )
 {
   GpioPinWrite (3, GPIO_PIN_PC2, Enable);
@@ -292,10 +301,11 @@ AttachCsotDsiPanel (
 CONST EFI_GUID *
 EFIAPI
 PlatformGetDtbFileGuid (
-  IN UINT32 CompatMode
+  IN UINT32  CompatMode
   )
 {
-  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+  STATIC CONST EFI_GUID  VendorDtbFileGuid = {
+    // DeviceTree/Vendor.inf
     0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
   };
 
@@ -317,11 +327,11 @@ PlatformEarlyInit (
   GpioPinWrite (4, GPIO_PIN_PA2, TRUE);
   GpioPinSetDirection (4, GPIO_PIN_PA2, GPIO_PIN_OUTPUT);
 
-  GpioPinSetFunction(1, GPIO_PIN_PC0, 0); //jdet
+  GpioPinSetFunction (1, GPIO_PIN_PC0, 0); // jdet
 
   /* spk-con-gpio */
   GpioPinWrite (4, GPIO_PIN_PA5, TRUE);
   GpioPinSetDirection (4, GPIO_PIN_PA5, GPIO_PIN_OUTPUT);
 
-  AttachCsotDsiPanel();
+  AttachCsotDsiPanel ();
 }

edk2-rockchip/Platform/Hinlink/Drivers/LogoDxe/Logo.c

@@ -19,15 +19,15 @@
 #include <Library/DebugLib.h>
 
 typedef struct {
-  EFI_IMAGE_ID                          ImageId;
-  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
-  INTN                                  OffsetX;
-  INTN                                  OffsetY;
+  EFI_IMAGE_ID                             ImageId;
+  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE    Attribute;
+  INTN                                     OffsetX;
+  INTN                                     OffsetY;
 } LOGO_ENTRY;
 
-STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
-STATIC EFI_HII_HANDLE            mHiiHandle;
-STATIC LOGO_ENTRY                mLogos[] = {
+STATIC EFI_HII_IMAGE_EX_PROTOCOL  *mHiiImageEx;
+STATIC EFI_HII_HANDLE             mHiiHandle;
+STATIC LOGO_ENTRY                 mLogos[] = {
   {
     IMAGE_TOKEN (IMG_LOGO),
     EdkiiPlatformLogoDisplayAttributeCenter,
@@ -53,18 +53,19 @@ STATIC
 EFI_STATUS
 EFIAPI
 GetImage (
-  IN     EDKII_PLATFORM_LOGO_PROTOCOL          *This,
-  IN OUT UINT32                                *Instance,
-     OUT EFI_IMAGE_INPUT                       *Image,
-     OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
-     OUT INTN                                  *OffsetX,
-     OUT INTN                                  *OffsetY
+  IN     EDKII_PLATFORM_LOGO_PROTOCOL        *This,
+  IN OUT UINT32                              *Instance,
+  OUT EFI_IMAGE_INPUT                        *Image,
+  OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE  *Attribute,
+  OUT INTN                                   *OffsetX,
+  OUT INTN                                   *OffsetY
   )
 {
-  UINT32 Current;
+  UINT32  Current;
 
-  if (Instance == NULL || Image == NULL ||
-      Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
+  if ((Instance == NULL) || (Image == NULL) ||
+      (Attribute == NULL) || (OffsetX == NULL) || (OffsetY == NULL))
+  {
     return EFI_INVALID_PARAMETER;
   }
 
@@ -78,11 +79,15 @@ GetImage (
   *OffsetX   = mLogos[Current].OffsetX;
   *OffsetY   = mLogos[Current].OffsetY;
 
-  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
-                        mLogos[Current].ImageId, Image);
+  return mHiiImageEx->GetImageEx (
+                        mHiiImageEx,
+                        mHiiHandle,
+                        mLogos[Current].ImageId,
+                        Image
+                        );
 }
 
-STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+STATIC EDKII_PLATFORM_LOGO_PROTOCOL  mPlatformLogo = {
   GetImage
 };
 
@@ -101,44 +106,66 @@ STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
 EFI_STATUS
 EFIAPI
 InitializeLogo (
-  IN EFI_HANDLE               ImageHandle,
-  IN EFI_SYSTEM_TABLE         *SystemTable
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
-  EFI_STATUS                  Status;
-  EFI_HII_PACKAGE_LIST_HEADER *PackageList;
-  EFI_HII_DATABASE_PROTOCOL   *HiiDatabase;
-  EFI_HANDLE                  Handle;
+  EFI_STATUS                   Status;
+  EFI_HII_PACKAGE_LIST_HEADER  *PackageList;
+  EFI_HII_DATABASE_PROTOCOL    *HiiDatabase;
+  EFI_HANDLE                   Handle;
 
-  Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
-                  (VOID **) &HiiDatabase);
+  Status = gBS->LocateProtocol (
+                  &gEfiHiiDatabaseProtocolGuid,
+                  NULL,
+                  (VOID **)&HiiDatabase
+                  );
   ASSERT_EFI_ERROR (Status);
 
-  Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
-                  (VOID **) &mHiiImageEx);
+  Status = gBS->LocateProtocol (
+                  &gEfiHiiImageExProtocolGuid,
+                  NULL,
+                  (VOID **)&mHiiImageEx
+                  );
   ASSERT_EFI_ERROR (Status);
 
   //
   // Retrieve HII package list from ImageHandle
   //
-  Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
-                  (VOID **) &PackageList, ImageHandle, NULL,
-                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+  Status = gBS->OpenProtocol (
+                  ImageHandle,
+                  &gEfiHiiPackageListProtocolGuid,
+                  (VOID **)&PackageList,
+                  ImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
   if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR,
-      "HII Image Package with logo not found in PE/COFF resource section\n"));
+    DEBUG ((
+      DEBUG_ERROR,
+      "HII Image Package with logo not found in PE/COFF resource section\n"
+      ));
     return Status;
   }
 
   //
   // Publish HII package list to HII Database.
   //
-  Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
-                          &mHiiHandle);
+  Status = HiiDatabase->NewPackageList (
+                          HiiDatabase,
+                          PackageList,
+                          NULL,
+                          &mHiiHandle
+                          );
   if (!EFI_ERROR (Status)) {
     Handle = NULL;
-    Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
-                    &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
+    Status = gBS->InstallMultipleProtocolInterfaces (
+                    &Handle,
+                    &gEdkiiPlatformLogoProtocolGuid,
+                    &mPlatformLogo,
+                    NULL
+                    );
   }
+
   return Status;
 }

edk2-rockchip/Platform/Hinlink/H88K/H88K.dsc

@@ -73,13 +73,6 @@
   gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
   gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x2
 
-  #
-  # CPU Performance default values
-  #
-  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-
   #
   # PCIe/SATA/USB Combo PIPE PHY support flags and default values
   #
@@ -109,6 +102,15 @@
   #
   gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE
 
+  #
+  # Display support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
+    VOP_OUTPUT_IF_HDMI0,
+    VOP_OUTPUT_IF_HDMI1,
+    VOP_OUTPUT_IF_DP0
+  })}
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.

edk2-rockchip/Platform/Hinlink/H88K/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -17,29 +17,29 @@
 #include <VarStoreData.h>
 #include <Library/TimerLib.h>
 
-static struct regulator_init_data rk806_init_data[] = {
+static struct regulator_init_data  rk806_init_data[] = {
   /* Master PMIC */
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
-  //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK4,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK5,  850000),
+  // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK7,  2000000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK8,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK10, 1800000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO2,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO4,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO5,  750000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO1,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO2,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO3,  1200000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO4,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO5,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO6,  1800000),
 
   /* No dual PMICs on this platform */
 };
@@ -51,9 +51,9 @@ SdmmcIoMux (
   )
 {
   /* sdmmc0 iomux (microSD socket) */
-  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
-  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
-  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+  BUS_IOC->GPIO4D_IOMUX_SEL_L  = (0xFFFFUL << 16) | (0x1111); // SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H  = (0x00FFUL << 16) | (0x0011); // SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); // SDMMC_DET
 }
 
 VOID
@@ -63,14 +63,14 @@ SdhciEmmcIoMux (
   )
 {
   /* sdhci0 iomux (eMMC socket) */
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); // EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
 }
 
-#define NS_CRU_BASE         0xFD7C0000
-#define CRU_CLKSEL_CON59    0x03EC
-#define CRU_CLKSEL_CON78    0x0438
+#define NS_CRU_BASE       0xFD7C0000
+#define CRU_CLKSEL_CON59  0x03EC
+#define CRU_CLKSEL_CON78  0x0438
 
 VOID
 EFIAPI
@@ -79,11 +79,11 @@ Rk806SpiIomux (
   )
 {
   /* io mux */
-  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
-  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  // BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  // BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
   PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
   PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+  MmioWrite32 (NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
 }
 
 VOID
@@ -92,24 +92,27 @@ Rk806Configure (
   VOID
   )
 {
-  UINTN RegCfgIndex;
+  UINTN  RegCfgIndex;
 
-  RK806Init();
+  RK806Init ();
 
-  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
-    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
+    RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
+  }
 }
 
 VOID
 EFIAPI
 SetCPULittleVoltage (
-  IN UINT32 Microvolts
+  IN UINT32  Microvolts
   )
 {
-  struct regulator_init_data Rk806CpuLittleSupply =
-        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+  struct regulator_init_data  Rk806CpuLittleSupply =
+    RK8XX_VOLTAGE_INIT (MASTER_BUCK2, Microvolts);
 
-  RK806RegulatorInit(Rk806CpuLittleSupply);
+  RK806RegulatorInit (Rk806CpuLittleSupply);
 }
 
 VOID
@@ -119,31 +122,33 @@ NorFspiIomux (
   )
 {
   /* io mux */
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
-             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
-#define FSPI_M1
-#if defined(FSPI_M0)
-   /*FSPI M0*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
-#elif defined(FSPI_M1)
+  MmioWrite32 (
+    NS_CRU_BASE + CRU_CLKSEL_CON78,
+    (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)
+    );
+  #define FSPI_M1
+ #if defined (FSPI_M0)
+  /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0);   // FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222);     // FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); // FSPI_CS0N_M0
+ #elif defined (FSPI_M1)
   /*FSPI M1*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
-#else
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); // FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); // FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3);         // FSPI_CS0N_M1
+ #else
   /*FSPI M2*/
-  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
-  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
-  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
-#endif
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); // [FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50);     // FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2);         // FSPI_CS0_M2
+ #endif
 }
 
 VOID
 EFIAPI
 GmacIomux (
-  IN UINT32 Id
+  IN UINT32  Id
   )
 {
   switch (Id) {
@@ -184,55 +189,55 @@ GmacIoPhyReset (
 VOID
 EFIAPI
 NorFspiEnableClock (
-  UINT32 *CruBase
+  UINT32  *CruBase
   )
 {
-  UINTN BaseAddr = (UINTN) CruBase;
+  UINTN  BaseAddr = (UINTN)CruBase;
 
-  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+  MmioWrite32 (BaseAddr + 0x087C, 0x0E000000);
 }
 
 VOID
 EFIAPI
 I2cIomux (
-   UINT32 id
+  UINT32  id
   )
 {
   switch (id) {
-  case 0:
-    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
-    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
-    break;
-  case 1:
-    GpioPinSetFunction(0, GPIO_PIN_PB5, 9); //i2c1_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PB6, 9); //i2c1_sda_m0
-    break;
-  case 2:
-    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
-    break;
-  case 3:
-    GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0
-    GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0
-    break;
-  case 4:
-    GpioPinSetFunction(3, GPIO_PIN_PA6, 9); //i2c4_scl_m0
-    GpioPinSetFunction(3, GPIO_PIN_PA5, 9); //i2c4_sda_m0
-    break;
-  case 5:
-    GpioPinSetFunction(3, GPIO_PIN_PC7, 9); //i2c5_scl_m0
-    GpioPinSetFunction(3, GPIO_PIN_PD0, 9); //i2c5_sda_m0
-    break;
-  case 6:
-    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
-    break;
-  case 7:
-    GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0
-    GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0
-    break;
-  default:
-    break;
+    case 0:
+      GpioPinSetFunction (0, GPIO_PIN_PD1, 3); // i2c0_scl_m2
+      GpioPinSetFunction (0, GPIO_PIN_PD2, 3); // i2c0_sda_m2
+      break;
+    case 1:
+      GpioPinSetFunction (0, GPIO_PIN_PB5, 9); // i2c1_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PB6, 9); // i2c1_sda_m0
+      break;
+    case 2:
+      GpioPinSetFunction (0, GPIO_PIN_PB7, 9); // i2c2_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC0, 9); // i2c2_sda_m0
+      break;
+    case 3:
+      GpioPinSetFunction (1, GPIO_PIN_PC1, 9); // i2c3_scl_m0
+      GpioPinSetFunction (1, GPIO_PIN_PC0, 9); // i2c3_sda_m0
+      break;
+    case 4:
+      GpioPinSetFunction (3, GPIO_PIN_PA6, 9); // i2c4_scl_m0
+      GpioPinSetFunction (3, GPIO_PIN_PA5, 9); // i2c4_sda_m0
+      break;
+    case 5:
+      GpioPinSetFunction (3, GPIO_PIN_PC7, 9); // i2c5_scl_m0
+      GpioPinSetFunction (3, GPIO_PIN_PD0, 9); // i2c5_sda_m0
+      break;
+    case 6:
+      GpioPinSetFunction (0, GPIO_PIN_PD0, 9); // i2c6_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC7, 9); // i2c6_sda_m0
+      break;
+    case 7:
+      GpioPinSetFunction (1, GPIO_PIN_PD0, 9); // i2c7_scl_m0
+      GpioPinSetFunction (1, GPIO_PIN_PD1, 9); // i2c7_sda_m0
+      break;
+    default:
+      break;
   }
 }
 
@@ -242,7 +247,7 @@ UsbPortPowerEnable (
   VOID
   )
 {
-  DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n"));
+  DEBUG ((DEBUG_INFO, "UsbPortPowerEnable called\n"));
   /* Set GPIO4 PB0 (USB_HOST_PWREN) output high to power USB ports */
   GpioPinSetDirection (4, GPIO_PIN_PB0, GPIO_PIN_OUTPUT);
   GpioPinWrite (4, GPIO_PIN_PB0, TRUE);
@@ -259,22 +264,22 @@ Usb2PhyResume (
   VOID
   )
 {
-  MmioWrite32(0xfd5d0008, 0x20000000);
-  MmioWrite32(0xfd5d4008, 0x20000000);
-  MmioWrite32(0xfd5d8008, 0x20000000);
-  MmioWrite32(0xfd5dc008, 0x20000000);
-  MmioWrite32(0xfd7f0a10, 0x07000700);
-  MmioWrite32(0xfd7f0a10, 0x07000000);
+  MmioWrite32 (0xfd5d0008, 0x20000000);
+  MmioWrite32 (0xfd5d4008, 0x20000000);
+  MmioWrite32 (0xfd5d8008, 0x20000000);
+  MmioWrite32 (0xfd5dc008, 0x20000000);
+  MmioWrite32 (0xfd7f0a10, 0x07000700);
+  MmioWrite32 (0xfd7f0a10, 0x07000000);
 }
 
 VOID
 EFIAPI
 PcieIoInit (
-  UINT32 Segment
+  UINT32  Segment
   )
 {
   /* Set reset and power IO to gpio output mode */
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4:
       GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
       GpioPinSetDirection (3, GPIO_PIN_PD5, GPIO_PIN_OUTPUT);
@@ -296,13 +301,13 @@ PcieIoInit (
 VOID
 EFIAPI
 PciePowerEn (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
   /* output high to enable power */
 
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4:
       GpioPinWrite (3, GPIO_PIN_PD5, Enable);
       break;
@@ -320,11 +325,11 @@ PciePowerEn (
 VOID
 EFIAPI
 PciePeReset (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4:
       GpioPinWrite (4, GPIO_PIN_PB6, !Enable);
       break;
@@ -342,6 +347,36 @@ PciePeReset (
   }
 }
 
+VOID
+EFIAPI
+HdmiTxIomux (
+  IN UINT32  Id
+  )
+{
+  switch (Id) {
+    case 0:
+      GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
+      GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
+      GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
+      GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
+      break;
+    case 1:
+      GpioPinSetFunction (3, GPIO_PIN_PC4, 5); // hdmim2_tx1_cec
+      GpioPinSetPull (3, GPIO_PIN_PC4, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA6, 5); // hdmim0_tx1_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA6, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (3, GPIO_PIN_PC6, 5); // hdmim1_tx1_scl
+      GpioPinSetPull (3, GPIO_PIN_PC6, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (3, GPIO_PIN_PC5, 5); // hdmim1_tx1_sda
+      GpioPinSetPull (3, GPIO_PIN_PC5, GPIO_PIN_PULL_NONE);
+      break;
+  }
+}
+
 VOID
 EFIAPI
 PwmFanIoSetup (
@@ -353,7 +388,7 @@ PwmFanIoSetup (
 VOID
 EFIAPI
 PwmFanSetSpeed (
-  IN UINT32 Percentage
+  IN UINT32  Percentage
   )
 {
 }
@@ -372,7 +407,7 @@ PlatformInitLeds (
 VOID
 EFIAPI
 PlatformSetStatusLed (
-  IN BOOLEAN Enable
+  IN BOOLEAN  Enable
   )
 {
   GpioPinWrite (3, GPIO_PIN_PB7, Enable);
@@ -381,10 +416,11 @@ PlatformSetStatusLed (
 CONST EFI_GUID *
 EFIAPI
 PlatformGetDtbFileGuid (
-  IN UINT32 CompatMode
+  IN UINT32  CompatMode
   )
 {
-  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+  STATIC CONST EFI_GUID  VendorDtbFileGuid = {
+    // DeviceTree/Vendor.inf
     0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
   };
 
@@ -403,5 +439,5 @@ PlatformEarlyInit (
   )
 {
   // Configure various things specific to this platform
-  GpioPinSetFunction(1, GPIO_PIN_PD5, 0); //jdet
+  GpioPinSetFunction (1, GPIO_PIN_PD5, 0); // jdet
 }

edk2-rockchip/Platform/Khadas/Drivers/KhadasMcuDxe/KhadasMcuDxe.c

@@ -25,7 +25,7 @@
 
 #include "KhadasMcuDxe.h"
 
-STATIC CONST EFI_GUID I2cGuid = I2C_GUID;
+STATIC CONST EFI_GUID  I2cGuid = I2C_GUID;
 
 STATIC
 EFI_STATUS
@@ -46,21 +46,21 @@ KhadasMcuRead (
   ASSERT (KhadasMcuContext != NULL);
   ASSERT (KhadasMcuContext->I2cIo != NULL);
 
-  RequestPacketSize = sizeof(UINTN) + sizeof (EFI_I2C_OPERATION) * 2;
-  RequestPacket = AllocateZeroPool (RequestPacketSize);
+  RequestPacketSize = sizeof (UINTN) + sizeof (EFI_I2C_OPERATION) * 2;
+  RequestPacket     = AllocateZeroPool (RequestPacketSize);
   if (RequestPacket == NULL) {
     return EFI_OUT_OF_RESOURCES;
   }
 
   RequestPacket->OperationCount = 2;
 
-  RequestPacket->Operation[0].Flags = 0;
+  RequestPacket->Operation[0].Flags         = 0;
   RequestPacket->Operation[0].LengthInBytes = RegAddressLength;
-  RequestPacket->Operation[0].Buffer = RegAddress;
+  RequestPacket->Operation[0].Buffer        = RegAddress;
 
-  RequestPacket->Operation[1].Flags = I2C_FLAG_READ;
+  RequestPacket->Operation[1].Flags         = I2C_FLAG_READ;
   RequestPacket->Operation[1].LengthInBytes = Length;
-  RequestPacket->Operation[1].Buffer = Buffer;
+  RequestPacket->Operation[1].Buffer        = Buffer;
 
   Status = KhadasMcuContext->I2cIo->QueueRequest (KhadasMcuContext->I2cIo, 0, NULL, RequestPacket, NULL);
   if (EFI_ERROR (Status)) {
@@ -93,8 +93,8 @@ KhadasMcuWrite (
   ASSERT (KhadasMcuContext != NULL);
   ASSERT (KhadasMcuContext->I2cIo != NULL);
 
-  RequestPacketSize = sizeof(UINTN) + sizeof (EFI_I2C_OPERATION);
-  RequestPacket = AllocateZeroPool (RequestPacketSize);
+  RequestPacketSize = sizeof (UINTN) + sizeof (EFI_I2C_OPERATION);
+  RequestPacket     = AllocateZeroPool (RequestPacketSize);
   if (RequestPacket == NULL) {
     return EFI_OUT_OF_RESOURCES;
   }
@@ -114,9 +114,9 @@ KhadasMcuWrite (
 
   RequestPacket->OperationCount = 1;
 
-  RequestPacket->Operation[0].Flags = 0;
+  RequestPacket->Operation[0].Flags         = 0;
   RequestPacket->Operation[0].LengthInBytes = RegAddressLength + Length;
-  RequestPacket->Operation[0].Buffer = Data;
+  RequestPacket->Operation[0].Buffer        = Data;
 
   Status = KhadasMcuContext->I2cIo->QueueRequest (KhadasMcuContext->I2cIo, 0, NULL, RequestPacket, NULL);
   if (EFI_ERROR (Status)) {
@@ -133,9 +133,9 @@ STATIC
 EFI_STATUS
 EFIAPI
 KhadasMcuReadRegister (
-  IN  CONST KHADAS_MCU_PROTOCOL   *This,
-  IN  UINT8                       Address,
-  OUT UINT8                       *Value
+  IN  CONST KHADAS_MCU_PROTOCOL  *This,
+  IN  UINT8                      Address,
+  OUT UINT8                      *Value
   )
 {
   return KhadasMcuRead (This, &Address, sizeof (UINT8), Value, sizeof (UINT8));
@@ -157,15 +157,18 @@ STATIC
 EFI_STATUS
 EFIAPI
 KhadasMcuSetFanSpeedPercentage (
-  IN KHADAS_MCU_PROTOCOL      *This,
-  IN UINT8                    Percentage
+  IN KHADAS_MCU_PROTOCOL  *This,
+  IN UINT8                Percentage
   )
 {
-  return KhadasMcuWriteRegister (This, MCU_CMD_FAN_STATUS_CTRL_REGv2,
-                                 MIN (Percentage, 100));
+  return KhadasMcuWriteRegister (
+           This,
+           MCU_CMD_FAN_STATUS_CTRL_REGv2,
+           MIN (Percentage, 100)
+           );
 }
 
-EFI_DRIVER_BINDING_PROTOCOL mDriverBindingProtocol = {
+EFI_DRIVER_BINDING_PROTOCOL  mDriverBindingProtocol = {
   KhadasMcuSupported,
   KhadasMcuStart,
   KhadasMcuStop
@@ -179,15 +182,15 @@ KhadasMcuSupported (
   IN EFI_DEVICE_PATH_PROTOCOL     *RemainingDevicePath OPTIONAL
   )
 {
-  EFI_STATUS            Status;
-  EFI_I2C_IO_PROTOCOL   *TmpI2cIo;
-  UINT8                 KhadasMcuAddress;
-  UINT8                 KhadasMcuBus;
+  EFI_STATUS           Status;
+  EFI_I2C_IO_PROTOCOL  *TmpI2cIo;
+  UINT8                KhadasMcuAddress;
+  UINT8                KhadasMcuBus;
 
   Status = gBS->OpenProtocol (
                   ControllerHandle,
                   &gEfiI2cIoProtocolGuid,
-                  (VOID **) &TmpI2cIo,
+                  (VOID **)&TmpI2cIo,
                   gImageHandle,
                   ControllerHandle,
                   EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -197,22 +200,23 @@ KhadasMcuSupported (
   }
 
   KhadasMcuAddress = PcdGet8 (PcdKhadasMcuAddress);
-  KhadasMcuBus = PcdGet8 (PcdKhadasMcuBus);
+  KhadasMcuBus     = PcdGet8 (PcdKhadasMcuBus);
 
   Status = EFI_UNSUPPORTED;
 
-  if (CompareGuid(TmpI2cIo->DeviceGuid, &I2cGuid) &&
-      TmpI2cIo->DeviceIndex == I2C_DEVICE_INDEX(KhadasMcuBus, KhadasMcuAddress)) {
+  if (CompareGuid (TmpI2cIo->DeviceGuid, &I2cGuid) &&
+      (TmpI2cIo->DeviceIndex == I2C_DEVICE_INDEX (KhadasMcuBus, KhadasMcuAddress)))
+  {
     DEBUG ((DEBUG_INFO, "%a: attached to Khadas MCU device\n", __func__));
     Status = EFI_SUCCESS;
   }
 
   gBS->CloseProtocol (
-        ControllerHandle,
-        &gEfiI2cIoProtocolGuid,
-        gImageHandle,
-        ControllerHandle
-        );
+         ControllerHandle,
+         &gEfiI2cIoProtocolGuid,
+         gImageHandle,
+         ControllerHandle
+         );
 
   return Status;
 }
@@ -225,26 +229,26 @@ KhadasMcuStart (
   IN EFI_DEVICE_PATH_PROTOCOL     *RemainingDevicePath OPTIONAL
   )
 {
-  EFI_STATUS            Status;
-  KHADAS_MCU_CONTEXT    *KhadasMcuContext;
-  KHADAS_MCU_PROTOCOL   *KhadasMcuProtocol;
+  EFI_STATUS           Status;
+  KHADAS_MCU_CONTEXT   *KhadasMcuContext;
+  KHADAS_MCU_PROTOCOL  *KhadasMcuProtocol;
 
-  KhadasMcuContext = AllocateZeroPool (sizeof(KHADAS_MCU_CONTEXT));
+  KhadasMcuContext = AllocateZeroPool (sizeof (KHADAS_MCU_CONTEXT));
   if (KhadasMcuContext == NULL) {
     DEBUG ((DEBUG_ERROR, "%a: context allocation failed\n", __func__));
     return EFI_OUT_OF_RESOURCES;
   }
 
   KhadasMcuContext->ControllerHandle = ControllerHandle;
-  KhadasMcuContext->Signature = KHADAS_MCU_SIGNATURE;
+  KhadasMcuContext->Signature        = KHADAS_MCU_SIGNATURE;
 
-  KhadasMcuProtocol = &KhadasMcuContext->KhadasMcuProtocol;
+  KhadasMcuProtocol                        = &KhadasMcuContext->KhadasMcuProtocol;
   KhadasMcuProtocol->SetFanSpeedPercentage = KhadasMcuSetFanSpeedPercentage;
 
   Status = gBS->OpenProtocol (
                   ControllerHandle,
                   &gEfiI2cIoProtocolGuid,
-                  (VOID **) &KhadasMcuContext->I2cIo,
+                  (VOID **)&KhadasMcuContext->I2cIo,
                   gImageHandle,
                   ControllerHandle,
                   EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -257,7 +261,8 @@ KhadasMcuStart (
 
   Status = gBS->InstallMultipleProtocolInterfaces (
                   &ControllerHandle,
-                  &gKhadasMcuProtocolGuid, KhadasMcuProtocol,
+                  &gKhadasMcuProtocolGuid,
+                  KhadasMcuProtocol,
                   NULL
                   );
   if (EFI_ERROR (Status)) {
@@ -270,11 +275,11 @@ KhadasMcuStart (
 fail:
   FreePool (KhadasMcuContext);
   gBS->CloseProtocol (
-        ControllerHandle,
-        &gEfiI2cIoProtocolGuid,
-        gImageHandle,
-        ControllerHandle
-        );
+         ControllerHandle,
+         &gEfiI2cIoProtocolGuid,
+         gImageHandle,
+         ControllerHandle
+         );
 
   return Status;
 }
@@ -288,14 +293,14 @@ KhadasMcuStop (
   IN EFI_HANDLE                   *ChildHandleBuffer OPTIONAL
   )
 {
-  EFI_STATUS            Status;
-  KHADAS_MCU_PROTOCOL   *KhadasMcuProtocol;
-  KHADAS_MCU_CONTEXT    *KhadasMcuContext;
+  EFI_STATUS           Status;
+  KHADAS_MCU_PROTOCOL  *KhadasMcuProtocol;
+  KHADAS_MCU_CONTEXT   *KhadasMcuContext;
 
   Status = gBS->OpenProtocol (
                   ControllerHandle,
                   &gKhadasMcuProtocolGuid,
-                  (VOID **) &KhadasMcuProtocol,
+                  (VOID **)&KhadasMcuProtocol,
                   This->DriverBindingHandle,
                   ControllerHandle,
                   EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -304,20 +309,22 @@ KhadasMcuStop (
     return EFI_DEVICE_ERROR;
   }
 
-  KhadasMcuContext = KHADAS_MCU_FROM_PROTOCOL(KhadasMcuProtocol);
+  KhadasMcuContext = KHADAS_MCU_FROM_PROTOCOL (KhadasMcuProtocol);
 
   gBS->UninstallMultipleProtocolInterfaces (
-        &ControllerHandle,
-        &gKhadasMcuProtocolGuid, &KhadasMcuContext->KhadasMcuProtocol,
-        &gEfiDriverBindingProtocolGuid, &mDriverBindingProtocol,
-        NULL
-        );
+         &ControllerHandle,
+         &gKhadasMcuProtocolGuid,
+         &KhadasMcuContext->KhadasMcuProtocol,
+         &gEfiDriverBindingProtocolGuid,
+         &mDriverBindingProtocol,
+         NULL
+         );
   gBS->CloseProtocol (
-        ControllerHandle,
-        &gEfiI2cIoProtocolGuid,
-        gImageHandle,
-        ControllerHandle
-        );
+         ControllerHandle,
+         &gEfiI2cIoProtocolGuid,
+         gImageHandle,
+         ControllerHandle
+         );
   FreePool (KhadasMcuContext);
 
   return EFI_SUCCESS;
@@ -326,15 +333,16 @@ KhadasMcuStop (
 EFI_STATUS
 EFIAPI
 KhadasMcuDxeInitialize (
-  IN EFI_HANDLE         ImageHandle,
-  IN EFI_SYSTEM_TABLE   *SystemTable
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
-  EFI_STATUS Status;
+  EFI_STATUS  Status;
 
   Status = gBS->InstallMultipleProtocolInterfaces (
                   &ImageHandle,
-                  &gEfiDriverBindingProtocolGuid, &mDriverBindingProtocol,
+                  &gEfiDriverBindingProtocolGuid,
+                  &mDriverBindingProtocol,
                   NULL
                   );
   return Status;

edk2-rockchip/Platform/Khadas/Drivers/KhadasMcuDxe/KhadasMcuDxe.h

@@ -13,7 +13,7 @@
 
 #include <Uefi.h>
 
-#define KHADAS_MCU_SIGNATURE          SIGNATURE_32 ('K', 'M', 'C', 'U')
+#define KHADAS_MCU_SIGNATURE  SIGNATURE_32 ('K', 'M', 'C', 'U')
 
 #define I2C_GUID \
   { \
@@ -21,20 +21,20 @@
   }
 
 typedef struct {
-  UINT32                      Signature;
-  EFI_HANDLE                  ControllerHandle;
-  EFI_I2C_IO_PROTOCOL         *I2cIo;
-  KHADAS_MCU_PROTOCOL         KhadasMcuProtocol;
+  UINT32                 Signature;
+  EFI_HANDLE             ControllerHandle;
+  EFI_I2C_IO_PROTOCOL    *I2cIo;
+  KHADAS_MCU_PROTOCOL    KhadasMcuProtocol;
 } KHADAS_MCU_CONTEXT;
 
-#define KHADAS_MCU_FROM_IO(a) CR (a, KHADAS_MCU_CONTEXT, I2cIo, KHADAS_MCU_SIGNATURE)
-#define KHADAS_MCU_FROM_PROTOCOL(a) CR (a, KHADAS_MCU_CONTEXT, KhadasMcuProtocol, KHADAS_MCU_SIGNATURE)
+#define KHADAS_MCU_FROM_IO(a)        CR (a, KHADAS_MCU_CONTEXT, I2cIo, KHADAS_MCU_SIGNATURE)
+#define KHADAS_MCU_FROM_PROTOCOL(a)  CR (a, KHADAS_MCU_CONTEXT, KhadasMcuProtocol, KHADAS_MCU_SIGNATURE)
 
 //
 // Registers & fields
 // https://docs.khadas.com/products/sbc/edge2/hardware/edge2-boot-flow
 //
-#define MCU_CMD_FAN_STATUS_CTRL_REGv2   0x8A
+#define MCU_CMD_FAN_STATUS_CTRL_REGv2  0x8A
 
 EFI_STATUS
 EFIAPI

edk2-rockchip/Platform/Khadas/Drivers/LogoDxe/Logo.c

@@ -19,15 +19,15 @@
 #include <Library/DebugLib.h>
 
 typedef struct {
-  EFI_IMAGE_ID                          ImageId;
-  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
-  INTN                                  OffsetX;
-  INTN                                  OffsetY;
+  EFI_IMAGE_ID                             ImageId;
+  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE    Attribute;
+  INTN                                     OffsetX;
+  INTN                                     OffsetY;
 } LOGO_ENTRY;
 
-STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
-STATIC EFI_HII_HANDLE            mHiiHandle;
-STATIC LOGO_ENTRY                mLogos[] = {
+STATIC EFI_HII_IMAGE_EX_PROTOCOL  *mHiiImageEx;
+STATIC EFI_HII_HANDLE             mHiiHandle;
+STATIC LOGO_ENTRY                 mLogos[] = {
   {
     IMAGE_TOKEN (IMG_LOGO),
     EdkiiPlatformLogoDisplayAttributeCenter,
@@ -53,18 +53,19 @@ STATIC
 EFI_STATUS
 EFIAPI
 GetImage (
-  IN     EDKII_PLATFORM_LOGO_PROTOCOL          *This,
-  IN OUT UINT32                                *Instance,
-     OUT EFI_IMAGE_INPUT                       *Image,
-     OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
-     OUT INTN                                  *OffsetX,
-     OUT INTN                                  *OffsetY
+  IN     EDKII_PLATFORM_LOGO_PROTOCOL        *This,
+  IN OUT UINT32                              *Instance,
+  OUT EFI_IMAGE_INPUT                        *Image,
+  OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE  *Attribute,
+  OUT INTN                                   *OffsetX,
+  OUT INTN                                   *OffsetY
   )
 {
-  UINT32 Current;
+  UINT32  Current;
 
-  if (Instance == NULL || Image == NULL ||
-      Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
+  if ((Instance == NULL) || (Image == NULL) ||
+      (Attribute == NULL) || (OffsetX == NULL) || (OffsetY == NULL))
+  {
     return EFI_INVALID_PARAMETER;
   }
 
@@ -78,11 +79,15 @@ GetImage (
   *OffsetX   = mLogos[Current].OffsetX;
   *OffsetY   = mLogos[Current].OffsetY;
 
-  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
-                        mLogos[Current].ImageId, Image);
+  return mHiiImageEx->GetImageEx (
+                        mHiiImageEx,
+                        mHiiHandle,
+                        mLogos[Current].ImageId,
+                        Image
+                        );
 }
 
-STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+STATIC EDKII_PLATFORM_LOGO_PROTOCOL  mPlatformLogo = {
   GetImage
 };
 
@@ -101,44 +106,66 @@ STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
 EFI_STATUS
 EFIAPI
 InitializeLogo (
-  IN EFI_HANDLE               ImageHandle,
-  IN EFI_SYSTEM_TABLE         *SystemTable
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
-  EFI_STATUS                  Status;
-  EFI_HII_PACKAGE_LIST_HEADER *PackageList;
-  EFI_HII_DATABASE_PROTOCOL   *HiiDatabase;
-  EFI_HANDLE                  Handle;
+  EFI_STATUS                   Status;
+  EFI_HII_PACKAGE_LIST_HEADER  *PackageList;
+  EFI_HII_DATABASE_PROTOCOL    *HiiDatabase;
+  EFI_HANDLE                   Handle;
 
-  Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
-                  (VOID **) &HiiDatabase);
+  Status = gBS->LocateProtocol (
+                  &gEfiHiiDatabaseProtocolGuid,
+                  NULL,
+                  (VOID **)&HiiDatabase
+                  );
   ASSERT_EFI_ERROR (Status);
 
-  Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
-                  (VOID **) &mHiiImageEx);
+  Status = gBS->LocateProtocol (
+                  &gEfiHiiImageExProtocolGuid,
+                  NULL,
+                  (VOID **)&mHiiImageEx
+                  );
   ASSERT_EFI_ERROR (Status);
 
   //
   // Retrieve HII package list from ImageHandle
   //
-  Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
-                  (VOID **) &PackageList, ImageHandle, NULL,
-                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+  Status = gBS->OpenProtocol (
+                  ImageHandle,
+                  &gEfiHiiPackageListProtocolGuid,
+                  (VOID **)&PackageList,
+                  ImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
   if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR,
-      "HII Image Package with logo not found in PE/COFF resource section\n"));
+    DEBUG ((
+      DEBUG_ERROR,
+      "HII Image Package with logo not found in PE/COFF resource section\n"
+      ));
     return Status;
   }
 
   //
   // Publish HII package list to HII Database.
   //
-  Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
-                          &mHiiHandle);
+  Status = HiiDatabase->NewPackageList (
+                          HiiDatabase,
+                          PackageList,
+                          NULL,
+                          &mHiiHandle
+                          );
   if (!EFI_ERROR (Status)) {
     Handle = NULL;
-    Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
-                    &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
+    Status = gBS->InstallMultipleProtocolInterfaces (
+                    &Handle,
+                    &gEdkiiPlatformLogoProtocolGuid,
+                    &mPlatformLogo,
+                    NULL
+                    );
   }
+
   return Status;
 }

edk2-rockchip/Platform/Khadas/Edge2/DeviceTree/Mainline.inf

@@ -14,7 +14,7 @@
   VERSION_STRING                 = 1.0
 
 [Sources]
-  devicetree/mainline/upstream/src/arm64/rockchip/rk3588s-khadas-edge2.dts
+  devicetree/mainline/rk3588s-khadas-edge2-fixup.dts
 
 [Packages]
   MdePkg/MdePkg.dec

edk2-rockchip/Platform/Khadas/Edge2/Edge2.dsc

@@ -27,6 +27,9 @@
   FLASH_DEFINITION               = Silicon/Rockchip/RK3588/RK3588.fdf
   RK_PLATFORM_FVMAIN_MODULES     = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc
 
+  # GMAC is not exposed
+  DEFINE RK3588_GMAC_ENABLE = FALSE
+
   #
   # HYM8563 RTC support
   # I2C location configured by PCDs below.
@@ -73,13 +76,6 @@
   gKhadasTokenSpaceGuid.PcdKhadasMcuAddress|0x18
   gKhadasTokenSpaceGuid.PcdKhadasMcuBus|0x2
 
-  #
-  # CPU Performance default values
-  #
-  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-
   #
   # PCIe/SATA/USB Combo PIPE PHY support flags and default values
   #
@@ -104,6 +100,14 @@
   #
   gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
 
+  #
+  # Display support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
+    VOP_OUTPUT_IF_HDMI0,
+    VOP_OUTPUT_IF_DP0
+  })}
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.

edk2-rockchip/Platform/Khadas/Edge2/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -21,33 +21,33 @@
 
 #include <Protocol/KhadasMcu.h>
 
-STATIC VOID                   *mKhadasMcuEventRegistration;
-STATIC KHADAS_MCU_PROTOCOL    *mKhadasMcu;
-STATIC UINT8                  mTargetFanSpeed;
+STATIC VOID                 *mKhadasMcuEventRegistration;
+STATIC KHADAS_MCU_PROTOCOL  *mKhadasMcu;
+STATIC UINT8                mTargetFanSpeed;
 
-static struct regulator_init_data rk806_init_data[] = {
+static struct regulator_init_data  rk806_init_data[] = {
   /* Master PMIC */
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
-  //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK4,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK5,  850000),
+  // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK7,  2000000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK8,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK10, 1800000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO2,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO4,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO5,  750000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO1,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO2,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO3,  1200000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO4,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO5,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO6,  1800000),
 
   /* No dual PMICs on this platform */
 };
@@ -59,9 +59,9 @@ SdmmcIoMux (
   )
 {
   /* sdmmc0 iomux (microSD socket) */
-  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
-  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
-  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+  BUS_IOC->GPIO4D_IOMUX_SEL_L  = (0xFFFFUL << 16) | (0x1111); // SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H  = (0x00FFUL << 16) | (0x0011); // SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); // SDMMC_DET
 }
 
 VOID
@@ -71,14 +71,14 @@ SdhciEmmcIoMux (
   )
 {
   /* sdmmc0 iomux */
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); // EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
 }
 
-#define NS_CRU_BASE         0xFD7C0000
-#define CRU_CLKSEL_CON59    0x03EC
-#define CRU_CLKSEL_CON78    0x0438
+#define NS_CRU_BASE       0xFD7C0000
+#define CRU_CLKSEL_CON59  0x03EC
+#define CRU_CLKSEL_CON78  0x0438
 
 VOID
 EFIAPI
@@ -87,11 +87,11 @@ Rk806SpiIomux (
   )
 {
   /* io mux */
-  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
-  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  // BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  // BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
   PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
   PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+  MmioWrite32 (NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
 }
 
 VOID
@@ -100,24 +100,27 @@ Rk806Configure (
   VOID
   )
 {
-  UINTN RegCfgIndex;
+  UINTN  RegCfgIndex;
 
-  RK806Init();
+  RK806Init ();
 
-  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
-    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
+    RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
+  }
 }
 
 VOID
 EFIAPI
 SetCPULittleVoltage (
-  IN UINT32 Microvolts
+  IN UINT32  Microvolts
   )
 {
-  struct regulator_init_data Rk806CpuLittleSupply =
-        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+  struct regulator_init_data  Rk806CpuLittleSupply =
+    RK8XX_VOLTAGE_INIT (MASTER_BUCK2, Microvolts);
 
-  RK806RegulatorInit(Rk806CpuLittleSupply);
+  RK806RegulatorInit (Rk806CpuLittleSupply);
 }
 
 VOID
@@ -127,31 +130,33 @@ NorFspiIomux (
   )
 {
   /* io mux */
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
-             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
-#define FSPI_M1
-#if defined(FSPI_M0)
-   /*FSPI M0*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
-#elif defined(FSPI_M1)
+  MmioWrite32 (
+    NS_CRU_BASE + CRU_CLKSEL_CON78,
+    (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)
+    );
+  #define FSPI_M1
+ #if defined (FSPI_M0)
+  /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0);   // FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222);     // FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); // FSPI_CS0N_M0
+ #elif defined (FSPI_M1)
   /*FSPI M1*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
-#else
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); // FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); // FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3);         // FSPI_CS0N_M1
+ #else
   /*FSPI M2*/
-  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
-  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
-  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
-#endif
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); // [FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50);     // FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2);         // FSPI_CS0_M2
+ #endif
 }
 
 VOID
 EFIAPI
 GmacIomux (
-  IN UINT32 Id
+  IN UINT32  Id
   )
 {
   /* No GMAC here */
@@ -160,49 +165,49 @@ GmacIomux (
 VOID
 EFIAPI
 NorFspiEnableClock (
-  UINT32 *CruBase
+  UINT32  *CruBase
   )
 {
-  UINTN BaseAddr = (UINTN) CruBase;
+  UINTN  BaseAddr = (UINTN)CruBase;
 
-  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+  MmioWrite32 (BaseAddr + 0x087C, 0x0E000000);
 }
 
 VOID
 EFIAPI
 I2cIomux (
-   UINT32 id
+  UINT32  id
   )
 {
   switch (id) {
-  case 0:
-    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
-    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
-    break;
-  case 1:
-    break;
-  case 2:
-    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
-    break;
-  case 3:
-    GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0
-    GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0
-    break;
-  case 4:
-    GpioPinSetFunction(1, GPIO_PIN_PA3, 9); //i2c4_scl_m3
-    GpioPinSetFunction(1, GPIO_PIN_PA2, 9); //i2c4_sda_m3
-    break;
-  case 5:
-    break;
-  case 6:
-    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
-    break;
-  case 7:
-    break;
-  default:
-    break;
+    case 0:
+      GpioPinSetFunction (0, GPIO_PIN_PD1, 3); // i2c0_scl_m2
+      GpioPinSetFunction (0, GPIO_PIN_PD2, 3); // i2c0_sda_m2
+      break;
+    case 1:
+      break;
+    case 2:
+      GpioPinSetFunction (0, GPIO_PIN_PB7, 9); // i2c2_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC0, 9); // i2c2_sda_m0
+      break;
+    case 3:
+      GpioPinSetFunction (1, GPIO_PIN_PC1, 9); // i2c3_scl_m0
+      GpioPinSetFunction (1, GPIO_PIN_PC0, 9); // i2c3_sda_m0
+      break;
+    case 4:
+      GpioPinSetFunction (1, GPIO_PIN_PA3, 9); // i2c4_scl_m3
+      GpioPinSetFunction (1, GPIO_PIN_PA2, 9); // i2c4_sda_m3
+      break;
+    case 5:
+      break;
+    case 6:
+      GpioPinSetFunction (0, GPIO_PIN_PD0, 9); // i2c6_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC7, 9); // i2c6_sda_m0
+      break;
+    case 7:
+      break;
+    default:
+      break;
   }
 }
 
@@ -212,11 +217,7 @@ UsbPortPowerEnable (
   VOID
   )
 {
-  DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n"));
-
-  /* Set VCC_5V0_PWREN_H */
-  GpioPinWrite (4, GPIO_PIN_PA2, TRUE);
-  GpioPinSetDirection (4, GPIO_PIN_PA2, GPIO_PIN_OUTPUT);
+  DEBUG ((DEBUG_INFO, "UsbPortPowerEnable called\n"));
 
   /* Set USB_HOST_PWREN_H */
   GpioPinWrite (1, GPIO_PIN_PB1, TRUE);
@@ -233,22 +234,23 @@ Usb2PhyResume (
   VOID
   )
 {
-  MmioWrite32(0xfd5d0008, 0x20000000);
-  MmioWrite32(0xfd5d4008, 0x20000000);
-  MmioWrite32(0xfd5d8008, 0x20000000);
-  MmioWrite32(0xfd5dc008, 0x20000000);
-  MmioWrite32(0xfd7f0a10, 0x07000700);
-  MmioWrite32(0xfd7f0a10, 0x07000000);
+  MmioWrite32 (0xfd5d0008, 0x20000000);
+  MmioWrite32 (0xfd5d4008, 0x20000000);
+  MmioWrite32 (0xfd5d8008, 0x20000000);
+  MmioWrite32 (0xfd5dc008, 0x20000000);
+  MmioWrite32 (0xfd7f0a10, 0x07000700);
+  MmioWrite32 (0xfd7f0a10, 0x07000000);
 }
 
 VOID
 EFIAPI
 PcieIoInit (
-  UINT32 Segment
+  UINT32  Segment
   )
 {
   /* Set reset to gpio output mode */
-  if(Segment == PCIE_SEGMENT_PCIE20L2) { // AP6275P Wi-Fi
+  if (Segment == PCIE_SEGMENT_PCIE20L2) {
+    // AP6275P Wi-Fi
     GpioPinSetDirection (3, GPIO_PIN_PD1, GPIO_PIN_OUTPUT);
 
     /* wifi_poweren_gpio */
@@ -259,11 +261,11 @@ PcieIoInit (
 VOID
 EFIAPI
 PciePowerEn (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  if(Segment == PCIE_SEGMENT_PCIE20L2) {
+  if (Segment == PCIE_SEGMENT_PCIE20L2) {
     /* wifi_poweren_gpio */
     GpioPinWrite (0, GPIO_PIN_PC4, Enable);
   }
@@ -272,43 +274,72 @@ PciePowerEn (
 VOID
 EFIAPI
 PciePeReset (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  if(Segment == PCIE_SEGMENT_PCIE20L2) {
+  if (Segment == PCIE_SEGMENT_PCIE20L2) {
     GpioPinWrite (3, GPIO_PIN_PD1, !Enable);
   }
 }
 
+VOID
+EFIAPI
+HdmiTxIomux (
+  IN UINT32  Id
+  )
+{
+  switch (Id) {
+    case 0:
+      GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
+      GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
+      GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
+      GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
+      break;
+  }
+}
+
 STATIC
 VOID
 KhadasMcuRegistrationEventHandler (
-  IN  EFI_EVENT       Event,
-  IN  VOID            *Context
+  IN  EFI_EVENT  Event,
+  IN  VOID       *Context
   )
 {
-  EFI_HANDLE     Handle;
-  UINTN          BufferSize;
-  EFI_STATUS     Status;
+  EFI_HANDLE  Handle;
+  UINTN       BufferSize;
+  EFI_STATUS  Status;
 
   BufferSize = sizeof (EFI_HANDLE);
-  Status = gBS->LocateHandle (
-                    ByRegisterNotify,
-                    NULL,
-                    mKhadasMcuEventRegistration,
-                    &BufferSize,
-                    &Handle);
+  Status     = gBS->LocateHandle (
+                      ByRegisterNotify,
+                      NULL,
+                      mKhadasMcuEventRegistration,
+                      &BufferSize,
+                      &Handle
+                      );
   if (EFI_ERROR (Status)) {
     if (Status != EFI_NOT_FOUND) {
-      DEBUG ((DEBUG_WARN, "%a: Failed to locate gKhadasMcuProtocol. Status=%r\n",
-              __func__, Status));
+      DEBUG ((
+        DEBUG_WARN,
+        "%a: Failed to locate gKhadasMcuProtocol. Status=%r\n",
+        __func__,
+        Status
+        ));
     }
+
     return;
   }
 
-  Status = gBS->HandleProtocol (Handle,
-              &gKhadasMcuProtocolGuid, (VOID **) &mKhadasMcu);
+  Status = gBS->HandleProtocol (
+                  Handle,
+                  &gKhadasMcuProtocolGuid,
+                  (VOID **)&mKhadasMcu
+                  );
   ASSERT_EFI_ERROR (Status);
 
   PwmFanSetSpeed (mTargetFanSpeed);
@@ -323,20 +354,21 @@ PwmFanIoSetup (
   )
 {
   EfiCreateProtocolNotifyEvent (
-          &gKhadasMcuProtocolGuid,
-          TPL_CALLBACK,
-          KhadasMcuRegistrationEventHandler,
-          NULL,
-          &mKhadasMcuEventRegistration);
+    &gKhadasMcuProtocolGuid,
+    TPL_CALLBACK,
+    KhadasMcuRegistrationEventHandler,
+    NULL,
+    &mKhadasMcuEventRegistration
+    );
 }
 
 VOID
 EFIAPI
 PwmFanSetSpeed (
-  UINT32 Percentage
+  UINT32  Percentage
   )
 {
-  mTargetFanSpeed = (UINT8) Percentage;
+  mTargetFanSpeed = (UINT8)Percentage;
 
   //
   // If the protocol is installed, set the speed now.
@@ -366,7 +398,7 @@ PlatformInitLeds (
 VOID
 EFIAPI
 PlatformSetStatusLed (
-  IN BOOLEAN Enable
+  IN BOOLEAN  Enable
   )
 {
   GpioPinWrite (4, GPIO_PIN_PB2, Enable);
@@ -375,13 +407,15 @@ PlatformSetStatusLed (
 CONST EFI_GUID *
 EFIAPI
 PlatformGetDtbFileGuid (
-  IN UINT32 CompatMode
+  IN UINT32  CompatMode
   )
 {
-  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+  STATIC CONST EFI_GUID  VendorDtbFileGuid = {
+    // DeviceTree/Vendor.inf
     0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
   };
-  STATIC CONST EFI_GUID MainlineDtbFileGuid = {       // DeviceTree/Mainline.inf
+  STATIC CONST EFI_GUID  MainlineDtbFileGuid = {
+    // DeviceTree/Mainline.inf
     0x84492e97, 0xa10f, 0x49a7, { 0x85, 0xe9, 0x02, 0x5d, 0x19, 0x66, 0xb3, 0x43 }
   };
 
@@ -402,6 +436,11 @@ PlatformEarlyInit (
   )
 {
   // Configure various things specific to this platform
-  GpioPinSetFunction(1, GPIO_PIN_PD3, 0); //jdet
-  GpioPinSetFunction(1, GPIO_PIN_PD0, 0); //spk_con
+
+  /* Set VCC_5V0_PWREN_H */
+  GpioPinWrite (4, GPIO_PIN_PA2, TRUE);
+  GpioPinSetDirection (4, GPIO_PIN_PA2, GPIO_PIN_OUTPUT);
+
+  GpioPinSetFunction (1, GPIO_PIN_PD3, 0); // jdet
+  GpioPinSetFunction (1, GPIO_PIN_PD0, 0); // spk_con
 }

edk2-rockchip/Platform/Khadas/Include/Protocol/KhadasMcu.h

@@ -16,15 +16,15 @@ typedef struct _KHADAS_MCU_PROTOCOL KHADAS_MCU_PROTOCOL;
 
 typedef
 EFI_STATUS
-(EFIAPI *KHADAS_MCU_SET_FAN_SPEED_PERCENTAGE) (
+(EFIAPI *KHADAS_MCU_SET_FAN_SPEED_PERCENTAGE)(
   IN KHADAS_MCU_PROTOCOL      *This,
   IN UINT8                    Percentage
   );
 
 struct _KHADAS_MCU_PROTOCOL {
-  KHADAS_MCU_SET_FAN_SPEED_PERCENTAGE   SetFanSpeedPercentage;
+  KHADAS_MCU_SET_FAN_SPEED_PERCENTAGE    SetFanSpeedPercentage;
 };
 
-extern EFI_GUID gKhadasMcuProtocolGuid;
+extern EFI_GUID  gKhadasMcuProtocolGuid;
 
 #endif // __KHADAS_MCU_H__

edk2-rockchip/Platform/Mekotronics/Drivers/LogoDxe/Logo.c

@@ -19,15 +19,15 @@
 #include <Library/DebugLib.h>
 
 typedef struct {
-  EFI_IMAGE_ID                          ImageId;
-  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
-  INTN                                  OffsetX;
-  INTN                                  OffsetY;
+  EFI_IMAGE_ID                             ImageId;
+  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE    Attribute;
+  INTN                                     OffsetX;
+  INTN                                     OffsetY;
 } LOGO_ENTRY;
 
-STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
-STATIC EFI_HII_HANDLE            mHiiHandle;
-STATIC LOGO_ENTRY                mLogos[] = {
+STATIC EFI_HII_IMAGE_EX_PROTOCOL  *mHiiImageEx;
+STATIC EFI_HII_HANDLE             mHiiHandle;
+STATIC LOGO_ENTRY                 mLogos[] = {
   {
     IMAGE_TOKEN (IMG_LOGO),
     EdkiiPlatformLogoDisplayAttributeCenter,
@@ -53,18 +53,19 @@ STATIC
 EFI_STATUS
 EFIAPI
 GetImage (
-  IN     EDKII_PLATFORM_LOGO_PROTOCOL          *This,
-  IN OUT UINT32                                *Instance,
-     OUT EFI_IMAGE_INPUT                       *Image,
-     OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
-     OUT INTN                                  *OffsetX,
-     OUT INTN                                  *OffsetY
+  IN     EDKII_PLATFORM_LOGO_PROTOCOL        *This,
+  IN OUT UINT32                              *Instance,
+  OUT EFI_IMAGE_INPUT                        *Image,
+  OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE  *Attribute,
+  OUT INTN                                   *OffsetX,
+  OUT INTN                                   *OffsetY
   )
 {
-  UINT32 Current;
+  UINT32  Current;
 
-  if (Instance == NULL || Image == NULL ||
-      Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
+  if ((Instance == NULL) || (Image == NULL) ||
+      (Attribute == NULL) || (OffsetX == NULL) || (OffsetY == NULL))
+  {
     return EFI_INVALID_PARAMETER;
   }
 
@@ -78,11 +79,15 @@ GetImage (
   *OffsetX   = mLogos[Current].OffsetX;
   *OffsetY   = mLogos[Current].OffsetY;
 
-  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
-                        mLogos[Current].ImageId, Image);
+  return mHiiImageEx->GetImageEx (
+                        mHiiImageEx,
+                        mHiiHandle,
+                        mLogos[Current].ImageId,
+                        Image
+                        );
 }
 
-STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+STATIC EDKII_PLATFORM_LOGO_PROTOCOL  mPlatformLogo = {
   GetImage
 };
 
@@ -101,44 +106,66 @@ STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
 EFI_STATUS
 EFIAPI
 InitializeLogo (
-  IN EFI_HANDLE               ImageHandle,
-  IN EFI_SYSTEM_TABLE         *SystemTable
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
-  EFI_STATUS                  Status;
-  EFI_HII_PACKAGE_LIST_HEADER *PackageList;
-  EFI_HII_DATABASE_PROTOCOL   *HiiDatabase;
-  EFI_HANDLE                  Handle;
+  EFI_STATUS                   Status;
+  EFI_HII_PACKAGE_LIST_HEADER  *PackageList;
+  EFI_HII_DATABASE_PROTOCOL    *HiiDatabase;
+  EFI_HANDLE                   Handle;
 
-  Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
-                  (VOID **) &HiiDatabase);
+  Status = gBS->LocateProtocol (
+                  &gEfiHiiDatabaseProtocolGuid,
+                  NULL,
+                  (VOID **)&HiiDatabase
+                  );
   ASSERT_EFI_ERROR (Status);
 
-  Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
-                  (VOID **) &mHiiImageEx);
+  Status = gBS->LocateProtocol (
+                  &gEfiHiiImageExProtocolGuid,
+                  NULL,
+                  (VOID **)&mHiiImageEx
+                  );
   ASSERT_EFI_ERROR (Status);
 
   //
   // Retrieve HII package list from ImageHandle
   //
-  Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
-                  (VOID **) &PackageList, ImageHandle, NULL,
-                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+  Status = gBS->OpenProtocol (
+                  ImageHandle,
+                  &gEfiHiiPackageListProtocolGuid,
+                  (VOID **)&PackageList,
+                  ImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
   if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR,
-      "HII Image Package with logo not found in PE/COFF resource section\n"));
+    DEBUG ((
+      DEBUG_ERROR,
+      "HII Image Package with logo not found in PE/COFF resource section\n"
+      ));
     return Status;
   }
 
   //
   // Publish HII package list to HII Database.
   //
-  Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
-                          &mHiiHandle);
+  Status = HiiDatabase->NewPackageList (
+                          HiiDatabase,
+                          PackageList,
+                          NULL,
+                          &mHiiHandle
+                          );
   if (!EFI_ERROR (Status)) {
     Handle = NULL;
-    Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
-                    &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
+    Status = gBS->InstallMultipleProtocolInterfaces (
+                    &Handle,
+                    &gEdkiiPlatformLogoProtocolGuid,
+                    &mPlatformLogo,
+                    NULL
+                    );
   }
+
   return Status;
 }

edk2-rockchip/Platform/Mekotronics/R58-Mini/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -16,29 +16,29 @@
 #include <Soc.h>
 #include <VarStoreData.h>
 
-static struct regulator_init_data rk806_init_data[] = {
+static struct regulator_init_data  rk806_init_data[] = {
   /* Master PMIC */
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
-  //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK4,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK5,  850000),
+  // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK7,  2000000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK8,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK10, 1800000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO2,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO4,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO5,  750000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO1,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO2,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO3,  1200000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO4,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO5,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO6,  1800000),
 
   /* No dual PMICs on this platform */
 };
@@ -50,9 +50,9 @@ SdmmcIoMux (
   )
 {
   /* sdmmc0 iomux (microSD socket) */
-  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
-  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
-  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+  BUS_IOC->GPIO4D_IOMUX_SEL_L  = (0xFFFFUL << 16) | (0x1111); // SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H  = (0x00FFUL << 16) | (0x0011); // SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); // SDMMC_DET
 }
 
 VOID
@@ -62,14 +62,14 @@ SdhciEmmcIoMux (
   )
 {
   /* sdhci0 iomux (eMMC socket) */
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); // EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
 }
 
-#define NS_CRU_BASE         0xFD7C0000
-#define CRU_CLKSEL_CON59    0x03EC
-#define CRU_CLKSEL_CON78    0x0438
+#define NS_CRU_BASE       0xFD7C0000
+#define CRU_CLKSEL_CON59  0x03EC
+#define CRU_CLKSEL_CON78  0x0438
 
 VOID
 EFIAPI
@@ -78,11 +78,11 @@ Rk806SpiIomux (
   )
 {
   /* io mux */
-  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
-  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  // BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  // BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
   PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
   PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+  MmioWrite32 (NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
 }
 
 VOID
@@ -91,24 +91,27 @@ Rk806Configure (
   VOID
   )
 {
-  UINTN RegCfgIndex;
+  UINTN  RegCfgIndex;
 
-  RK806Init();
+  RK806Init ();
 
-  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
-    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
+    RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
+  }
 }
 
 VOID
 EFIAPI
 SetCPULittleVoltage (
-  IN UINT32 Microvolts
+  IN UINT32  Microvolts
   )
 {
-  struct regulator_init_data Rk806CpuLittleSupply =
-        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+  struct regulator_init_data  Rk806CpuLittleSupply =
+    RK8XX_VOLTAGE_INIT (MASTER_BUCK2, Microvolts);
 
-  RK806RegulatorInit(Rk806CpuLittleSupply);
+  RK806RegulatorInit (Rk806CpuLittleSupply);
 }
 
 VOID
@@ -118,31 +121,33 @@ NorFspiIomux (
   )
 {
   /* io mux */
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
-             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
-#define FSPI_M1
-#if defined(FSPI_M0)
-   /*FSPI M0*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
-#elif defined(FSPI_M1)
+  MmioWrite32 (
+    NS_CRU_BASE + CRU_CLKSEL_CON78,
+    (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)
+    );
+  #define FSPI_M1
+ #if defined (FSPI_M0)
+  /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0);   // FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222);     // FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); // FSPI_CS0N_M0
+ #elif defined (FSPI_M1)
   /*FSPI M1*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
-#else
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); // FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); // FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3);         // FSPI_CS0N_M1
+ #else
   /*FSPI M2*/
-  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
-  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
-  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
-#endif
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); // [FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50);     // FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2);         // FSPI_CS0_M2
+ #endif
 }
 
 VOID
 EFIAPI
 GmacIomux (
-  IN UINT32 Id
+  IN UINT32  Id
   )
 {
   switch (Id) {
@@ -183,47 +188,47 @@ GmacIoPhyReset (
 VOID
 EFIAPI
 NorFspiEnableClock (
-  UINT32 *CruBase
+  UINT32  *CruBase
   )
 {
-  UINTN BaseAddr = (UINTN) CruBase;
+  UINTN  BaseAddr = (UINTN)CruBase;
 
-  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+  MmioWrite32 (BaseAddr + 0x087C, 0x0E000000);
 }
 
 VOID
 EFIAPI
 I2cIomux (
-   UINT32 id
+  UINT32  id
   )
 {
   switch (id) {
-  case 0:
-    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
-    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
-    break;
-  case 1:
-    break;
-  case 2:
-    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
-    break;
-  case 3:
-    break;
-  case 4:
-    break;
-  case 5:
-    GpioPinSetFunction(1, GPIO_PIN_PB6, 9); //i2c5_scl_m3
-    GpioPinSetFunction(1, GPIO_PIN_PB7, 9); //i2c5_sda_m3
-    break;
-  case 6:
-    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
-    break;
-  case 7:
-    break;
-  default:
-    break;
+    case 0:
+      GpioPinSetFunction (0, GPIO_PIN_PD1, 3); // i2c0_scl_m2
+      GpioPinSetFunction (0, GPIO_PIN_PD2, 3); // i2c0_sda_m2
+      break;
+    case 1:
+      break;
+    case 2:
+      GpioPinSetFunction (0, GPIO_PIN_PB7, 9); // i2c2_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC0, 9); // i2c2_sda_m0
+      break;
+    case 3:
+      break;
+    case 4:
+      break;
+    case 5:
+      GpioPinSetFunction (1, GPIO_PIN_PB6, 9); // i2c5_scl_m3
+      GpioPinSetFunction (1, GPIO_PIN_PB7, 9); // i2c5_sda_m3
+      break;
+    case 6:
+      GpioPinSetFunction (0, GPIO_PIN_PD0, 9); // i2c6_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC7, 9); // i2c6_sda_m0
+      break;
+    case 7:
+      break;
+    default:
+      break;
   }
 }
 
@@ -233,7 +238,7 @@ UsbPortPowerEnable (
   VOID
   )
 {
-  DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n"));
+  DEBUG ((DEBUG_INFO, "UsbPortPowerEnable called\n"));
 
   /* Enable USB-C VBUS */
   GpioPinWrite (4, GPIO_PIN_PA7, TRUE);
@@ -250,22 +255,23 @@ Usb2PhyResume (
   VOID
   )
 {
-  MmioWrite32(0xfd5d0008, 0x20000000);
-  MmioWrite32(0xfd5d4008, 0x20000000);
-  MmioWrite32(0xfd5d8008, 0x20000000);
-  MmioWrite32(0xfd5dc008, 0x20000000);
-  MmioWrite32(0xfd7f0a10, 0x07000700);
-  MmioWrite32(0xfd7f0a10, 0x07000000);
+  MmioWrite32 (0xfd5d0008, 0x20000000);
+  MmioWrite32 (0xfd5d4008, 0x20000000);
+  MmioWrite32 (0xfd5d8008, 0x20000000);
+  MmioWrite32 (0xfd5dc008, 0x20000000);
+  MmioWrite32 (0xfd7f0a10, 0x07000700);
+  MmioWrite32 (0xfd7f0a10, 0x07000000);
 }
 
 VOID
 EFIAPI
 PcieIoInit (
-  UINT32 Segment
+  UINT32  Segment
   )
 {
   /* Set reset to gpio output mode */
-  if(Segment == PCIE_SEGMENT_PCIE20L0) { // AP6275P Wi-Fi
+  if (Segment == PCIE_SEGMENT_PCIE20L0) {
+    // AP6275P Wi-Fi
     GpioPinSetDirection (1, GPIO_PIN_PB4, GPIO_PIN_OUTPUT);
 
     /* wifi_poweren_gpio */
@@ -276,11 +282,11 @@ PcieIoInit (
 VOID
 EFIAPI
 PciePowerEn (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  if(Segment == PCIE_SEGMENT_PCIE20L0) {
+  if (Segment == PCIE_SEGMENT_PCIE20L0) {
     /* wifi_poweren_gpio */
     GpioPinWrite (1, GPIO_PIN_PB1, Enable);
   }
@@ -289,15 +295,45 @@ PciePowerEn (
 VOID
 EFIAPI
 PciePeReset (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  if(Segment == PCIE_SEGMENT_PCIE20L0) {
+  if (Segment == PCIE_SEGMENT_PCIE20L0) {
     GpioPinWrite (1, GPIO_PIN_PB4, !Enable);
   }
 }
 
+VOID
+EFIAPI
+HdmiTxIomux (
+  IN UINT32  Id
+  )
+{
+  switch (Id) {
+    case 0:
+      GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
+      GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
+      GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
+      GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
+      break;
+    case 1:
+      GpioPinSetFunction (3, GPIO_PIN_PC4, 5); // hdmim2_tx1_cec
+      GpioPinSetPull (3, GPIO_PIN_PC4, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA6, 5); // hdmim0_tx1_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA6, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (3, GPIO_PIN_PC6, 5); // hdmim1_tx1_scl
+      GpioPinSetPull (3, GPIO_PIN_PC6, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (3, GPIO_PIN_PC5, 5); // hdmim1_tx1_sda
+      GpioPinSetPull (3, GPIO_PIN_PC5, GPIO_PIN_PULL_NONE);
+      break;
+  }
+}
+
 VOID
 EFIAPI
 PwmFanIoSetup (
@@ -309,7 +345,7 @@ PwmFanIoSetup (
 VOID
 EFIAPI
 PwmFanSetSpeed (
-  IN UINT32 Percentage
+  IN UINT32  Percentage
   )
 {
 }
@@ -328,7 +364,7 @@ PlatformInitLeds (
 VOID
 EFIAPI
 PlatformSetStatusLed (
-  IN BOOLEAN Enable
+  IN BOOLEAN  Enable
   )
 {
   GpioPinWrite (3, GPIO_PIN_PB7, Enable);
@@ -337,10 +373,11 @@ PlatformSetStatusLed (
 CONST EFI_GUID *
 EFIAPI
 PlatformGetDtbFileGuid (
-  IN UINT32 CompatMode
+  IN UINT32  CompatMode
   )
 {
-  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+  STATIC CONST EFI_GUID  VendorDtbFileGuid = {
+    // DeviceTree/Vendor.inf
     0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
   };
 
@@ -358,5 +395,4 @@ PlatformEarlyInit (
   VOID
   )
 {
-
 }

edk2-rockchip/Platform/Mekotronics/R58-Mini/R58-Mini.dsc

@@ -75,13 +75,6 @@
   gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
   gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6
 
-  #
-  # CPU Performance default values
-  #
-  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-
   #
   # PCIe/SATA/USB Combo PIPE PHY support flags and default values
   #
@@ -111,6 +104,16 @@
   gRK3588TokenSpaceGuid.PcdGmac0Supported|TRUE
   gRK3588TokenSpaceGuid.PcdGmac0TxDelay|0x44
 
+  #
+  # Display support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
+    VOP_OUTPUT_IF_HDMI0,
+    VOP_OUTPUT_IF_HDMI1,
+    VOP_OUTPUT_IF_DP0,
+    VOP_OUTPUT_IF_DP1
+  })}
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.

edk2-rockchip/Platform/Mekotronics/R58X/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -16,29 +16,29 @@
 #include <Soc.h>
 #include <VarStoreData.h>
 
-static struct regulator_init_data rk806_init_data[] = {
+static struct regulator_init_data  rk806_init_data[] = {
   /* Master PMIC */
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
-  //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK4,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK5,  850000),
+  // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK7,  2000000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK8,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK10, 1800000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO2,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO4,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO5,  750000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO1,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO2,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO3,  1200000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO4,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO5,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO6,  1800000),
 
   /* No dual PMICs on this platform */
 };
@@ -50,9 +50,9 @@ SdmmcIoMux (
   )
 {
   /* sdmmc0 iomux (microSD socket) */
-  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
-  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
-  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+  BUS_IOC->GPIO4D_IOMUX_SEL_L  = (0xFFFFUL << 16) | (0x1111); // SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H  = (0x00FFUL << 16) | (0x0011); // SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); // SDMMC_DET
 }
 
 VOID
@@ -62,14 +62,14 @@ SdhciEmmcIoMux (
   )
 {
   /* sdhci0 iomux (eMMC socket) */
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); // EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
 }
 
-#define NS_CRU_BASE         0xFD7C0000
-#define CRU_CLKSEL_CON59    0x03EC
-#define CRU_CLKSEL_CON78    0x0438
+#define NS_CRU_BASE       0xFD7C0000
+#define CRU_CLKSEL_CON59  0x03EC
+#define CRU_CLKSEL_CON78  0x0438
 
 VOID
 EFIAPI
@@ -78,11 +78,11 @@ Rk806SpiIomux (
   )
 {
   /* io mux */
-  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
-  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  // BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  // BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
   PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
   PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+  MmioWrite32 (NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
 }
 
 VOID
@@ -91,24 +91,27 @@ Rk806Configure (
   VOID
   )
 {
-  UINTN RegCfgIndex;
+  UINTN  RegCfgIndex;
 
-  RK806Init();
+  RK806Init ();
 
-  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
-    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
+    RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
+  }
 }
 
 VOID
 EFIAPI
 SetCPULittleVoltage (
-  IN UINT32 Microvolts
+  IN UINT32  Microvolts
   )
 {
-  struct regulator_init_data Rk806CpuLittleSupply =
-        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+  struct regulator_init_data  Rk806CpuLittleSupply =
+    RK8XX_VOLTAGE_INIT (MASTER_BUCK2, Microvolts);
 
-  RK806RegulatorInit(Rk806CpuLittleSupply);
+  RK806RegulatorInit (Rk806CpuLittleSupply);
 }
 
 VOID
@@ -118,31 +121,33 @@ NorFspiIomux (
   )
 {
   /* io mux */
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
-             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
-#define FSPI_M1
-#if defined(FSPI_M0)
-   /*FSPI M0*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
-#elif defined(FSPI_M1)
+  MmioWrite32 (
+    NS_CRU_BASE + CRU_CLKSEL_CON78,
+    (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)
+    );
+  #define FSPI_M1
+ #if defined (FSPI_M0)
+  /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0);   // FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222);     // FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); // FSPI_CS0N_M0
+ #elif defined (FSPI_M1)
   /*FSPI M1*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
-#else
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); // FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); // FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3);         // FSPI_CS0N_M1
+ #else
   /*FSPI M2*/
-  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
-  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
-  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
-#endif
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); // [FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50);     // FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2);         // FSPI_CS0_M2
+ #endif
 }
 
 VOID
 EFIAPI
 GmacIomux (
-  IN UINT32 Id
+  IN UINT32  Id
   )
 {
   switch (Id) {
@@ -198,49 +203,49 @@ GmacIoPhyReset (
 VOID
 EFIAPI
 NorFspiEnableClock (
-  UINT32 *CruBase
+  UINT32  *CruBase
   )
 {
-  UINTN BaseAddr = (UINTN) CruBase;
+  UINTN  BaseAddr = (UINTN)CruBase;
 
-  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+  MmioWrite32 (BaseAddr + 0x087C, 0x0E000000);
 }
 
 VOID
 EFIAPI
 I2cIomux (
-   UINT32 id
+  UINT32  id
   )
 {
   switch (id) {
-  case 0:
-    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
-    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
-    break;
-  case 1:
-    break;
-  case 2:
-    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
-    break;
-  case 3:
-    GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0
-    GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0
-    break;
-  case 4:
-    break;
-  case 5:
-    GpioPinSetFunction(1, GPIO_PIN_PB6, 9); //i2c5_scl_m3
-    GpioPinSetFunction(1, GPIO_PIN_PB7, 9); //i2c5_sda_m3
-    break;
-  case 6:
-    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
-    break;
-  case 7:
-    break;
-  default:
-    break;
+    case 0:
+      GpioPinSetFunction (0, GPIO_PIN_PD1, 3); // i2c0_scl_m2
+      GpioPinSetFunction (0, GPIO_PIN_PD2, 3); // i2c0_sda_m2
+      break;
+    case 1:
+      break;
+    case 2:
+      GpioPinSetFunction (0, GPIO_PIN_PB7, 9); // i2c2_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC0, 9); // i2c2_sda_m0
+      break;
+    case 3:
+      GpioPinSetFunction (1, GPIO_PIN_PC1, 9); // i2c3_scl_m0
+      GpioPinSetFunction (1, GPIO_PIN_PC0, 9); // i2c3_sda_m0
+      break;
+    case 4:
+      break;
+    case 5:
+      GpioPinSetFunction (1, GPIO_PIN_PB6, 9); // i2c5_scl_m3
+      GpioPinSetFunction (1, GPIO_PIN_PB7, 9); // i2c5_sda_m3
+      break;
+    case 6:
+      GpioPinSetFunction (0, GPIO_PIN_PD0, 9); // i2c6_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC7, 9); // i2c6_sda_m0
+      break;
+    case 7:
+      break;
+    default:
+      break;
   }
 }
 
@@ -250,7 +255,7 @@ UsbPortPowerEnable (
   VOID
   )
 {
-  DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n"));
+  DEBUG ((DEBUG_INFO, "UsbPortPowerEnable called\n"));
 
   /* Enable USB-C VBUS */
   GpioPinWrite (4, GPIO_PIN_PA7, TRUE);
@@ -267,22 +272,22 @@ Usb2PhyResume (
   VOID
   )
 {
-  MmioWrite32(0xfd5d0008, 0x20000000);
-  MmioWrite32(0xfd5d4008, 0x20000000);
-  MmioWrite32(0xfd5d8008, 0x20000000);
-  MmioWrite32(0xfd5dc008, 0x20000000);
-  MmioWrite32(0xfd7f0a10, 0x07000700);
-  MmioWrite32(0xfd7f0a10, 0x07000000);
+  MmioWrite32 (0xfd5d0008, 0x20000000);
+  MmioWrite32 (0xfd5d4008, 0x20000000);
+  MmioWrite32 (0xfd5d8008, 0x20000000);
+  MmioWrite32 (0xfd5dc008, 0x20000000);
+  MmioWrite32 (0xfd7f0a10, 0x07000700);
+  MmioWrite32 (0xfd7f0a10, 0x07000000);
 }
 
 VOID
 EFIAPI
 PcieIoInit (
-  UINT32 Segment
+  UINT32  Segment
   )
 {
   /* Set reset and power IO to gpio output mode */
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4: // M.2 M Key
       /* reset */
       GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
@@ -304,11 +309,11 @@ PcieIoInit (
 VOID
 EFIAPI
 PciePowerEn (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4:
       /* vcc3v3_pcie30 */
       GpioPinWrite (1, GPIO_PIN_PC4, Enable);
@@ -325,11 +330,11 @@ PciePowerEn (
 VOID
 EFIAPI
 PciePeReset (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4:
       GpioPinWrite (4, GPIO_PIN_PB6, !Enable);
       break;
@@ -341,6 +346,26 @@ PciePeReset (
   }
 }
 
+VOID
+EFIAPI
+HdmiTxIomux (
+  IN UINT32  Id
+  )
+{
+  switch (Id) {
+    case 0:
+      GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
+      GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
+      GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
+      GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
+      break;
+  }
+}
+
 VOID
 EFIAPI
 PwmFanIoSetup (
@@ -352,7 +377,7 @@ PwmFanIoSetup (
 VOID
 EFIAPI
 PwmFanSetSpeed (
-  IN UINT32 Percentage
+  IN UINT32  Percentage
   )
 {
 }
@@ -371,7 +396,7 @@ PlatformInitLeds (
 VOID
 EFIAPI
 PlatformSetStatusLed (
-  IN BOOLEAN Enable
+  IN BOOLEAN  Enable
   )
 {
   GpioPinWrite (3, GPIO_PIN_PB7, Enable);
@@ -380,10 +405,11 @@ PlatformSetStatusLed (
 CONST EFI_GUID *
 EFIAPI
 PlatformGetDtbFileGuid (
-  IN UINT32 CompatMode
+  IN UINT32  CompatMode
   )
 {
-  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+  STATIC CONST EFI_GUID  VendorDtbFileGuid = {
+    // DeviceTree/Vendor.inf
     0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
   };
 
@@ -401,5 +427,5 @@ PlatformEarlyInit (
   VOID
   )
 {
-  GpioPinSetFunction(3, GPIO_PIN_PB2, 0); //jdet
+  GpioPinSetFunction (3, GPIO_PIN_PB2, 0); // jdet
 }

edk2-rockchip/Platform/Mekotronics/R58X/R58X.dsc

@@ -75,13 +75,6 @@
   # Disable HS400 for now, otherwise eMMC is unusable.
   gRockchipTokenSpaceGuid.PcdDwcSdhciDisableHs400|TRUE
 
-  #
-  # CPU Performance default values
-  #
-  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-
   #
   # PCIe/SATA/USB Combo PIPE PHY support flags and default values
   #
@@ -113,6 +106,15 @@
   #
   gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE
 
+  #
+  # Display support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
+    VOP_OUTPUT_IF_HDMI0,
+    VOP_OUTPUT_IF_DP0,
+    VOP_OUTPUT_IF_DP1
+  })}
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.

edk2-rockchip/Platform/Mixtile/Blade3/Blade3.dsc

@@ -27,6 +27,9 @@
   FLASH_DEFINITION               = Silicon/Rockchip/RK3588/RK3588.fdf
   RK_PLATFORM_FVMAIN_MODULES     = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc
 
+  # GMAC is not exposed
+  DEFINE RK3588_GMAC_ENABLE = FALSE
+
   # No status LED on this platform.
   DEFINE RK_STATUS_LED_ENABLE = FALSE
 
@@ -66,13 +69,6 @@
   gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 }
   gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) }
 
-  #
-  # CPU Performance default values
-  #
-  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-
   #
   # PCIe/SATA/USB Combo PIPE PHY support flags and default values
   #
@@ -96,6 +92,15 @@
   #
   gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
 
+  #
+  # Display support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
+    VOP_OUTPUT_IF_HDMI0,
+    VOP_OUTPUT_IF_DP0,
+    VOP_OUTPUT_IF_DP1
+  })}
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.

edk2-rockchip/Platform/Mixtile/Blade3/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -17,29 +17,29 @@
 #include <Soc.h>
 #include <VarStoreData.h>
 
-static struct regulator_init_data rk806_init_data[] = {
+static struct regulator_init_data  rk806_init_data[] = {
   /* Master PMIC */
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
-  //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK4,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK5,  850000),
+  // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK7,  2000000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK8,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK10, 1800000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO2,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO4,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO5,  750000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO1,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO2,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO3,  1200000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO4,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO5,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO6,  1800000),
 
   /* No dual PMICs on this platform */
 };
@@ -51,9 +51,9 @@ SdmmcIoMux (
   )
 {
   /* sdmmc0 iomux (microSD socket) */
-  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
-  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
-  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+  BUS_IOC->GPIO4D_IOMUX_SEL_L  = (0xFFFFUL << 16) | (0x1111); // SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H  = (0x00FFUL << 16) | (0x0011); // SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); // SDMMC_DET
 }
 
 VOID
@@ -63,14 +63,14 @@ SdhciEmmcIoMux (
   )
 {
   /* sdhci0 iomux (eMMC socket) */
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); // EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
 }
 
-#define NS_CRU_BASE         0xFD7C0000
-#define CRU_CLKSEL_CON59    0x03EC
-#define CRU_CLKSEL_CON78    0x0438
+#define NS_CRU_BASE       0xFD7C0000
+#define CRU_CLKSEL_CON59  0x03EC
+#define CRU_CLKSEL_CON78  0x0438
 
 VOID
 EFIAPI
@@ -79,11 +79,11 @@ Rk806SpiIomux (
   )
 {
   /* io mux */
-  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
-  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  // BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  // BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
   PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
   PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+  MmioWrite32 (NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
 }
 
 VOID
@@ -92,24 +92,27 @@ Rk806Configure (
   VOID
   )
 {
-  UINTN RegCfgIndex;
+  UINTN  RegCfgIndex;
 
-  RK806Init();
+  RK806Init ();
 
-  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
-    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
+    RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
+  }
 }
 
 VOID
 EFIAPI
 SetCPULittleVoltage (
-  IN UINT32 Microvolts
+  IN UINT32  Microvolts
   )
 {
-  struct regulator_init_data Rk806CpuLittleSupply =
-        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+  struct regulator_init_data  Rk806CpuLittleSupply =
+    RK8XX_VOLTAGE_INIT (MASTER_BUCK2, Microvolts);
 
-  RK806RegulatorInit(Rk806CpuLittleSupply);
+  RK806RegulatorInit (Rk806CpuLittleSupply);
 }
 
 VOID
@@ -119,31 +122,33 @@ NorFspiIomux (
   )
 {
   /* io mux */
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
-             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
-#define FSPI_M1
-#if defined(FSPI_M0)
-   /*FSPI M0*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
-#elif defined(FSPI_M1)
+  MmioWrite32 (
+    NS_CRU_BASE + CRU_CLKSEL_CON78,
+    (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)
+    );
+  #define FSPI_M1
+ #if defined (FSPI_M0)
+  /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0);   // FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222);     // FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); // FSPI_CS0N_M0
+ #elif defined (FSPI_M1)
   /*FSPI M1*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
-#else
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); // FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); // FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3);         // FSPI_CS0N_M1
+ #else
   /*FSPI M2*/
-  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
-  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
-  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
-#endif
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); // [FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50);     // FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2);         // FSPI_CS0_M2
+ #endif
 }
 
 VOID
 EFIAPI
 GmacIomux (
-  IN UINT32 Id
+  IN UINT32  Id
   )
 {
   /* No GMAC here */
@@ -152,49 +157,49 @@ GmacIomux (
 VOID
 EFIAPI
 NorFspiEnableClock (
-  UINT32 *CruBase
+  UINT32  *CruBase
   )
 {
-  UINTN BaseAddr = (UINTN) CruBase;
+  UINTN  BaseAddr = (UINTN)CruBase;
 
-  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+  MmioWrite32 (BaseAddr + 0x087C, 0x0E000000);
 }
 
 VOID
 EFIAPI
 I2cIomux (
-   UINT32 id
+  UINT32  id
   )
 {
   switch (id) {
-  case 0:
-    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
-    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
-    break;
-  case 1:
-    GpioPinSetFunction(0, GPIO_PIN_PD4, 9); //i2c1_scl_m2
-    GpioPinSetFunction(0, GPIO_PIN_PD5, 9); //i2c1_sda_m2
-    break;
-  case 2:
-    break;
-  case 3:
-    break;
-  case 4:
-    GpioPinSetFunction(3, GPIO_PIN_PA6, 9); //i2c4_scl_m0
-    GpioPinSetFunction(3, GPIO_PIN_PA5, 9); //i2c4_sda_m0
-    break;
-  case 5:
-    GpioPinSetFunction(1, GPIO_PIN_PB6, 9); //i2c5_scl_m3
-    GpioPinSetFunction(1, GPIO_PIN_PB7, 9); //i2c5_sda_m3
-    break;
-  case 6:
-    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
-    break;
-  case 7:
-    break;
-  default:
-    break;
+    case 0:
+      GpioPinSetFunction (0, GPIO_PIN_PD1, 3); // i2c0_scl_m2
+      GpioPinSetFunction (0, GPIO_PIN_PD2, 3); // i2c0_sda_m2
+      break;
+    case 1:
+      GpioPinSetFunction (0, GPIO_PIN_PD4, 9); // i2c1_scl_m2
+      GpioPinSetFunction (0, GPIO_PIN_PD5, 9); // i2c1_sda_m2
+      break;
+    case 2:
+      break;
+    case 3:
+      break;
+    case 4:
+      GpioPinSetFunction (3, GPIO_PIN_PA6, 9); // i2c4_scl_m0
+      GpioPinSetFunction (3, GPIO_PIN_PA5, 9); // i2c4_sda_m0
+      break;
+    case 5:
+      GpioPinSetFunction (1, GPIO_PIN_PB6, 9); // i2c5_scl_m3
+      GpioPinSetFunction (1, GPIO_PIN_PB7, 9); // i2c5_sda_m3
+      break;
+    case 6:
+      GpioPinSetFunction (0, GPIO_PIN_PD0, 9); // i2c6_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC7, 9); // i2c6_sda_m0
+      break;
+    case 7:
+      break;
+    default:
+      break;
   }
 }
 
@@ -204,7 +209,7 @@ UsbPortPowerEnable (
   VOID
   )
 {
-  DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n"));
+  DEBUG ((DEBUG_INFO, "UsbPortPowerEnable called\n"));
 
   /* vbus5v0_typec0 (data-only port) */
   GpioPinWrite (4, GPIO_PIN_PB0, TRUE);
@@ -224,22 +229,22 @@ Usb2PhyResume (
   VOID
   )
 {
-  MmioWrite32(0xfd5d0008, 0x20000000);
-  MmioWrite32(0xfd5d4008, 0x20000000);
-  MmioWrite32(0xfd5d8008, 0x20000000);
-  MmioWrite32(0xfd5dc008, 0x20000000);
-  MmioWrite32(0xfd7f0a10, 0x07000700);
-  MmioWrite32(0xfd7f0a10, 0x07000000);
+  MmioWrite32 (0xfd5d0008, 0x20000000);
+  MmioWrite32 (0xfd5d4008, 0x20000000);
+  MmioWrite32 (0xfd5d8008, 0x20000000);
+  MmioWrite32 (0xfd5dc008, 0x20000000);
+  MmioWrite32 (0xfd7f0a10, 0x07000700);
+  MmioWrite32 (0xfd7f0a10, 0x07000000);
 }
 
 VOID
 EFIAPI
 PcieIoInit (
-  UINT32 Segment
+  UINT32  Segment
   )
 {
   /* Set reset and power IO to gpio output mode */
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4: // U.2
       /* reset */
       GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
@@ -260,11 +265,11 @@ PcieIoInit (
 VOID
 EFIAPI
 PciePowerEn (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4:
       GpioPinWrite (1, GPIO_PIN_PB2, Enable);
       break;
@@ -274,11 +279,11 @@ PciePowerEn (
 VOID
 EFIAPI
 PciePeReset (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4:
       GpioPinWrite (4, GPIO_PIN_PB6, !Enable);
       break;
@@ -291,12 +296,32 @@ PciePeReset (
   }
 }
 
-PWM_DATA pwm_data = {
+VOID
+EFIAPI
+HdmiTxIomux (
+  IN UINT32  Id
+  )
+{
+  switch (Id) {
+    case 0:
+      GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
+      GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
+      GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
+      GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
+      break;
+  }
+}
+
+PWM_DATA  pwm_data = {
   .ControllerID = PWM_CONTROLLER2,
-  .ChannelID = PWM_CHANNEL0,
-  .PeriodNs = 4000000,
-  .DutyNs = 4000000,
-  .Polarity = FALSE,
+  .ChannelID    = PWM_CHANNEL0,
+  .PeriodNs     = 4000000,
+  .DutyNs       = 4000000,
+  .Polarity     = FALSE,
 }; // PWM2_CH0
 
 VOID
@@ -313,7 +338,7 @@ PwmFanIoSetup (
 VOID
 EFIAPI
 PwmFanSetSpeed (
-  IN UINT32 Percentage
+  IN UINT32  Percentage
   )
 {
   pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100;
@@ -332,7 +357,7 @@ PlatformInitLeds (
 VOID
 EFIAPI
 PlatformSetStatusLed (
-  IN BOOLEAN Enable
+  IN BOOLEAN  Enable
   )
 {
   // No controllable LEDs on this platform
@@ -341,10 +366,11 @@ PlatformSetStatusLed (
 CONST EFI_GUID *
 EFIAPI
 PlatformGetDtbFileGuid (
-  IN UINT32 CompatMode
+  IN UINT32  CompatMode
   )
 {
-  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+  STATIC CONST EFI_GUID  VendorDtbFileGuid = {
+    // DeviceTree/Vendor.inf
     0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
   };
 

edk2-rockchip/Platform/Mixtile/Drivers/LogoDxe/Logo.c

@@ -19,15 +19,15 @@
 #include <Library/DebugLib.h>
 
 typedef struct {
-  EFI_IMAGE_ID                          ImageId;
-  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
-  INTN                                  OffsetX;
-  INTN                                  OffsetY;
+  EFI_IMAGE_ID                             ImageId;
+  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE    Attribute;
+  INTN                                     OffsetX;
+  INTN                                     OffsetY;
 } LOGO_ENTRY;
 
-STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
-STATIC EFI_HII_HANDLE            mHiiHandle;
-STATIC LOGO_ENTRY                mLogos[] = {
+STATIC EFI_HII_IMAGE_EX_PROTOCOL  *mHiiImageEx;
+STATIC EFI_HII_HANDLE             mHiiHandle;
+STATIC LOGO_ENTRY                 mLogos[] = {
   {
     IMAGE_TOKEN (IMG_LOGO),
     EdkiiPlatformLogoDisplayAttributeCenter,
@@ -53,18 +53,19 @@ STATIC
 EFI_STATUS
 EFIAPI
 GetImage (
-  IN     EDKII_PLATFORM_LOGO_PROTOCOL          *This,
-  IN OUT UINT32                                *Instance,
-     OUT EFI_IMAGE_INPUT                       *Image,
-     OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
-     OUT INTN                                  *OffsetX,
-     OUT INTN                                  *OffsetY
+  IN     EDKII_PLATFORM_LOGO_PROTOCOL        *This,
+  IN OUT UINT32                              *Instance,
+  OUT EFI_IMAGE_INPUT                        *Image,
+  OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE  *Attribute,
+  OUT INTN                                   *OffsetX,
+  OUT INTN                                   *OffsetY
   )
 {
-  UINT32 Current;
+  UINT32  Current;
 
-  if (Instance == NULL || Image == NULL ||
-      Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
+  if ((Instance == NULL) || (Image == NULL) ||
+      (Attribute == NULL) || (OffsetX == NULL) || (OffsetY == NULL))
+  {
     return EFI_INVALID_PARAMETER;
   }
 
@@ -78,11 +79,15 @@ GetImage (
   *OffsetX   = mLogos[Current].OffsetX;
   *OffsetY   = mLogos[Current].OffsetY;
 
-  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
-                        mLogos[Current].ImageId, Image);
+  return mHiiImageEx->GetImageEx (
+                        mHiiImageEx,
+                        mHiiHandle,
+                        mLogos[Current].ImageId,
+                        Image
+                        );
 }
 
-STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+STATIC EDKII_PLATFORM_LOGO_PROTOCOL  mPlatformLogo = {
   GetImage
 };
 
@@ -101,44 +106,66 @@ STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
 EFI_STATUS
 EFIAPI
 InitializeLogo (
-  IN EFI_HANDLE               ImageHandle,
-  IN EFI_SYSTEM_TABLE         *SystemTable
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
-  EFI_STATUS                  Status;
-  EFI_HII_PACKAGE_LIST_HEADER *PackageList;
-  EFI_HII_DATABASE_PROTOCOL   *HiiDatabase;
-  EFI_HANDLE                  Handle;
+  EFI_STATUS                   Status;
+  EFI_HII_PACKAGE_LIST_HEADER  *PackageList;
+  EFI_HII_DATABASE_PROTOCOL    *HiiDatabase;
+  EFI_HANDLE                   Handle;
 
-  Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
-                  (VOID **) &HiiDatabase);
+  Status = gBS->LocateProtocol (
+                  &gEfiHiiDatabaseProtocolGuid,
+                  NULL,
+                  (VOID **)&HiiDatabase
+                  );
   ASSERT_EFI_ERROR (Status);
 
-  Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
-                  (VOID **) &mHiiImageEx);
+  Status = gBS->LocateProtocol (
+                  &gEfiHiiImageExProtocolGuid,
+                  NULL,
+                  (VOID **)&mHiiImageEx
+                  );
   ASSERT_EFI_ERROR (Status);
 
   //
   // Retrieve HII package list from ImageHandle
   //
-  Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
-                  (VOID **) &PackageList, ImageHandle, NULL,
-                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+  Status = gBS->OpenProtocol (
+                  ImageHandle,
+                  &gEfiHiiPackageListProtocolGuid,
+                  (VOID **)&PackageList,
+                  ImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
   if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR,
-      "HII Image Package with logo not found in PE/COFF resource section\n"));
+    DEBUG ((
+      DEBUG_ERROR,
+      "HII Image Package with logo not found in PE/COFF resource section\n"
+      ));
     return Status;
   }
 
   //
   // Publish HII package list to HII Database.
   //
-  Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
-                          &mHiiHandle);
+  Status = HiiDatabase->NewPackageList (
+                          HiiDatabase,
+                          PackageList,
+                          NULL,
+                          &mHiiHandle
+                          );
   if (!EFI_ERROR (Status)) {
     Handle = NULL;
-    Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
-                    &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
+    Status = gBS->InstallMultipleProtocolInterfaces (
+                    &Handle,
+                    &gEdkiiPlatformLogoProtocolGuid,
+                    &mPlatformLogo,
+                    NULL
+                    );
   }
+
   return Status;
 }

edk2-rockchip/Platform/OrangePi/Drivers/LogoDxe/Logo.c

@@ -19,15 +19,15 @@
 #include <Library/DebugLib.h>
 
 typedef struct {
-  EFI_IMAGE_ID                          ImageId;
-  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
-  INTN                                  OffsetX;
-  INTN                                  OffsetY;
+  EFI_IMAGE_ID                             ImageId;
+  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE    Attribute;
+  INTN                                     OffsetX;
+  INTN                                     OffsetY;
 } LOGO_ENTRY;
 
-STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
-STATIC EFI_HII_HANDLE            mHiiHandle;
-STATIC LOGO_ENTRY                mLogos[] = {
+STATIC EFI_HII_IMAGE_EX_PROTOCOL  *mHiiImageEx;
+STATIC EFI_HII_HANDLE             mHiiHandle;
+STATIC LOGO_ENTRY                 mLogos[] = {
   {
     IMAGE_TOKEN (IMG_LOGO),
     EdkiiPlatformLogoDisplayAttributeCenter,
@@ -53,18 +53,19 @@ STATIC
 EFI_STATUS
 EFIAPI
 GetImage (
-  IN     EDKII_PLATFORM_LOGO_PROTOCOL          *This,
-  IN OUT UINT32                                *Instance,
-     OUT EFI_IMAGE_INPUT                       *Image,
-     OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
-     OUT INTN                                  *OffsetX,
-     OUT INTN                                  *OffsetY
+  IN     EDKII_PLATFORM_LOGO_PROTOCOL        *This,
+  IN OUT UINT32                              *Instance,
+  OUT EFI_IMAGE_INPUT                        *Image,
+  OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE  *Attribute,
+  OUT INTN                                   *OffsetX,
+  OUT INTN                                   *OffsetY
   )
 {
-  UINT32 Current;
+  UINT32  Current;
 
-  if (Instance == NULL || Image == NULL ||
-      Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
+  if ((Instance == NULL) || (Image == NULL) ||
+      (Attribute == NULL) || (OffsetX == NULL) || (OffsetY == NULL))
+  {
     return EFI_INVALID_PARAMETER;
   }
 
@@ -78,11 +79,15 @@ GetImage (
   *OffsetX   = mLogos[Current].OffsetX;
   *OffsetY   = mLogos[Current].OffsetY;
 
-  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
-                        mLogos[Current].ImageId, Image);
+  return mHiiImageEx->GetImageEx (
+                        mHiiImageEx,
+                        mHiiHandle,
+                        mLogos[Current].ImageId,
+                        Image
+                        );
 }
 
-STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+STATIC EDKII_PLATFORM_LOGO_PROTOCOL  mPlatformLogo = {
   GetImage
 };
 
@@ -101,44 +106,66 @@ STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
 EFI_STATUS
 EFIAPI
 InitializeLogo (
-  IN EFI_HANDLE               ImageHandle,
-  IN EFI_SYSTEM_TABLE         *SystemTable
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
-  EFI_STATUS                  Status;
-  EFI_HII_PACKAGE_LIST_HEADER *PackageList;
-  EFI_HII_DATABASE_PROTOCOL   *HiiDatabase;
-  EFI_HANDLE                  Handle;
+  EFI_STATUS                   Status;
+  EFI_HII_PACKAGE_LIST_HEADER  *PackageList;
+  EFI_HII_DATABASE_PROTOCOL    *HiiDatabase;
+  EFI_HANDLE                   Handle;
 
-  Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
-                  (VOID **) &HiiDatabase);
+  Status = gBS->LocateProtocol (
+                  &gEfiHiiDatabaseProtocolGuid,
+                  NULL,
+                  (VOID **)&HiiDatabase
+                  );
   ASSERT_EFI_ERROR (Status);
 
-  Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
-                  (VOID **) &mHiiImageEx);
+  Status = gBS->LocateProtocol (
+                  &gEfiHiiImageExProtocolGuid,
+                  NULL,
+                  (VOID **)&mHiiImageEx
+                  );
   ASSERT_EFI_ERROR (Status);
 
   //
   // Retrieve HII package list from ImageHandle
   //
-  Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
-                  (VOID **) &PackageList, ImageHandle, NULL,
-                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+  Status = gBS->OpenProtocol (
+                  ImageHandle,
+                  &gEfiHiiPackageListProtocolGuid,
+                  (VOID **)&PackageList,
+                  ImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
   if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR,
-      "HII Image Package with logo not found in PE/COFF resource section\n"));
+    DEBUG ((
+      DEBUG_ERROR,
+      "HII Image Package with logo not found in PE/COFF resource section\n"
+      ));
     return Status;
   }
 
   //
   // Publish HII package list to HII Database.
   //
-  Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
-                          &mHiiHandle);
+  Status = HiiDatabase->NewPackageList (
+                          HiiDatabase,
+                          PackageList,
+                          NULL,
+                          &mHiiHandle
+                          );
   if (!EFI_ERROR (Status)) {
     Handle = NULL;
-    Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
-                    &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
+    Status = gBS->InstallMultipleProtocolInterfaces (
+                    &Handle,
+                    &gEdkiiPlatformLogoProtocolGuid,
+                    &mPlatformLogo,
+                    NULL
+                    );
   }
+
   return Status;
 }

edk2-rockchip/Platform/OrangePi/OrangePi5/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -17,31 +17,32 @@
 #include <Soc.h>
 #include <VarStoreData.h>
 
-static struct regulator_init_data rk806_init_data[] = {
+static struct regulator_init_data  rk806_init_data[] = {
   /* Master PMIC */
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK1,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK4,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK5,  850000),
+
   /* This is not configured in the OrangePi5's Linux device tree
   RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 1100000), */
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK7,  2000000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK8,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK10, 1800000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO2,  850000),
   /* The OPi is officially configured for the 837500 voltage, but is still marked as avdd_0v75_s0 in the schematic and Linux device tree. rockchip says this voltage is set to improve HDMI stability. */
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 837500),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO3,  837500),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO4,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO5,  750000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO1,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO2,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO3,  1200000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO4,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO5,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO6,  1800000),
   /* No dual PMICs on this platform */
 };
 
@@ -52,9 +53,9 @@ SdmmcIoMux (
   )
 {
   /* sdmmc0 iomux (microSD socket) */
-  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
-  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
-  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+  BUS_IOC->GPIO4D_IOMUX_SEL_L  = (0xFFFFUL << 16) | (0x1111); // SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H  = (0x00FFUL << 16) | (0x0011); // SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); // SDMMC_DET
 }
 
 VOID
@@ -67,9 +68,9 @@ SdhciEmmcIoMux (
   /* Do not override, set by earlier boot stages. */
 }
 
-#define NS_CRU_BASE         0xFD7C0000
-#define CRU_CLKSEL_CON59    0x03EC
-#define CRU_CLKSEL_CON78    0x0438
+#define NS_CRU_BASE       0xFD7C0000
+#define CRU_CLKSEL_CON59  0x03EC
+#define CRU_CLKSEL_CON78  0x0438
 
 VOID
 EFIAPI
@@ -78,11 +79,11 @@ Rk806SpiIomux (
   )
 {
   /* io mux */
-  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
-  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  // BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  // BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
   PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
   PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+  MmioWrite32 (NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
 }
 
 VOID
@@ -91,24 +92,27 @@ Rk806Configure (
   VOID
   )
 {
-  UINTN RegCfgIndex;
+  UINTN  RegCfgIndex;
 
-  RK806Init();
+  RK806Init ();
 
-  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
-    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
+    RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
+  }
 }
 
 VOID
 EFIAPI
 SetCPULittleVoltage (
-  IN UINT32 Microvolts
+  IN UINT32  Microvolts
   )
 {
-  struct regulator_init_data Rk806CpuLittleSupply =
-        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+  struct regulator_init_data  Rk806CpuLittleSupply =
+    RK8XX_VOLTAGE_INIT (MASTER_BUCK2, Microvolts);
 
-  RK806RegulatorInit(Rk806CpuLittleSupply);
+  RK806RegulatorInit (Rk806CpuLittleSupply);
 }
 
 VOID
@@ -124,7 +128,7 @@ NorFspiIomux (
 VOID
 EFIAPI
 GmacIomux (
-  IN UINT32 Id
+  IN UINT32  Id
   )
 {
   switch (Id) {
@@ -164,49 +168,49 @@ GmacIoPhyReset (
 VOID
 EFIAPI
 NorFspiEnableClock (
-  UINT32 *CruBase
+  UINT32  *CruBase
   )
 {
-  UINTN BaseAddr = (UINTN) CruBase;
+  UINTN  BaseAddr = (UINTN)CruBase;
 
-  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+  MmioWrite32 (BaseAddr + 0x087C, 0x0E000000);
 }
 
 VOID
 EFIAPI
 I2cIomux (
-   UINT32 id
+  UINT32  id
   )
 {
   switch (id) {
-  case 0:
-    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
-    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
-    break;
-  case 1:
-    break;
-  case 2:
-    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
-    break;
-  case 3:
-    break;
-  case 4:
-    GpioPinSetFunction(3, GPIO_PIN_PA6, 9); //i2c4_scl_m0
-    GpioPinSetFunction(3, GPIO_PIN_PA5, 9); //i2c4_sda_m0
-    break;
-  case 5:
-    break;
-  case 6:
-    GpioPinSetFunction(4, GPIO_PIN_PB1, 9); //i2c6_scl_m3
-    GpioPinSetFunction(4, GPIO_PIN_PB0, 9); //i2c6_sda_m3
-    break;
-  case 7:
-    GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0
-    GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0
-    break;
-  default:
-    break;
+    case 0:
+      GpioPinSetFunction (0, GPIO_PIN_PD1, 3); // i2c0_scl_m2
+      GpioPinSetFunction (0, GPIO_PIN_PD2, 3); // i2c0_sda_m2
+      break;
+    case 1:
+      break;
+    case 2:
+      GpioPinSetFunction (0, GPIO_PIN_PB7, 9); // i2c2_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC0, 9); // i2c2_sda_m0
+      break;
+    case 3:
+      break;
+    case 4:
+      GpioPinSetFunction (3, GPIO_PIN_PA6, 9); // i2c4_scl_m0
+      GpioPinSetFunction (3, GPIO_PIN_PA5, 9); // i2c4_sda_m0
+      break;
+    case 5:
+      break;
+    case 6:
+      GpioPinSetFunction (4, GPIO_PIN_PB1, 9); // i2c6_scl_m3
+      GpioPinSetFunction (4, GPIO_PIN_PB0, 9); // i2c6_sda_m3
+      break;
+    case 7:
+      GpioPinSetFunction (1, GPIO_PIN_PD0, 9); // i2c7_scl_m0
+      GpioPinSetFunction (1, GPIO_PIN_PD1, 9); // i2c7_sda_m0
+      break;
+    default:
+      break;
   }
 }
 
@@ -216,7 +220,7 @@ UsbPortPowerEnable (
   VOID
   )
 {
-  DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n"));
+  DEBUG ((DEBUG_INFO, "UsbPortPowerEnable called\n"));
   /* Set GPIO3 PC0 (TYPEC_EN) output high to power Type-C/USB2.0 ports */
   GpioPinWrite (3, GPIO_PIN_PC0, TRUE);
   GpioPinSetDirection (3, GPIO_PIN_PC0, GPIO_PIN_OUTPUT);
@@ -232,22 +236,23 @@ Usb2PhyResume (
   VOID
   )
 {
-  MmioWrite32(0xfd5d0008, 0x20000000);
-  MmioWrite32(0xfd5d4008, 0x20000000);
-  MmioWrite32(0xfd5d8008, 0x20000000);
-  MmioWrite32(0xfd5dc008, 0x20000000);
-  MmioWrite32(0xfd7f0a10, 0x07000700);
-  MmioWrite32(0xfd7f0a10, 0x07000000);
+  MmioWrite32 (0xfd5d0008, 0x20000000);
+  MmioWrite32 (0xfd5d4008, 0x20000000);
+  MmioWrite32 (0xfd5d8008, 0x20000000);
+  MmioWrite32 (0xfd5dc008, 0x20000000);
+  MmioWrite32 (0xfd7f0a10, 0x07000700);
+  MmioWrite32 (0xfd7f0a10, 0x07000000);
 }
 
 VOID
 EFIAPI
 PcieIoInit (
-  UINT32 Segment
+  UINT32  Segment
   )
 {
   /* Set reset to gpio output mode */
-  if(Segment == PCIE_SEGMENT_PCIE20L2) { // M.2 M Key
+  if (Segment == PCIE_SEGMENT_PCIE20L2) {
+    // M.2 M Key
     GpioPinSetDirection (3, GPIO_PIN_PD1, GPIO_PIN_OUTPUT);
   }
 }
@@ -255,8 +260,8 @@ PcieIoInit (
 VOID
 EFIAPI
 PciePowerEn (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
   /* nothing to power on */
@@ -265,21 +270,41 @@ PciePowerEn (
 VOID
 EFIAPI
 PciePeReset (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  if(Segment == PCIE_SEGMENT_PCIE20L2) {
+  if (Segment == PCIE_SEGMENT_PCIE20L2) {
     GpioPinWrite (3, GPIO_PIN_PD1, !Enable);
   }
 }
 
-PWM_DATA pwm_data = {
+VOID
+EFIAPI
+HdmiTxIomux (
+  IN UINT32  Id
+  )
+{
+  switch (Id) {
+    case 0:
+      GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
+      GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
+      GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
+      GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
+      break;
+  }
+}
+
+PWM_DATA  pwm_data = {
   .ControllerID = PWM_CONTROLLER3,
-  .ChannelID = PWM_CHANNEL2,
-  .PeriodNs = 4000000,
-  .DutyNs = 4000000,
-  .Polarity = FALSE,
+  .ChannelID    = PWM_CHANNEL2,
+  .PeriodNs     = 4000000,
+  .DutyNs       = 4000000,
+  .Polarity     = FALSE,
 }; // PWM3_CH2
 
 VOID
@@ -296,7 +321,7 @@ PwmFanIoSetup (
 VOID
 EFIAPI
 PwmFanSetSpeed (
-  IN UINT32 Percentage
+  IN UINT32  Percentage
   )
 {
   pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100;
@@ -317,7 +342,7 @@ PlatformInitLeds (
 VOID
 EFIAPI
 PlatformSetStatusLed (
-  IN BOOLEAN Enable
+  IN BOOLEAN  Enable
   )
 {
   GpioPinWrite (1, GPIO_PIN_PA2, Enable);
@@ -326,13 +351,15 @@ PlatformSetStatusLed (
 CONST EFI_GUID *
 EFIAPI
 PlatformGetDtbFileGuid (
-  IN UINT32 CompatMode
+  IN UINT32  CompatMode
   )
 {
-  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+  STATIC CONST EFI_GUID  VendorDtbFileGuid = {
+    // DeviceTree/Vendor.inf
     0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
   };
-  STATIC CONST EFI_GUID MainlineDtbFileGuid = {       // DeviceTree/Mainline.inf
+  STATIC CONST EFI_GUID  MainlineDtbFileGuid = {
+    // DeviceTree/Mainline.inf
     0x84492e97, 0xa10f, 0x49a7, { 0x85, 0xe9, 0x02, 0x5d, 0x19, 0x66, 0xb3, 0x43 }
   };
 
@@ -354,5 +381,5 @@ PlatformEarlyInit (
 {
   // Configure various things specific to this platform
 
-  GpioPinSetFunction(1, GPIO_PIN_PD5, 0); //jdet
+  GpioPinSetFunction (1, GPIO_PIN_PD5, 0); // jdet
 }

edk2-rockchip/Platform/OrangePi/OrangePi5/OrangePi5.dsc

@@ -72,13 +72,6 @@
   gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
   gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6
 
-  #
-  # CPU Performance default values
-  #
-  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-
   #
   # PCIe/SATA/USB Combo PIPE PHY support flags and default values
   #
@@ -109,6 +102,14 @@
   #
   gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
 
+  #
+  # Display support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
+    VOP_OUTPUT_IF_HDMI0,
+    VOP_OUTPUT_IF_DP0
+  })}
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.

edk2-rockchip/Platform/OrangePi/OrangePi5Plus/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -17,29 +17,29 @@
 #include <Soc.h>
 #include <VarStoreData.h>
 
-static struct regulator_init_data rk806_init_data[] = {
+static struct regulator_init_data  rk806_init_data[] = {
   /* Master PMIC */
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
-  //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK4,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK5,  850000),
+  // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK7,  2000000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK8,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK10, 1800000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO2,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO4,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO5,  750000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO1,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO2,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO3,  1200000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO4,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO5,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO6,  1800000),
 
   /* No dual PMICs on this platform */
 };
@@ -51,9 +51,9 @@ SdmmcIoMux (
   )
 {
   /* sdmmc0 iomux (microSD socket) */
-  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
-  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
-  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+  BUS_IOC->GPIO4D_IOMUX_SEL_L  = (0xFFFFUL << 16) | (0x1111); // SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H  = (0x00FFUL << 16) | (0x0011); // SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); // SDMMC_DET
 }
 
 VOID
@@ -63,14 +63,14 @@ SdhciEmmcIoMux (
   )
 {
   /* sdmmc0 iomux */
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); // EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
 }
 
-#define NS_CRU_BASE         0xFD7C0000
-#define CRU_CLKSEL_CON59    0x03EC
-#define CRU_CLKSEL_CON78    0x0438
+#define NS_CRU_BASE       0xFD7C0000
+#define CRU_CLKSEL_CON59  0x03EC
+#define CRU_CLKSEL_CON78  0x0438
 
 VOID
 EFIAPI
@@ -79,11 +79,11 @@ Rk806SpiIomux (
   )
 {
   /* io mux */
-  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
-  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  // BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  // BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
   PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
   PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+  MmioWrite32 (NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
 }
 
 VOID
@@ -92,24 +92,27 @@ Rk806Configure (
   VOID
   )
 {
-  UINTN RegCfgIndex;
+  UINTN  RegCfgIndex;
 
-  RK806Init();
+  RK806Init ();
 
-  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
-    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
+    RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
+  }
 }
 
 VOID
 EFIAPI
 SetCPULittleVoltage (
-  IN UINT32 Microvolts
+  IN UINT32  Microvolts
   )
 {
-  struct regulator_init_data Rk806CpuLittleSupply =
-        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+  struct regulator_init_data  Rk806CpuLittleSupply =
+    RK8XX_VOLTAGE_INIT (MASTER_BUCK2, Microvolts);
 
-  RK806RegulatorInit(Rk806CpuLittleSupply);
+  RK806RegulatorInit (Rk806CpuLittleSupply);
 }
 
 VOID
@@ -119,31 +122,33 @@ NorFspiIomux (
   )
 {
   /* io mux */
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
-             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
-#define FSPI_M1
-#if defined(FSPI_M0)
-   /*FSPI M0*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
-#elif defined(FSPI_M1)
+  MmioWrite32 (
+    NS_CRU_BASE + CRU_CLKSEL_CON78,
+    (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)
+    );
+  #define FSPI_M1
+ #if defined (FSPI_M0)
+  /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0);   // FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222);     // FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); // FSPI_CS0N_M0
+ #elif defined (FSPI_M1)
   /*FSPI M1*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
-#else
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); // FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); // FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3);         // FSPI_CS0N_M1
+ #else
   /*FSPI M2*/
-  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
-  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
-  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
-#endif
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); // [FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50);     // FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2);         // FSPI_CS0_M2
+ #endif
 }
 
 VOID
 EFIAPI
 GmacIomux (
-  IN UINT32 Id
+  IN UINT32  Id
   )
 {
   /* No GMAC here */
@@ -152,49 +157,49 @@ GmacIomux (
 VOID
 EFIAPI
 NorFspiEnableClock (
-  UINT32 *CruBase
+  UINT32  *CruBase
   )
 {
-  UINTN BaseAddr = (UINTN) CruBase;
+  UINTN  BaseAddr = (UINTN)CruBase;
 
-  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+  MmioWrite32 (BaseAddr + 0x087C, 0x0E000000);
 }
 
 VOID
 EFIAPI
 I2cIomux (
-   UINT32 id
+  UINT32  id
   )
 {
   switch (id) {
-  case 0:
-    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
-    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
-    break;
-  case 1:
-    GpioPinSetFunction(0, GPIO_PIN_PD4, 9); //i2c1_scl_m2
-    GpioPinSetFunction(0, GPIO_PIN_PD5, 9); //i2c1_sda_m2
-    break;
-  case 2:
-    break;
-  case 3:
-    GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0
-    GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0
-    break;
-  case 4:
-    break;
-  case 5:
-    break;
-  case 6:
-    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
-    break;
-  case 7:
-    GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0
-    GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0
-    break;
-  default:
-    break;
+    case 0:
+      GpioPinSetFunction (0, GPIO_PIN_PD1, 3); // i2c0_scl_m2
+      GpioPinSetFunction (0, GPIO_PIN_PD2, 3); // i2c0_sda_m2
+      break;
+    case 1:
+      GpioPinSetFunction (0, GPIO_PIN_PD4, 9); // i2c1_scl_m2
+      GpioPinSetFunction (0, GPIO_PIN_PD5, 9); // i2c1_sda_m2
+      break;
+    case 2:
+      break;
+    case 3:
+      GpioPinSetFunction (1, GPIO_PIN_PC1, 9); // i2c3_scl_m0
+      GpioPinSetFunction (1, GPIO_PIN_PC0, 9); // i2c3_sda_m0
+      break;
+    case 4:
+      break;
+    case 5:
+      break;
+    case 6:
+      GpioPinSetFunction (0, GPIO_PIN_PD0, 9); // i2c6_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC7, 9); // i2c6_sda_m0
+      break;
+    case 7:
+      GpioPinSetFunction (1, GPIO_PIN_PD0, 9); // i2c7_scl_m0
+      GpioPinSetFunction (1, GPIO_PIN_PD1, 9); // i2c7_sda_m0
+      break;
+    default:
+      break;
   }
 }
 
@@ -204,7 +209,7 @@ UsbPortPowerEnable (
   VOID
   )
 {
-  DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n"));
+  DEBUG ((DEBUG_INFO, "UsbPortPowerEnable called\n"));
 
   /* vcc5v0_host_en */
   GpioPinWrite (3, GPIO_PIN_PB7, TRUE);
@@ -221,22 +226,22 @@ Usb2PhyResume (
   VOID
   )
 {
-  MmioWrite32(0xfd5d0008, 0x20000000);
-  MmioWrite32(0xfd5d4008, 0x20000000);
-  MmioWrite32(0xfd5d8008, 0x20000000);
-  MmioWrite32(0xfd5dc008, 0x20000000);
-  MmioWrite32(0xfd7f0a10, 0x07000700);
-  MmioWrite32(0xfd7f0a10, 0x07000000);
+  MmioWrite32 (0xfd5d0008, 0x20000000);
+  MmioWrite32 (0xfd5d4008, 0x20000000);
+  MmioWrite32 (0xfd5d8008, 0x20000000);
+  MmioWrite32 (0xfd5dc008, 0x20000000);
+  MmioWrite32 (0xfd7f0a10, 0x07000700);
+  MmioWrite32 (0xfd7f0a10, 0x07000000);
 }
 
 VOID
 EFIAPI
 PcieIoInit (
-  UINT32 Segment
+  UINT32  Segment
   )
 {
   /* Set reset and power IO to gpio output mode */
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4: // M.2 M Key
       /* reset */
       GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
@@ -260,7 +265,8 @@ PcieIoInit (
     default:
       break;
   }
-  if (Segment == PCIE_SEGMENT_PCIE20L1 || Segment == PCIE_SEGMENT_PCIE20L2) {
+
+  if ((Segment == PCIE_SEGMENT_PCIE20L1) || (Segment == PCIE_SEGMENT_PCIE20L2)) {
     /* vcc3v3_pcie_eth */
     GpioPinSetDirection (3, GPIO_PIN_PB4, GPIO_PIN_OUTPUT);
   }
@@ -269,11 +275,11 @@ PcieIoInit (
 VOID
 EFIAPI
 PciePowerEn (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4:
       GpioPinWrite (2, GPIO_PIN_PB6, Enable);
       break;
@@ -293,11 +299,11 @@ PciePowerEn (
 VOID
 EFIAPI
 PciePeReset (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4:
       GpioPinWrite (4, GPIO_PIN_PB6, !Enable);
       break;
@@ -315,12 +321,42 @@ PciePeReset (
   }
 }
 
-PWM_DATA pwm_data = {
+VOID
+EFIAPI
+HdmiTxIomux (
+  IN UINT32  Id
+  )
+{
+  switch (Id) {
+    case 0:
+      GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
+      GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
+      GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
+      GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
+      break;
+    case 1:
+      GpioPinSetFunction (3, GPIO_PIN_PC4, 5); // hdmim2_tx1_cec
+      GpioPinSetPull (3, GPIO_PIN_PC4, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA6, 5); // hdmim0_tx1_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA6, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (3, GPIO_PIN_PC6, 5); // hdmim1_tx1_scl
+      GpioPinSetPull (3, GPIO_PIN_PC6, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (3, GPIO_PIN_PC5, 5); // hdmim1_tx1_sda
+      GpioPinSetPull (3, GPIO_PIN_PC5, GPIO_PIN_PULL_NONE);
+      break;
+  }
+}
+
+PWM_DATA  pwm_data = {
   .ControllerID = PWM_CONTROLLER0,
-  .ChannelID = PWM_CHANNEL3,
-  .PeriodNs = 4000000,
-  .DutyNs = 4000000,
-  .Polarity = FALSE,
+  .ChannelID    = PWM_CHANNEL3,
+  .PeriodNs     = 4000000,
+  .DutyNs       = 4000000,
+  .Polarity     = FALSE,
 }; // PWM0_CH3
 
 VOID
@@ -337,7 +373,7 @@ PwmFanIoSetup (
 VOID
 EFIAPI
 PwmFanSetSpeed (
-  IN UINT32 Percentage
+  IN UINT32  Percentage
   )
 {
   pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100;
@@ -358,7 +394,7 @@ PlatformInitLeds (
 VOID
 EFIAPI
 PlatformSetStatusLed (
-  IN BOOLEAN Enable
+  IN BOOLEAN  Enable
   )
 {
   GpioPinWrite (3, GPIO_PIN_PA6, Enable);
@@ -367,7 +403,7 @@ PlatformSetStatusLed (
 VOID
 EFIAPI
 PlatformWiFiEnable (
-  IN BOOLEAN Enable
+  IN BOOLEAN  Enable
   )
 {
   // WiFi - enable
@@ -378,13 +414,15 @@ PlatformWiFiEnable (
 CONST EFI_GUID *
 EFIAPI
 PlatformGetDtbFileGuid (
-  IN UINT32 CompatMode
+  IN UINT32  CompatMode
   )
 {
-  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+  STATIC CONST EFI_GUID  VendorDtbFileGuid = {
+    // DeviceTree/Vendor.inf
     0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
   };
-  STATIC CONST EFI_GUID MainlineDtbFileGuid = {       // DeviceTree/Mainline.inf
+  STATIC CONST EFI_GUID  MainlineDtbFileGuid = {
+    // DeviceTree/Mainline.inf
     0x84492e97, 0xa10f, 0x49a7, { 0x85, 0xe9, 0x02, 0x5d, 0x19, 0x66, 0xb3, 0x43 }
   };
 
@@ -407,5 +445,5 @@ PlatformEarlyInit (
   // Configure various things specific to this platform
   PlatformWiFiEnable (TRUE);
 
-  GpioPinSetFunction(1, GPIO_PIN_PD3, 0); //jdet
+  GpioPinSetFunction (1, GPIO_PIN_PD3, 0); // jdet
 }

edk2-rockchip/Platform/OrangePi/OrangePi5Plus/OrangePi5Plus.dsc

@@ -27,6 +27,9 @@
   FLASH_DEFINITION               = Silicon/Rockchip/RK3588/RK3588.fdf
   RK_PLATFORM_FVMAIN_MODULES     = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc
 
+  # GMAC is not exposed
+  DEFINE RK3588_GMAC_ENABLE = FALSE
+
   #
   # HYM8563 RTC support
   # I2C location configured by PCDs below.
@@ -71,13 +74,6 @@
   gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
   gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6
 
-  #
-  # CPU Performance default values
-  #
-  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-
   #
   # PCIe/SATA/USB Combo PIPE PHY support flags and default values
   #
@@ -106,6 +102,15 @@
   #
   gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
 
+  #
+  # Display support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
+    VOP_OUTPUT_IF_HDMI0,
+    VOP_OUTPUT_IF_HDMI1,
+    VOP_OUTPUT_IF_DP0
+  })}
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.

edk2-rockchip/Platform/Radxa/Drivers/LogoDxe/Logo.c

@@ -19,15 +19,15 @@
 #include <Library/DebugLib.h>
 
 typedef struct {
-  EFI_IMAGE_ID                          ImageId;
-  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
-  INTN                                  OffsetX;
-  INTN                                  OffsetY;
+  EFI_IMAGE_ID                             ImageId;
+  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE    Attribute;
+  INTN                                     OffsetX;
+  INTN                                     OffsetY;
 } LOGO_ENTRY;
 
-STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
-STATIC EFI_HII_HANDLE            mHiiHandle;
-STATIC LOGO_ENTRY                mLogos[] = {
+STATIC EFI_HII_IMAGE_EX_PROTOCOL  *mHiiImageEx;
+STATIC EFI_HII_HANDLE             mHiiHandle;
+STATIC LOGO_ENTRY                 mLogos[] = {
   {
     IMAGE_TOKEN (IMG_LOGO),
     EdkiiPlatformLogoDisplayAttributeCenter,
@@ -53,18 +53,19 @@ STATIC
 EFI_STATUS
 EFIAPI
 GetImage (
-  IN     EDKII_PLATFORM_LOGO_PROTOCOL          *This,
-  IN OUT UINT32                                *Instance,
-     OUT EFI_IMAGE_INPUT                       *Image,
-     OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
-     OUT INTN                                  *OffsetX,
-     OUT INTN                                  *OffsetY
+  IN     EDKII_PLATFORM_LOGO_PROTOCOL        *This,
+  IN OUT UINT32                              *Instance,
+  OUT EFI_IMAGE_INPUT                        *Image,
+  OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE  *Attribute,
+  OUT INTN                                   *OffsetX,
+  OUT INTN                                   *OffsetY
   )
 {
-  UINT32 Current;
+  UINT32  Current;
 
-  if (Instance == NULL || Image == NULL ||
-      Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
+  if ((Instance == NULL) || (Image == NULL) ||
+      (Attribute == NULL) || (OffsetX == NULL) || (OffsetY == NULL))
+  {
     return EFI_INVALID_PARAMETER;
   }
 
@@ -78,11 +79,15 @@ GetImage (
   *OffsetX   = mLogos[Current].OffsetX;
   *OffsetY   = mLogos[Current].OffsetY;
 
-  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
-                        mLogos[Current].ImageId, Image);
+  return mHiiImageEx->GetImageEx (
+                        mHiiImageEx,
+                        mHiiHandle,
+                        mLogos[Current].ImageId,
+                        Image
+                        );
 }
 
-STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+STATIC EDKII_PLATFORM_LOGO_PROTOCOL  mPlatformLogo = {
   GetImage
 };
 
@@ -101,44 +106,66 @@ STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
 EFI_STATUS
 EFIAPI
 InitializeLogo (
-  IN EFI_HANDLE               ImageHandle,
-  IN EFI_SYSTEM_TABLE         *SystemTable
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
-  EFI_STATUS                  Status;
-  EFI_HII_PACKAGE_LIST_HEADER *PackageList;
-  EFI_HII_DATABASE_PROTOCOL   *HiiDatabase;
-  EFI_HANDLE                  Handle;
+  EFI_STATUS                   Status;
+  EFI_HII_PACKAGE_LIST_HEADER  *PackageList;
+  EFI_HII_DATABASE_PROTOCOL    *HiiDatabase;
+  EFI_HANDLE                   Handle;
 
-  Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
-                  (VOID **) &HiiDatabase);
+  Status = gBS->LocateProtocol (
+                  &gEfiHiiDatabaseProtocolGuid,
+                  NULL,
+                  (VOID **)&HiiDatabase
+                  );
   ASSERT_EFI_ERROR (Status);
 
-  Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
-                  (VOID **) &mHiiImageEx);
+  Status = gBS->LocateProtocol (
+                  &gEfiHiiImageExProtocolGuid,
+                  NULL,
+                  (VOID **)&mHiiImageEx
+                  );
   ASSERT_EFI_ERROR (Status);
 
   //
   // Retrieve HII package list from ImageHandle
   //
-  Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
-                  (VOID **) &PackageList, ImageHandle, NULL,
-                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+  Status = gBS->OpenProtocol (
+                  ImageHandle,
+                  &gEfiHiiPackageListProtocolGuid,
+                  (VOID **)&PackageList,
+                  ImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
   if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR,
-      "HII Image Package with logo not found in PE/COFF resource section\n"));
+    DEBUG ((
+      DEBUG_ERROR,
+      "HII Image Package with logo not found in PE/COFF resource section\n"
+      ));
     return Status;
   }
 
   //
   // Publish HII package list to HII Database.
   //
-  Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
-                          &mHiiHandle);
+  Status = HiiDatabase->NewPackageList (
+                          HiiDatabase,
+                          PackageList,
+                          NULL,
+                          &mHiiHandle
+                          );
   if (!EFI_ERROR (Status)) {
     Handle = NULL;
-    Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
-                    &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
+    Status = gBS->InstallMultipleProtocolInterfaces (
+                    &Handle,
+                    &gEdkiiPlatformLogoProtocolGuid,
+                    &mPlatformLogo,
+                    NULL
+                    );
   }
+
   return Status;
 }

edk2-rockchip/Platform/Radxa/ROCK5A/DeviceTree/Mainline.inf

@@ -14,7 +14,7 @@
   VERSION_STRING                 = 1.0
 
 [Sources]
-  devicetree/mainline/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
+  devicetree/mainline/rk3588s-rock-5a-fixup.dts
 
 [Packages]
   MdePkg/MdePkg.dec

edk2-rockchip/Platform/Radxa/ROCK5A/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -17,29 +17,29 @@
 #include <Soc.h>
 #include <VarStoreData.h>
 
-static struct regulator_init_data rk806_init_data[] = {
+static struct regulator_init_data  rk806_init_data[] = {
   /* Master PMIC */
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
-  //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK4,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK5,  850000),
+  // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK7,  2000000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK8,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK10, 1800000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO2,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO4,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO5,  750000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO1,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO2,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO3,  1200000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO4,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO5,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO6,  1800000),
   /* No dual PMICs on this platform */
 };
 
@@ -50,9 +50,9 @@ SdmmcIoMux (
   )
 {
   /* sdmmc0 iomux (microSD socket) */
-  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
-  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
-  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+  BUS_IOC->GPIO4D_IOMUX_SEL_L  = (0xFFFFUL << 16) | (0x1111); // SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H  = (0x00FFUL << 16) | (0x0011); // SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); // SDMMC_DET
 }
 
 VOID
@@ -65,9 +65,9 @@ SdhciEmmcIoMux (
   /* Do not override, set by earlier boot stages. */
 }
 
-#define NS_CRU_BASE         0xFD7C0000
-#define CRU_CLKSEL_CON59    0x03EC
-#define CRU_CLKSEL_CON78    0x0438
+#define NS_CRU_BASE       0xFD7C0000
+#define CRU_CLKSEL_CON59  0x03EC
+#define CRU_CLKSEL_CON78  0x0438
 
 VOID
 EFIAPI
@@ -76,11 +76,11 @@ Rk806SpiIomux (
   )
 {
   /* io mux */
-  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
-  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  // BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  // BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
   PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
   PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+  MmioWrite32 (NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
 }
 
 VOID
@@ -89,24 +89,27 @@ Rk806Configure (
   VOID
   )
 {
-  UINTN RegCfgIndex;
+  UINTN  RegCfgIndex;
 
-  RK806Init();
+  RK806Init ();
 
-  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
-    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
+    RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
+  }
 }
 
 VOID
 EFIAPI
 SetCPULittleVoltage (
-  IN UINT32 Microvolts
+  IN UINT32  Microvolts
   )
 {
-  struct regulator_init_data Rk806CpuLittleSupply =
-        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+  struct regulator_init_data  Rk806CpuLittleSupply =
+    RK8XX_VOLTAGE_INIT (MASTER_BUCK2, Microvolts);
 
-  RK806RegulatorInit(Rk806CpuLittleSupply);
+  RK806RegulatorInit (Rk806CpuLittleSupply);
 }
 
 VOID
@@ -122,7 +125,7 @@ NorFspiIomux (
 VOID
 EFIAPI
 GmacIomux (
-  IN UINT32 Id
+  IN UINT32  Id
   )
 {
   switch (Id) {
@@ -162,45 +165,45 @@ GmacIoPhyReset (
 VOID
 EFIAPI
 NorFspiEnableClock (
-  UINT32 *CruBase
+  UINT32  *CruBase
   )
 {
-  UINTN BaseAddr = (UINTN) CruBase;
+  UINTN  BaseAddr = (UINTN)CruBase;
 
-  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+  MmioWrite32 (BaseAddr + 0x087C, 0x0E000000);
 }
 
 VOID
 EFIAPI
 I2cIomux (
-   UINT32 id
+  UINT32  id
   )
 {
   switch (id) {
-  case 0:
-    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
-    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
-    break;
-  case 1:
-    break;
-  case 2:
-    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
-    break;
-  case 3:
-    break;
-  case 4:
-    break;
-  case 5:
-    break;
-  case 6:
-    break;
-  case 7:
-    GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0
-    GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0
-    break;
-  default:
-    break;
+    case 0:
+      GpioPinSetFunction (0, GPIO_PIN_PD1, 3); // i2c0_scl_m2
+      GpioPinSetFunction (0, GPIO_PIN_PD2, 3); // i2c0_sda_m2
+      break;
+    case 1:
+      break;
+    case 2:
+      GpioPinSetFunction (0, GPIO_PIN_PB7, 9); // i2c2_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC0, 9); // i2c2_sda_m0
+      break;
+    case 3:
+      break;
+    case 4:
+      break;
+    case 5:
+      break;
+    case 6:
+      break;
+    case 7:
+      GpioPinSetFunction (1, GPIO_PIN_PD0, 9); // i2c7_scl_m0
+      GpioPinSetFunction (1, GPIO_PIN_PD1, 9); // i2c7_sda_m0
+      break;
+    default:
+      break;
   }
 }
 
@@ -210,7 +213,7 @@ UsbPortPowerEnable (
   VOID
   )
 {
-  DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n"));
+  DEBUG ((DEBUG_INFO, "UsbPortPowerEnable called\n"));
 
   /* vcc5v0_host */
   GpioPinSetDirection (4, GPIO_PIN_PB5, GPIO_PIN_OUTPUT);
@@ -227,21 +230,21 @@ Usb2PhyResume (
   VOID
   )
 {
-  MmioWrite32(0xfd5d0008, 0x20000000);
-  MmioWrite32(0xfd5d4008, 0x20000000);
-  MmioWrite32(0xfd5d8008, 0x20000000);
-  MmioWrite32(0xfd5dc008, 0x20000000);
-  MmioWrite32(0xfd7f0a10, 0x07000700);
-  MmioWrite32(0xfd7f0a10, 0x07000000);
+  MmioWrite32 (0xfd5d0008, 0x20000000);
+  MmioWrite32 (0xfd5d4008, 0x20000000);
+  MmioWrite32 (0xfd5d8008, 0x20000000);
+  MmioWrite32 (0xfd5dc008, 0x20000000);
+  MmioWrite32 (0xfd7f0a10, 0x07000700);
+  MmioWrite32 (0xfd7f0a10, 0x07000000);
 }
 
 VOID
 EFIAPI
 PcieIoInit (
-  UINT32 Segment
+  UINT32  Segment
   )
 {
-  if(Segment == PCIE_SEGMENT_PCIE20L2) {
+  if (Segment == PCIE_SEGMENT_PCIE20L2) {
     // Set reset and power IO to gpio output mode
     GpioPinSetDirection (0, GPIO_PIN_PC5, GPIO_PIN_OUTPUT);
     GpioPinSetDirection (3, GPIO_PIN_PD1, GPIO_PIN_OUTPUT);
@@ -251,11 +254,11 @@ PcieIoInit (
 VOID
 EFIAPI
 PciePowerEn (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  if(Segment == PCIE_SEGMENT_PCIE20L2) {
+  if (Segment == PCIE_SEGMENT_PCIE20L2) {
     /* output high to enable power */
     GpioPinWrite (0, GPIO_PIN_PC5, Enable);
   }
@@ -264,21 +267,41 @@ PciePowerEn (
 VOID
 EFIAPI
 PciePeReset (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  if(Segment == PCIE_SEGMENT_PCIE20L2) {
+  if (Segment == PCIE_SEGMENT_PCIE20L2) {
     GpioPinWrite (3, GPIO_PIN_PD1, !Enable);
   }
 }
 
-PWM_DATA pwm_data = {
+VOID
+EFIAPI
+HdmiTxIomux (
+  IN UINT32  Id
+  )
+{
+  switch (Id) {
+    case 0:
+      GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
+      GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (3, GPIO_PIN_PD4, 3); // hdmim1_tx0_hpd
+      GpioPinSetPull (3, GPIO_PIN_PD4, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
+      GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
+      GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
+      break;
+  }
+}
+
+PWM_DATA  pwm_data = {
   .ControllerID = PWM_CONTROLLER0,
-  .ChannelID = PWM_CHANNEL3,
-  .PeriodNs = 4000000,
-  .DutyNs = 4000000,
-  .Polarity = FALSE,
+  .ChannelID    = PWM_CHANNEL3,
+  .PeriodNs     = 4000000,
+  .DutyNs       = 4000000,
+  .Polarity     = FALSE,
 }; // PWM0_CH3
 
 VOID
@@ -295,7 +318,7 @@ PwmFanIoSetup (
 VOID
 EFIAPI
 PwmFanSetSpeed (
-  IN UINT32 Percentage
+  IN UINT32  Percentage
   )
 {
   pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100;
@@ -316,7 +339,7 @@ PlatformInitLeds (
 VOID
 EFIAPI
 PlatformSetStatusLed (
-  IN BOOLEAN Enable
+  IN BOOLEAN  Enable
   )
 {
   GpioPinWrite (3, GPIO_PIN_PD5, Enable);
@@ -325,13 +348,15 @@ PlatformSetStatusLed (
 CONST EFI_GUID *
 EFIAPI
 PlatformGetDtbFileGuid (
-  IN UINT32 CompatMode
+  IN UINT32  CompatMode
   )
 {
-  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+  STATIC CONST EFI_GUID  VendorDtbFileGuid = {
+    // DeviceTree/Vendor.inf
     0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
   };
-  STATIC CONST EFI_GUID MainlineDtbFileGuid = {       // DeviceTree/Mainline.inf
+  STATIC CONST EFI_GUID  MainlineDtbFileGuid = {
+    // DeviceTree/Mainline.inf
     0x84492e97, 0xa10f, 0x49a7, { 0x85, 0xe9, 0x02, 0x5d, 0x19, 0x66, 0xb3, 0x43 }
   };
 
@@ -352,5 +377,5 @@ PlatformEarlyInit (
   )
 {
   // Configure various things specific to this platform
-  GpioPinSetFunction(1, GPIO_PIN_PC4, 0); //jdet
+  GpioPinSetFunction (1, GPIO_PIN_PC4, 0); // jdet
 }

edk2-rockchip/Platform/Radxa/ROCK5A/ROCK5A.dsc

@@ -64,13 +64,6 @@
   gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 }
   gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) }
 
-  #
-  # CPU Performance default values
-  #
-  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-
   #
   # PCIe/SATA/USB Combo PIPE PHY support flags and default values
   #
@@ -102,6 +95,14 @@
   #
   gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
 
+  #
+  # Display support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
+    VOP_OUTPUT_IF_HDMI0,
+    VOP_OUTPUT_IF_DP0
+  })}
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.

edk2-rockchip/Platform/Radxa/ROCK5B/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -17,29 +17,29 @@
 #include <Soc.h>
 #include <VarStoreData.h>
 
-static struct regulator_init_data rk806_init_data[] = {
+static struct regulator_init_data  rk806_init_data[] = {
   /* Master PMIC */
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
-  //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK4,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK5,  850000),
+  // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK7,  2000000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK8,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK10, 1800000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO2,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO4,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO5,  750000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO1,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO2,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO3,  1200000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO4,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO5,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO6,  1800000),
 
   /* No dual PMICs on this platform */
 };
@@ -51,9 +51,9 @@ SdmmcIoMux (
   )
 {
   /* sdmmc0 iomux (microSD socket) */
-  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
-  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
-  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+  BUS_IOC->GPIO4D_IOMUX_SEL_L  = (0xFFFFUL << 16) | (0x1111); // SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H  = (0x00FFUL << 16) | (0x0011); // SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); // SDMMC_DET
 }
 
 VOID
@@ -63,14 +63,14 @@ SdhciEmmcIoMux (
   )
 {
   /* sdhci0 iomux (eMMC socket) */
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); // EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
 }
 
-#define NS_CRU_BASE         0xFD7C0000
-#define CRU_CLKSEL_CON59    0x03EC
-#define CRU_CLKSEL_CON78    0x0438
+#define NS_CRU_BASE       0xFD7C0000
+#define CRU_CLKSEL_CON59  0x03EC
+#define CRU_CLKSEL_CON78  0x0438
 
 VOID
 EFIAPI
@@ -79,11 +79,11 @@ Rk806SpiIomux (
   )
 {
   /* io mux */
-  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
-  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  // BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  // BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
   PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
   PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+  MmioWrite32 (NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
 }
 
 VOID
@@ -92,24 +92,27 @@ Rk806Configure (
   VOID
   )
 {
-  UINTN RegCfgIndex;
+  UINTN  RegCfgIndex;
 
-  RK806Init();
+  RK806Init ();
 
-  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
-    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
+    RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
+  }
 }
 
 VOID
 EFIAPI
 SetCPULittleVoltage (
-  IN UINT32 Microvolts
+  IN UINT32  Microvolts
   )
 {
-  struct regulator_init_data Rk806CpuLittleSupply =
-        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+  struct regulator_init_data  Rk806CpuLittleSupply =
+    RK8XX_VOLTAGE_INIT (MASTER_BUCK2, Microvolts);
 
-  RK806RegulatorInit(Rk806CpuLittleSupply);
+  RK806RegulatorInit (Rk806CpuLittleSupply);
 }
 
 VOID
@@ -119,31 +122,33 @@ NorFspiIomux (
   )
 {
   /* io mux */
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
-             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
-#define FSPI_M1
-#if defined(FSPI_M0)
-   /*FSPI M0*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
-#elif defined(FSPI_M1)
+  MmioWrite32 (
+    NS_CRU_BASE + CRU_CLKSEL_CON78,
+    (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)
+    );
+  #define FSPI_M1
+ #if defined (FSPI_M0)
+  /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0);   // FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222);     // FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); // FSPI_CS0N_M0
+ #elif defined (FSPI_M1)
   /*FSPI M1*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
-#else
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); // FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); // FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3);         // FSPI_CS0N_M1
+ #else
   /*FSPI M2*/
-  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
-  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
-  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
-#endif
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); // [FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50);     // FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2);         // FSPI_CS0_M2
+ #endif
 }
 
 VOID
 EFIAPI
 GmacIomux (
-  IN UINT32 Id
+  IN UINT32  Id
   )
 {
   /* No GMAC here */
@@ -152,49 +157,49 @@ GmacIomux (
 VOID
 EFIAPI
 NorFspiEnableClock (
-  UINT32 *CruBase
+  UINT32  *CruBase
   )
 {
-  UINTN BaseAddr = (UINTN) CruBase;
+  UINTN  BaseAddr = (UINTN)CruBase;
 
-  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+  MmioWrite32 (BaseAddr + 0x087C, 0x0E000000);
 }
 
 VOID
 EFIAPI
 I2cIomux (
-   UINT32 id
+  UINT32  id
   )
 {
   switch (id) {
-  case 0:
-    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
-    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
-    break;
-  case 1:
-    GpioPinSetFunction(0, GPIO_PIN_PD4, 9); //i2c1_scl_m2
-    GpioPinSetFunction(0, GPIO_PIN_PD5, 9); //i2c1_sda_m2
-    break;
-  case 2:
-    break;
-  case 3:
-    break;
-  case 4:
-    GpioPinSetFunction(2, GPIO_PIN_PB5, 9); //i2c4_scl_m1
-    GpioPinSetFunction(2, GPIO_PIN_PB4, 9); //i2c4_sda_m1
-    break;
-  case 5:
-    break;
-  case 6:
-    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
-    break;
-  case 7:
-    GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0
-    GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0
-    break;
-  default:
-    break;
+    case 0:
+      GpioPinSetFunction (0, GPIO_PIN_PD1, 3); // i2c0_scl_m2
+      GpioPinSetFunction (0, GPIO_PIN_PD2, 3); // i2c0_sda_m2
+      break;
+    case 1:
+      GpioPinSetFunction (0, GPIO_PIN_PD4, 9); // i2c1_scl_m2
+      GpioPinSetFunction (0, GPIO_PIN_PD5, 9); // i2c1_sda_m2
+      break;
+    case 2:
+      break;
+    case 3:
+      break;
+    case 4:
+      GpioPinSetFunction (2, GPIO_PIN_PB5, 9); // i2c4_scl_m1
+      GpioPinSetFunction (2, GPIO_PIN_PB4, 9); // i2c4_sda_m1
+      break;
+    case 5:
+      break;
+    case 6:
+      GpioPinSetFunction (0, GPIO_PIN_PD0, 9); // i2c6_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC7, 9); // i2c6_sda_m0
+      break;
+    case 7:
+      GpioPinSetFunction (1, GPIO_PIN_PD0, 9); // i2c7_scl_m0
+      GpioPinSetFunction (1, GPIO_PIN_PD1, 9); // i2c7_sda_m0
+      break;
+    default:
+      break;
   }
 }
 
@@ -204,7 +209,7 @@ UsbPortPowerEnable (
   VOID
   )
 {
-  DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n"));
+  DEBUG ((DEBUG_INFO, "UsbPortPowerEnable called\n"));
   /* Set GPIO4 PB0 (USB_HOST_PWREN) output high to power USB ports */
   GpioPinWrite (4, GPIO_PIN_PB0, TRUE);
   GpioPinSetDirection (4, GPIO_PIN_PB0, GPIO_PIN_OUTPUT);
@@ -220,22 +225,22 @@ Usb2PhyResume (
   VOID
   )
 {
-  MmioWrite32(0xfd5d0008, 0x20000000);
-  MmioWrite32(0xfd5d4008, 0x20000000);
-  MmioWrite32(0xfd5d8008, 0x20000000);
-  MmioWrite32(0xfd5dc008, 0x20000000);
-  MmioWrite32(0xfd7f0a10, 0x07000700);
-  MmioWrite32(0xfd7f0a10, 0x07000000);
+  MmioWrite32 (0xfd5d0008, 0x20000000);
+  MmioWrite32 (0xfd5d4008, 0x20000000);
+  MmioWrite32 (0xfd5d8008, 0x20000000);
+  MmioWrite32 (0xfd5dc008, 0x20000000);
+  MmioWrite32 (0xfd7f0a10, 0x07000700);
+  MmioWrite32 (0xfd7f0a10, 0x07000000);
 }
 
 VOID
 EFIAPI
 PcieIoInit (
-  UINT32 Segment
+  UINT32  Segment
   )
 {
   /* Set reset and power IO to gpio output mode */
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4:
       GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
       GpioPinSetDirection (1, GPIO_PIN_PA4, GPIO_PIN_OUTPUT);
@@ -260,13 +265,13 @@ PcieIoInit (
 VOID
 EFIAPI
 PciePowerEn (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
   /* output high to enable power */
 
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4:
       GpioPinWrite (1, GPIO_PIN_PA4, Enable);
       break;
@@ -285,11 +290,11 @@ PciePowerEn (
 VOID
 EFIAPI
 PciePeReset (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4:
       GpioPinWrite (4, GPIO_PIN_PB6, !Enable);
       break;
@@ -306,12 +311,42 @@ PciePeReset (
   }
 }
 
-PWM_DATA pwm_data = {
+VOID
+EFIAPI
+HdmiTxIomux (
+  IN UINT32  Id
+  )
+{
+  switch (Id) {
+    case 0:
+      GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
+      GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
+      GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
+      GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
+      break;
+    case 1:
+      GpioPinSetFunction (2, GPIO_PIN_PC4, 4); // hdmim0_tx1_cec
+      GpioPinSetPull (2, GPIO_PIN_PC4, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA6, 5); // hdmim0_tx1_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA6, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (3, GPIO_PIN_PC6, 5); // hdmim1_tx1_scl
+      GpioPinSetPull (3, GPIO_PIN_PC6, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (3, GPIO_PIN_PC5, 5); // hdmim1_tx1_sda
+      GpioPinSetPull (3, GPIO_PIN_PC5, GPIO_PIN_PULL_NONE);
+      break;
+  }
+}
+
+PWM_DATA  pwm_data = {
   .ControllerID = PWM_CONTROLLER0,
-  .ChannelID = PWM_CHANNEL1,
-  .PeriodNs = 4000000,
-  .DutyNs = 4000000,
-  .Polarity = FALSE,
+  .ChannelID    = PWM_CHANNEL1,
+  .PeriodNs     = 4000000,
+  .DutyNs       = 4000000,
+  .Polarity     = FALSE,
 }; // PWM0_CH1
 
 VOID
@@ -328,7 +363,7 @@ PwmFanIoSetup (
 VOID
 EFIAPI
 PwmFanSetSpeed (
-  IN UINT32 Percentage
+  IN UINT32  Percentage
   )
 {
   pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100;
@@ -349,7 +384,7 @@ PlatformInitLeds (
 VOID
 EFIAPI
 PlatformSetStatusLed (
-  IN BOOLEAN Enable
+  IN BOOLEAN  Enable
   )
 {
   GpioPinWrite (0, GPIO_PIN_PB7, Enable);
@@ -358,7 +393,7 @@ PlatformSetStatusLed (
 VOID
 EFIAPI
 PlatformPcieWiFiEnable (
-  IN BOOLEAN Enable
+  IN BOOLEAN  Enable
   )
 {
   // WiFi - enable
@@ -372,19 +407,20 @@ PlatformPcieWiFiEnable (
   GpioPinSetDirection (3, GPIO_PIN_PD5, GPIO_PIN_OUTPUT);
   GpioPinWrite (3, GPIO_PIN_PA6, Enable);
   GpioPinSetDirection (3, GPIO_PIN_PA6, GPIO_PIN_OUTPUT);
-
 }
 
 CONST EFI_GUID *
 EFIAPI
 PlatformGetDtbFileGuid (
-  IN UINT32 CompatMode
+  IN UINT32  CompatMode
   )
 {
-  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+  STATIC CONST EFI_GUID  VendorDtbFileGuid = {
+    // DeviceTree/Vendor.inf
     0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
   };
-  STATIC CONST EFI_GUID MainlineDtbFileGuid = {       // DeviceTree/Mainline.inf
+  STATIC CONST EFI_GUID  MainlineDtbFileGuid = {
+    // DeviceTree/Mainline.inf
     0x84492e97, 0xa10f, 0x49a7, { 0x85, 0xe9, 0x02, 0x5d, 0x19, 0x66, 0xb3, 0x43 }
   };
 
@@ -405,6 +441,6 @@ PlatformEarlyInit (
   )
 {
   // Configure various things specific to this platform
-  PlatformPcieWiFiEnable(TRUE);
-  GpioPinSetFunction(1, GPIO_PIN_PD5, 0); //jdet
+  PlatformPcieWiFiEnable (TRUE);
+  GpioPinSetFunction (1, GPIO_PIN_PD5, 0); // jdet
 }

edk2-rockchip/Platform/Radxa/ROCK5B/ROCK5B.dsc

@@ -28,6 +28,9 @@
   FLASH_DEFINITION               = Silicon/Rockchip/RK3588/RK3588.fdf
   RK_PLATFORM_FVMAIN_MODULES     = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc
 
+  # GMAC is not exposed
+  DEFINE RK3588_GMAC_ENABLE = FALSE
+
   #
   # HYM8563 RTC support
   # I2C location configured by PCDs below.
@@ -72,13 +75,6 @@
   gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
   gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6
 
-  #
-  # CPU Performance default values
-  #
-  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-
   #
   # PCIe/SATA/USB Combo PIPE PHY support flags and default values
   #
@@ -107,6 +103,15 @@
   #
   gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
 
+  #
+  # Display support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
+    VOP_OUTPUT_IF_HDMI0,
+    VOP_OUTPUT_IF_HDMI1,
+    VOP_OUTPUT_IF_DP0
+  })}
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.

edk2-rockchip/Platform/Radxa/ROCK5BPlus/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -17,29 +17,29 @@
 #include <Soc.h>
 #include <VarStoreData.h>
 
-static struct regulator_init_data rk806_init_data[] = {
+static struct regulator_init_data  rk806_init_data[] = {
   /* Master PMIC */
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
-  //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK4,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK5,  850000),
+  // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK7,  2000000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK8,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK10, 1800000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO2,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO4,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO5,  750000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO1,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO2,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO3,  1200000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO4,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO5,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO6,  1800000),
 
   /* No dual PMICs on this platform */
 };
@@ -51,9 +51,9 @@ SdmmcIoMux (
   )
 {
   /* sdmmc0 iomux (microSD socket) */
-  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
-  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
-  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+  BUS_IOC->GPIO4D_IOMUX_SEL_L  = (0xFFFFUL << 16) | (0x1111); // SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H  = (0x00FFUL << 16) | (0x0011); // SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); // SDMMC_DET
 }
 
 VOID
@@ -63,14 +63,14 @@ SdhciEmmcIoMux (
   )
 {
   /* sdhci0 iomux (eMMC socket) */
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); // EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
 }
 
-#define NS_CRU_BASE         0xFD7C0000
-#define CRU_CLKSEL_CON59    0x03EC
-#define CRU_CLKSEL_CON78    0x0438
+#define NS_CRU_BASE       0xFD7C0000
+#define CRU_CLKSEL_CON59  0x03EC
+#define CRU_CLKSEL_CON78  0x0438
 
 VOID
 EFIAPI
@@ -79,11 +79,11 @@ Rk806SpiIomux (
   )
 {
   /* io mux */
-  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
-  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  // BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  // BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
   PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
   PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+  MmioWrite32 (NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
 }
 
 VOID
@@ -92,24 +92,27 @@ Rk806Configure (
   VOID
   )
 {
-  UINTN RegCfgIndex;
+  UINTN  RegCfgIndex;
 
-  RK806Init();
+  RK806Init ();
 
-  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
-    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
+    RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
+  }
 }
 
 VOID
 EFIAPI
 SetCPULittleVoltage (
-  IN UINT32 Microvolts
+  IN UINT32  Microvolts
   )
 {
-  struct regulator_init_data Rk806CpuLittleSupply =
-        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+  struct regulator_init_data  Rk806CpuLittleSupply =
+    RK8XX_VOLTAGE_INIT (MASTER_BUCK2, Microvolts);
 
-  RK806RegulatorInit(Rk806CpuLittleSupply);
+  RK806RegulatorInit (Rk806CpuLittleSupply);
 }
 
 VOID
@@ -119,31 +122,33 @@ NorFspiIomux (
   )
 {
   /* io mux */
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
-             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
-#define FSPI_M1
-#if defined(FSPI_M0)
-   /*FSPI M0*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
-#elif defined(FSPI_M1)
+  MmioWrite32 (
+    NS_CRU_BASE + CRU_CLKSEL_CON78,
+    (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)
+    );
+  #define FSPI_M1
+ #if defined (FSPI_M0)
+  /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0);   // FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222);     // FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); // FSPI_CS0N_M0
+ #elif defined (FSPI_M1)
   /*FSPI M1*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
-#else
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); // FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); // FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3);         // FSPI_CS0N_M1
+ #else
   /*FSPI M2*/
-  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
-  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
-  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
-#endif
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); // [FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50);     // FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2);         // FSPI_CS0_M2
+ #endif
 }
 
 VOID
 EFIAPI
 GmacIomux (
-  IN UINT32 Id
+  IN UINT32  Id
   )
 {
   /* No GMAC here */
@@ -152,49 +157,49 @@ GmacIomux (
 VOID
 EFIAPI
 NorFspiEnableClock (
-  UINT32 *CruBase
+  UINT32  *CruBase
   )
 {
-  UINTN BaseAddr = (UINTN) CruBase;
+  UINTN  BaseAddr = (UINTN)CruBase;
 
-  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+  MmioWrite32 (BaseAddr + 0x087C, 0x0E000000);
 }
 
 VOID
 EFIAPI
 I2cIomux (
-   UINT32 id
+  UINT32  id
   )
 {
   switch (id) {
-  case 0:
-    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
-    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
-    break;
-  case 1:
-    GpioPinSetFunction(0, GPIO_PIN_PD4, 9); //i2c1_scl_m2
-    GpioPinSetFunction(0, GPIO_PIN_PD5, 9); //i2c1_sda_m2
-    break;
-  case 2:
-    break;
-  case 3:
-    break;
-  case 4:
-    GpioPinSetFunction(2, GPIO_PIN_PB5, 9); //i2c4_scl_m1
-    GpioPinSetFunction(2, GPIO_PIN_PB4, 9); //i2c4_sda_m1
-    break;
-  case 5:
-    break;
-  case 6:
-    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
-    break;
-  case 7:
-    GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0
-    GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0
-    break;
-  default:
-    break;
+    case 0:
+      GpioPinSetFunction (0, GPIO_PIN_PD1, 3); // i2c0_scl_m2
+      GpioPinSetFunction (0, GPIO_PIN_PD2, 3); // i2c0_sda_m2
+      break;
+    case 1:
+      GpioPinSetFunction (0, GPIO_PIN_PD4, 9); // i2c1_scl_m2
+      GpioPinSetFunction (0, GPIO_PIN_PD5, 9); // i2c1_sda_m2
+      break;
+    case 2:
+      break;
+    case 3:
+      break;
+    case 4:
+      GpioPinSetFunction (2, GPIO_PIN_PB5, 9); // i2c4_scl_m1
+      GpioPinSetFunction (2, GPIO_PIN_PB4, 9); // i2c4_sda_m1
+      break;
+    case 5:
+      break;
+    case 6:
+      GpioPinSetFunction (0, GPIO_PIN_PD0, 9); // i2c6_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC7, 9); // i2c6_sda_m0
+      break;
+    case 7:
+      GpioPinSetFunction (1, GPIO_PIN_PD0, 9); // i2c7_scl_m0
+      GpioPinSetFunction (1, GPIO_PIN_PD1, 9); // i2c7_sda_m0
+      break;
+    default:
+      break;
   }
 }
 
@@ -204,7 +209,7 @@ UsbPortPowerEnable (
   VOID
   )
 {
-  DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n"));
+  DEBUG ((DEBUG_INFO, "UsbPortPowerEnable called\n"));
   /* Set GPIO1 PA1 (USB_HOST_PWREN) output high to power USB ports */
   GpioPinWrite (1, GPIO_PIN_PA1, TRUE);
   GpioPinSetDirection (1, GPIO_PIN_PA1, GPIO_PIN_OUTPUT);
@@ -223,22 +228,22 @@ Usb2PhyResume (
   VOID
   )
 {
-  MmioWrite32(0xfd5d0008, 0x20000000);
-  MmioWrite32(0xfd5d4008, 0x20000000);
-  MmioWrite32(0xfd5d8008, 0x20000000);
-  MmioWrite32(0xfd5dc008, 0x20000000);
-  MmioWrite32(0xfd7f0a10, 0x07000700);
-  MmioWrite32(0xfd7f0a10, 0x07000000);
+  MmioWrite32 (0xfd5d0008, 0x20000000);
+  MmioWrite32 (0xfd5d4008, 0x20000000);
+  MmioWrite32 (0xfd5d8008, 0x20000000);
+  MmioWrite32 (0xfd5dc008, 0x20000000);
+  MmioWrite32 (0xfd7f0a10, 0x07000700);
+  MmioWrite32 (0xfd7f0a10, 0x07000000);
 }
 
 VOID
 EFIAPI
 PcieIoInit (
-  UINT32 Segment
+  UINT32  Segment
   )
 {
   /* Set reset and power IO to gpio output mode */
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4:
       GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
       GpioPinSetDirection (1, GPIO_PIN_PA4, GPIO_PIN_OUTPUT);
@@ -268,15 +273,15 @@ PcieIoInit (
 VOID
 EFIAPI
 PciePowerEn (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
   /* output high to enable power */
 
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4:
-      /* fall through */
+    /* fall through */
     case PCIE_SEGMENT_PCIE30X2:
       GpioPinWrite (1, GPIO_PIN_PA4, Enable);
       break;
@@ -295,11 +300,11 @@ PciePowerEn (
 VOID
 EFIAPI
 PciePeReset (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4:
       GpioPinWrite (4, GPIO_PIN_PB6, !Enable);
       break;
@@ -319,12 +324,42 @@ PciePeReset (
   }
 }
 
-PWM_DATA pwm_data = {
+VOID
+EFIAPI
+HdmiTxIomux (
+  IN UINT32  Id
+  )
+{
+  switch (Id) {
+    case 0:
+      GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
+      GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
+      GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
+      GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
+      break;
+    case 1:
+      GpioPinSetFunction (2, GPIO_PIN_PC4, 4); // hdmim0_tx1_cec
+      GpioPinSetPull (2, GPIO_PIN_PC4, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA6, 5); // hdmim0_tx1_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA6, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (3, GPIO_PIN_PC6, 5); // hdmim1_tx1_scl
+      GpioPinSetPull (3, GPIO_PIN_PC6, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (3, GPIO_PIN_PC5, 5); // hdmim1_tx1_sda
+      GpioPinSetPull (3, GPIO_PIN_PC5, GPIO_PIN_PULL_NONE);
+      break;
+  }
+}
+
+PWM_DATA  pwm_data = {
   .ControllerID = PWM_CONTROLLER0,
-  .ChannelID = PWM_CHANNEL1,
-  .PeriodNs = 4000000,
-  .DutyNs = 4000000,
-  .Polarity = FALSE,
+  .ChannelID    = PWM_CHANNEL1,
+  .PeriodNs     = 4000000,
+  .DutyNs       = 4000000,
+  .Polarity     = FALSE,
 }; // PWM0_CH1
 
 VOID
@@ -341,7 +376,7 @@ PwmFanIoSetup (
 VOID
 EFIAPI
 PwmFanSetSpeed (
-  IN UINT32 Percentage
+  IN UINT32  Percentage
   )
 {
   pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100;
@@ -362,7 +397,7 @@ PlatformInitLeds (
 VOID
 EFIAPI
 PlatformSetStatusLed (
-  IN BOOLEAN Enable
+  IN BOOLEAN  Enable
   )
 {
   GpioPinWrite (0, GPIO_PIN_PB7, Enable);
@@ -371,7 +406,7 @@ PlatformSetStatusLed (
 VOID
 EFIAPI
 PlatformPcieWiFiEnable (
-  IN BOOLEAN Enable
+  IN BOOLEAN  Enable
   )
 {
   // WiFi - enable
@@ -383,16 +418,16 @@ PlatformPcieWiFiEnable (
   // bluetooth - enable
   GpioPinWrite (3, GPIO_PIN_PD5, Enable);
   GpioPinSetDirection (3, GPIO_PIN_PD5, GPIO_PIN_OUTPUT);
-
 }
 
 CONST EFI_GUID *
 EFIAPI
 PlatformGetDtbFileGuid (
-  IN UINT32 CompatMode
+  IN UINT32  CompatMode
   )
 {
-  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+  STATIC CONST EFI_GUID  VendorDtbFileGuid = {
+    // DeviceTree/Vendor.inf
     0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
   };
 
@@ -411,6 +446,6 @@ PlatformEarlyInit (
   )
 {
   // Configure various things specific to this platform
-  PlatformPcieWiFiEnable(TRUE);
-  GpioPinSetFunction(1, GPIO_PIN_PD5, 0); //jdet
+  PlatformPcieWiFiEnable (TRUE);
+  GpioPinSetFunction (1, GPIO_PIN_PD5, 0); // jdet
 }

edk2-rockchip/Platform/Radxa/ROCK5BPlus/ROCK5BPlus.dsc

@@ -29,6 +29,9 @@
   FLASH_DEFINITION               = Silicon/Rockchip/RK3588/RK3588.fdf
   RK_PLATFORM_FVMAIN_MODULES     = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc
 
+  # GMAC is not exposed
+  DEFINE RK3588_GMAC_ENABLE = FALSE
+
   #
   # HYM8563 RTC support
   # I2C location configured by PCDs below.
@@ -73,13 +76,6 @@
   gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
   gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6
 
-  #
-  # CPU Performance default values
-  #
-  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-
   #
   # PCIe/SATA/USB Combo PIPE PHY support flags and default values
   #
@@ -111,6 +107,15 @@
   #
   gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
 
+  #
+  # Display support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
+    VOP_OUTPUT_IF_HDMI0,
+    VOP_OUTPUT_IF_HDMI1,
+    VOP_OUTPUT_IF_DP0
+  })}
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.

edk2-rockchip/Platform/Radxa/ROCK5ITX/DeviceTree/Mainline.inf

@@ -14,7 +14,7 @@
   VERSION_STRING                 = 1.0
 
 [Sources]
-  devicetree/mainline/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts
+  devicetree/mainline/rk3588-rock-5-itx-fixup.dts
 
 [Packages]
   MdePkg/MdePkg.dec

edk2-rockchip/Platform/Radxa/ROCK5ITX/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -17,29 +17,29 @@
 #include <Soc.h>
 #include <VarStoreData.h>
 
-static struct regulator_init_data rk806_init_data[] = {
+static struct regulator_init_data  rk806_init_data[] = {
   /* Master PMIC */
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
-  //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK4,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK5,  850000),
+  // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK7,  2000000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK8,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_BUCK10, 1800000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
-  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO1,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO2,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO3,  750000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO4,  850000),
+  RK8XX_VOLTAGE_INIT (MASTER_NLDO5,  750000),
 
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
-  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO1,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO2,  1800000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO3,  1200000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO4,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO5,  3300000),
+  RK8XX_VOLTAGE_INIT (MASTER_PLDO6,  1800000),
 
   /* No dual PMICs on this platform */
 };
@@ -51,9 +51,9 @@ SdmmcIoMux (
   )
 {
   /* sdmmc0 iomux (microSD socket) */
-  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
-  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
-  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+  BUS_IOC->GPIO4D_IOMUX_SEL_L  = (0xFFFFUL << 16) | (0x1111); // SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H  = (0x00FFUL << 16) | (0x0011); // SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); // SDMMC_DET
 }
 
 VOID
@@ -63,14 +63,14 @@ SdhciEmmcIoMux (
   )
 {
   /* sdhci0 iomux (eMMC socket) */
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); // EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); // EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
 }
 
-#define NS_CRU_BASE         0xFD7C0000
-#define CRU_CLKSEL_CON59    0x03EC
-#define CRU_CLKSEL_CON78    0x0438
+#define NS_CRU_BASE       0xFD7C0000
+#define CRU_CLKSEL_CON59  0x03EC
+#define CRU_CLKSEL_CON78  0x0438
 
 VOID
 EFIAPI
@@ -79,11 +79,11 @@ Rk806SpiIomux (
   )
 {
   /* io mux */
-  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
-  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  // BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  // BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
   PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
   PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+  MmioWrite32 (NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
 }
 
 VOID
@@ -92,24 +92,27 @@ Rk806Configure (
   VOID
   )
 {
-  UINTN RegCfgIndex;
+  UINTN  RegCfgIndex;
 
-  RK806Init();
+  RK806Init ();
 
-  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
-    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
+    RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
+  }
 }
 
 VOID
 EFIAPI
 SetCPULittleVoltage (
-  IN UINT32 Microvolts
+  IN UINT32  Microvolts
   )
 {
-  struct regulator_init_data Rk806CpuLittleSupply =
-        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+  struct regulator_init_data  Rk806CpuLittleSupply =
+    RK8XX_VOLTAGE_INIT (MASTER_BUCK2, Microvolts);
 
-  RK806RegulatorInit(Rk806CpuLittleSupply);
+  RK806RegulatorInit (Rk806CpuLittleSupply);
 }
 
 VOID
@@ -119,31 +122,33 @@ NorFspiIomux (
   )
 {
   /* io mux */
-  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
-             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
-#define FSPI_M1
-#if defined(FSPI_M0)
-   /*FSPI M0*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
-  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
-#elif defined(FSPI_M1)
+  MmioWrite32 (
+    NS_CRU_BASE + CRU_CLKSEL_CON78,
+    (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)
+    );
+  #define FSPI_M1
+ #if defined (FSPI_M0)
+  /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0);   // FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222);     // FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); // FSPI_CS0N_M0
+ #elif defined (FSPI_M1)
   /*FSPI M1*/
-  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
-  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
-#else
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); // FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); // FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3);         // FSPI_CS0N_M1
+ #else
   /*FSPI M2*/
-  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
-  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
-  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
-#endif
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); // [FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50);     // FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2);         // FSPI_CS0_M2
+ #endif
 }
 
 VOID
 EFIAPI
 GmacIomux (
-  IN UINT32 Id
+  IN UINT32  Id
   )
 {
   /* No GMAC here */
@@ -152,49 +157,49 @@ GmacIomux (
 VOID
 EFIAPI
 NorFspiEnableClock (
-  UINT32 *CruBase
+  UINT32  *CruBase
   )
 {
-  UINTN BaseAddr = (UINTN) CruBase;
+  UINTN  BaseAddr = (UINTN)CruBase;
 
-  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+  MmioWrite32 (BaseAddr + 0x087C, 0x0E000000);
 }
 
 VOID
 EFIAPI
 I2cIomux (
-   UINT32 id
+  UINT32  id
   )
 {
   switch (id) {
-  case 0:
-    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
-    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
-    break;
-  case 1:
-    GpioPinSetFunction(0, GPIO_PIN_PD4, 9); //i2c1_scl_m2
-    GpioPinSetFunction(0, GPIO_PIN_PD5, 9); //i2c1_sda_m2
-    break;
-  case 2:
-    break;
-  case 3:
-    break;
-  case 4:
-    GpioPinSetFunction(2, GPIO_PIN_PB5, 9); //i2c4_scl_m1
-    GpioPinSetFunction(2, GPIO_PIN_PB4, 9); //i2c4_sda_m1
-    break;
-  case 5:
-    break;
-  case 6:
-    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
-    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
-    break;
-  case 7:
-    GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0
-    GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0
-    break;
-  default:
-    break;
+    case 0:
+      GpioPinSetFunction (0, GPIO_PIN_PD1, 3); // i2c0_scl_m2
+      GpioPinSetFunction (0, GPIO_PIN_PD2, 3); // i2c0_sda_m2
+      break;
+    case 1:
+      GpioPinSetFunction (0, GPIO_PIN_PD4, 9); // i2c1_scl_m2
+      GpioPinSetFunction (0, GPIO_PIN_PD5, 9); // i2c1_sda_m2
+      break;
+    case 2:
+      break;
+    case 3:
+      break;
+    case 4:
+      GpioPinSetFunction (2, GPIO_PIN_PB5, 9); // i2c4_scl_m1
+      GpioPinSetFunction (2, GPIO_PIN_PB4, 9); // i2c4_sda_m1
+      break;
+    case 5:
+      break;
+    case 6:
+      GpioPinSetFunction (0, GPIO_PIN_PD0, 9); // i2c6_scl_m0
+      GpioPinSetFunction (0, GPIO_PIN_PC7, 9); // i2c6_sda_m0
+      break;
+    case 7:
+      GpioPinSetFunction (1, GPIO_PIN_PD0, 9); // i2c7_scl_m0
+      GpioPinSetFunction (1, GPIO_PIN_PD1, 9); // i2c7_sda_m0
+      break;
+    default:
+      break;
   }
 }
 
@@ -204,7 +209,7 @@ UsbPortPowerEnable (
   VOID
   )
 {
-  DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n"));
+  DEBUG ((DEBUG_INFO, "UsbPortPowerEnable called\n"));
   /* Set GPIO4 PB0 (USB_HOST_PWREN) output high to power USB ports */
   GpioPinWrite (3, GPIO_PIN_PB7, TRUE);
   GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT);
@@ -220,27 +225,30 @@ Usb2PhyResume (
   VOID
   )
 {
-  MmioWrite32(0xfd5d0008, 0x20000000);
-  MmioWrite32(0xfd5d4008, 0x20000000);
-  MmioWrite32(0xfd5d8008, 0x20000000);
-  MmioWrite32(0xfd5dc008, 0x20000000);
-  MmioWrite32(0xfd7f0a10, 0x07000700);
-  MmioWrite32(0xfd7f0a10, 0x07000000);
+  MmioWrite32 (0xfd5d0008, 0x20000000);
+  MmioWrite32 (0xfd5d4008, 0x20000000);
+  MmioWrite32 (0xfd5d8008, 0x20000000);
+  MmioWrite32 (0xfd5dc008, 0x20000000);
+  MmioWrite32 (0xfd7f0a10, 0x07000700);
+  MmioWrite32 (0xfd7f0a10, 0x07000000);
 }
 
 VOID
 EFIAPI
 PcieIoInit (
-  UINT32 Segment
+  UINT32  Segment
   )
 {
   /* Set reset and power IO to gpio output mode */
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4:
       GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
       GpioPinSetDirection (1, GPIO_PIN_PA4, GPIO_PIN_OUTPUT);
       // PciePinmuxInit(Segment, 1);
       break;
+    case PCIE_SEGMENT_PCIE30X2:
+      GpioPinSetDirection (4, GPIO_PIN_PB0, GPIO_PIN_OUTPUT);
+      break;
     case PCIE_SEGMENT_PCIE20L0:
       GpioPinSetDirection (4, GPIO_PIN_PA5, GPIO_PIN_OUTPUT);
       GpioPinSetDirection (1, GPIO_PIN_PD2, GPIO_PIN_OUTPUT);
@@ -262,13 +270,13 @@ PcieIoInit (
 VOID
 EFIAPI
 PciePowerEn (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
   /* output high to enable power */
 
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4:
       GpioPinWrite (1, GPIO_PIN_PA4, Enable);
       break;
@@ -288,14 +296,17 @@ PciePowerEn (
 VOID
 EFIAPI
 PciePeReset (
-  UINT32 Segment,
-  BOOLEAN Enable
+  UINT32   Segment,
+  BOOLEAN  Enable
   )
 {
-  switch(Segment) {
+  switch (Segment) {
     case PCIE_SEGMENT_PCIE30X4:
       GpioPinWrite (4, GPIO_PIN_PB6, !Enable);
       break;
+    case PCIE_SEGMENT_PCIE30X2:
+      GpioPinWrite (4, GPIO_PIN_PB0, !Enable);
+      break;
     case PCIE_SEGMENT_PCIE20L0: // m.2 a+e key
       GpioPinWrite (4, GPIO_PIN_PA5, !Enable);
       break;
@@ -310,12 +321,32 @@ PciePeReset (
   }
 }
 
-PWM_DATA pwm_data = {
+VOID
+EFIAPI
+HdmiTxIomux (
+  IN UINT32  Id
+  )
+{
+  switch (Id) {
+    case 1:
+      GpioPinSetFunction (2, GPIO_PIN_PC4, 4); // hdmim0_tx1_cec
+      GpioPinSetPull (2, GPIO_PIN_PC4, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (1, GPIO_PIN_PA6, 5); // hdmim0_tx1_hpd
+      GpioPinSetPull (1, GPIO_PIN_PA6, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (3, GPIO_PIN_PC6, 5); // hdmim1_tx1_scl
+      GpioPinSetPull (3, GPIO_PIN_PC6, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (3, GPIO_PIN_PC5, 5); // hdmim1_tx1_sda
+      GpioPinSetPull (3, GPIO_PIN_PC5, GPIO_PIN_PULL_NONE);
+      break;
+  }
+}
+
+PWM_DATA  pwm_data = {
   .ControllerID = PWM_CONTROLLER0,
-  .ChannelID = PWM_CHANNEL1,
-  .PeriodNs = 4000000,
-  .DutyNs = 4000000,
-  .Polarity = FALSE,
+  .ChannelID    = PWM_CHANNEL1,
+  .PeriodNs     = 4000000,
+  .DutyNs       = 4000000,
+  .Polarity     = FALSE,
 }; // PWM0_CH1
 
 VOID
@@ -332,7 +363,7 @@ PwmFanIoSetup (
 VOID
 EFIAPI
 PwmFanSetSpeed (
-  IN UINT32 Percentage
+  IN UINT32  Percentage
   )
 {
   pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100;
@@ -353,7 +384,7 @@ PlatformInitLeds (
 VOID
 EFIAPI
 PlatformSetStatusLed (
-  IN BOOLEAN Enable
+  IN BOOLEAN  Enable
   )
 {
   GpioPinWrite (0, GPIO_PIN_PC0, Enable);
@@ -362,7 +393,7 @@ PlatformSetStatusLed (
 VOID
 EFIAPI
 PlatformPcieWiFiEnable (
-  IN BOOLEAN Enable
+  IN BOOLEAN  Enable
   )
 {
   // WiFi - enable
@@ -376,19 +407,20 @@ PlatformPcieWiFiEnable (
   GpioPinSetDirection (4, GPIO_PIN_PC5, GPIO_PIN_OUTPUT);
   GpioPinWrite (2, GPIO_PIN_PC5, Enable);
   GpioPinSetDirection (2, GPIO_PIN_PC5, GPIO_PIN_OUTPUT);
-
 }
 
 CONST EFI_GUID *
 EFIAPI
 PlatformGetDtbFileGuid (
-  IN UINT32 CompatMode
+  IN UINT32  CompatMode
   )
 {
-  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+  STATIC CONST EFI_GUID  VendorDtbFileGuid = {
+    // DeviceTree/Vendor.inf
     0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
   };
-  STATIC CONST EFI_GUID MainlineDtbFileGuid = {       // DeviceTree/Mainline.inf
+  STATIC CONST EFI_GUID  MainlineDtbFileGuid = {
+    // DeviceTree/Mainline.inf
     0x84492e97, 0xa10f, 0x49a7, { 0x85, 0xe9, 0x02, 0x5d, 0x19, 0x66, 0xb3, 0x43 }
   };
 
@@ -409,6 +441,6 @@ PlatformEarlyInit (
   )
 {
   // Configure various things specific to this platform
-  PlatformPcieWiFiEnable(TRUE);
-  GpioPinSetFunction(1, GPIO_PIN_PD5, 0); //jdet
+  PlatformPcieWiFiEnable (TRUE);
+  GpioPinSetFunction (1, GPIO_PIN_PD5, 0); // jdet
 }

edk2-rockchip/Platform/Radxa/ROCK5ITX/ROCK5ITX.dsc

@@ -28,6 +28,9 @@
   FLASH_DEFINITION               = Silicon/Rockchip/RK3588/RK3588.fdf
   RK_PLATFORM_FVMAIN_MODULES     = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc
 
+  # GMAC is not exposed
+  DEFINE RK3588_GMAC_ENABLE = FALSE
+
   #
   # HYM8563 RTC support
   # I2C location configured by PCDs below.
@@ -72,21 +75,11 @@
   gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
   gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6
 
-  #
-  # HDMI1 Display
-  #
-  gRockchipTokenSpaceGuid.PcdHdmiId|0x00000001 #hdmi1
-
-  #
-  # CPU Performance default values
-  #
-  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
-
   #
   # PCIe/SATA/USB Combo PIPE PHY support flags and default values
   #
+  gRK3588TokenSpaceGuid.PcdPcie30PhyModeDefault|$(PCIE30_PHY_MODE_NANBNB)
+  gRK3588TokenSpaceGuid.PcdPcie30x2Supported|TRUE
   gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|FALSE
   gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|FALSE
   gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|FALSE
@@ -112,6 +105,13 @@
   #
   gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
 
+  #
+  # Display support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
+    VOP_OUTPUT_IF_HDMI1,
+    VOP_OUTPUT_IF_DP0
+  })}
 
 ################################################################################
 #

edk2-rockchip/Platform/StationPC/Drivers/LogoDxe/Logo.c

@@ -19,15 +19,15 @@
 #include <Library/DebugLib.h>
 
 typedef struct {
-  EFI_IMAGE_ID                          ImageId;
-  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
-  INTN                                  OffsetX;
-  INTN                                  OffsetY;
+  EFI_IMAGE_ID                             ImageId;
+  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE    Attribute;
+  INTN                                     OffsetX;
+  INTN                                     OffsetY;
 } LOGO_ENTRY;
 
-STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
-STATIC EFI_HII_HANDLE            mHiiHandle;
-STATIC LOGO_ENTRY                mLogos[] = {
+STATIC EFI_HII_IMAGE_EX_PROTOCOL  *mHiiImageEx;
+STATIC EFI_HII_HANDLE             mHiiHandle;
+STATIC LOGO_ENTRY                 mLogos[] = {
   {
     IMAGE_TOKEN (IMG_LOGO),
     EdkiiPlatformLogoDisplayAttributeCenter,
@@ -53,18 +53,19 @@ STATIC
 EFI_STATUS
 EFIAPI
 GetImage (
-  IN     EDKII_PLATFORM_LOGO_PROTOCOL          *This,
-  IN OUT UINT32                                *Instance,
-     OUT EFI_IMAGE_INPUT                       *Image,
-     OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
-     OUT INTN                                  *OffsetX,
-     OUT INTN                                  *OffsetY
+  IN     EDKII_PLATFORM_LOGO_PROTOCOL        *This,
+  IN OUT UINT32                              *Instance,
+  OUT EFI_IMAGE_INPUT                        *Image,
+  OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE  *Attribute,
+  OUT INTN                                   *OffsetX,
+  OUT INTN                                   *OffsetY
   )
 {
-  UINT32 Current;
+  UINT32  Current;
 
-  if (Instance == NULL || Image == NULL ||
-      Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
+  if ((Instance == NULL) || (Image == NULL) ||
+      (Attribute == NULL) || (OffsetX == NULL) || (OffsetY == NULL))
+  {
     return EFI_INVALID_PARAMETER;
   }
 
@@ -78,11 +79,15 @@ GetImage (
   *OffsetX   = mLogos[Current].OffsetX;
   *OffsetY   = mLogos[Current].OffsetY;
 
-  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
-                        mLogos[Current].ImageId, Image);
+  return mHiiImageEx->GetImageEx (
+                        mHiiImageEx,
+                        mHiiHandle,
+                        mLogos[Current].ImageId,
+                        Image
+                        );
 }
 
-STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+STATIC EDKII_PLATFORM_LOGO_PROTOCOL  mPlatformLogo = {
   GetImage
 };
 
@@ -101,44 +106,66 @@ STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
 EFI_STATUS
 EFIAPI
 InitializeLogo (
-  IN EFI_HANDLE               ImageHandle,
-  IN EFI_SYSTEM_TABLE         *SystemTable
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
-  EFI_STATUS                  Status;
-  EFI_HII_PACKAGE_LIST_HEADER *PackageList;
-  EFI_HII_DATABASE_PROTOCOL   *HiiDatabase;
-  EFI_HANDLE                  Handle;
+  EFI_STATUS                   Status;
+  EFI_HII_PACKAGE_LIST_HEADER  *PackageList;
+  EFI_HII_DATABASE_PROTOCOL    *HiiDatabase;
+  EFI_HANDLE                   Handle;
 
-  Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
-                  (VOID **) &HiiDatabase);
+  Status = gBS->LocateProtocol (
+                  &gEfiHiiDatabaseProtocolGuid,
+                  NULL,
+                  (VOID **)&HiiDatabase
+                  );
   ASSERT_EFI_ERROR (Status);
 
-  Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
-                  (VOID **) &mHiiImageEx);
+  Status = gBS->LocateProtocol (
+                  &gEfiHiiImageExProtocolGuid,
+                  NULL,
+                  (VOID **)&mHiiImageEx
+                  );
   ASSERT_EFI_ERROR (Status);
 
   //
   // Retrieve HII package list from ImageHandle
   //
-  Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
-                  (VOID **) &PackageList, ImageHandle, NULL,
-                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+  Status = gBS->OpenProtocol (
+                  ImageHandle,
+                  &gEfiHiiPackageListProtocolGuid,
+                  (VOID **)&PackageList,
+                  ImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
   if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR,
-      "HII Image Package with logo not found in PE/COFF resource section\n"));
+    DEBUG ((
+      DEBUG_ERROR,
+      "HII Image Package with logo not found in PE/COFF resource section\n"
+      ));
     return Status;
   }
 
   //
   // Publish HII package list to HII Database.
   //
-  Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
-                          &mHiiHandle);
+  Status = HiiDatabase->NewPackageList (
+                          HiiDatabase,
+                          PackageList,
+                          NULL,
+                          &mHiiHandle
+                          );
   if (!EFI_ERROR (Status)) {
     Handle = NULL;
-    Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
-                    &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
+    Status = gBS->InstallMultipleProtocolInterfaces (
+                    &Handle,
+                    &gEdkiiPlatformLogoProtocolGuid,
+                    &mPlatformLogo,
+                    NULL
+                    );
   }
+
   return Status;
 }

edk2-rockchip/Platform/StationPC/StationM3/StationM3.dsc

@@ -43,10 +43,3 @@
   gRockchipTokenSpaceGuid.PcdFamilyName|"Station M"
   gRockchipTokenSpaceGuid.PcdProductUrl|"https://www.stationpc.com/product/stationm3"
   gRockchipTokenSpaceGuid.PcdDeviceTreeName|"roc-rk3588s-pc"
-
-  #
-  # CPU Performance default values
-  #
-  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX)
-  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX)
-  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX)

edk2-rockchip/Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.c

@@ -26,16 +26,16 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include <Protocol/I2cDemo.h>
 #include <Protocol/I2c.h>
 
-CONST CHAR16 ShellI2cDemoFileName[] = L"I2cDemoTestShellCommand";
-EFI_HANDLE ShellI2cDemoHiiHandle = NULL;
+CONST CHAR16  ShellI2cDemoFileName[] = L"I2cDemoTestShellCommand";
+EFI_HANDLE    ShellI2cDemoHiiHandle  = NULL;
 
-STATIC CONST SHELL_PARAM_ITEM ParamList[] = {
-  {L"read", TypeFlag},
-  {L"write", TypeFlag},
-  {L"list", TypeFlag},
-  {L"help", TypeFlag},
-  {NULL , TypeMax}
-  };
+STATIC CONST SHELL_PARAM_ITEM  ParamList[] = {
+  { L"read",  TypeFlag },
+  { L"write", TypeFlag },
+  { L"list",  TypeFlag },
+  { L"help",  TypeFlag },
+  { NULL,     TypeMax  }
+};
 
 /**
   Return the file name of the help text file if not using HII.
@@ -43,7 +43,7 @@ STATIC CONST SHELL_PARAM_ITEM ParamList[] = {
   @return The string pointer to the file name.
 **/
 STATIC
-CONST CHAR16*
+CONST CHAR16 *
 EFIAPI
 ShellCommandGetManFileNameI2cDemo (
   VOID
@@ -58,44 +58,47 @@ Usage (
   VOID
   )
 {
-  Print (L"I2C DEMO TEST commands:\n"
-         "i2cdemo [read] [write] [list] [<Bus>][<Address>] [<Length>] [<RegAddress>] [<RegAddressLength>] [<Data>] \n"
-         "All modes except 'list' require Address, Length and Chip set.\n\n"
-         "read    - read from i2cdemo device\n"
-         "write   - write Data to i2cdemo device\\n"
-         "list    - list available i2cdemo devices\n\n"
-         "Bus    - I2C bus address\n"
-	 "Address    - i2cdemo bus address\n"
-         "Length	  - data byte length to read/write\\n"
-         "RegAddress - address in i2cdemo to read/write\n"
-         "RegAddressLength - address in i2cdemo length\n"
-         "Data    - data byte to be written\n"
-         "Examples:\n"
-         "List devices:\n"
-         " i2cdemo list\n"
-         "Read 2 bytes from address 0x10 in chip 0x51@bus2:\n"
-         " i2cdemo read 2 0x51 2 0x10 1\n"
-         "Fill 16 bytes with 0xab at address 0x0 in chip 0x57:\n"
-         " i2cdemo write 2 0x51 1 0x10 1 0x00\n"
-  );
+  Print (
+    L"I2C DEMO TEST commands:\n"
+    "i2cdemo [read] [write] [list] [<Bus>][<Address>] [<Length>] [<RegAddress>] [<RegAddressLength>] [<Data>] \n"
+    "All modes except 'list' require Address, Length and Chip set.\n\n"
+    "read    - read from i2cdemo device\n"
+    "write   - write Data to i2cdemo device\\n"
+    "list    - list available i2cdemo devices\n\n"
+    "Bus    - I2C bus address\n"
+    "Address    - i2cdemo bus address\n"
+    "Length\t  - data byte length to read/write\\n"
+    "RegAddress - address in i2cdemo to read/write\n"
+    "RegAddressLength - address in i2cdemo length\n"
+    "Data    - data byte to be written\n"
+    "Examples:\n"
+    "List devices:\n"
+    " i2cdemo list\n"
+    "Read 2 bytes from address 0x10 in chip 0x51@bus2:\n"
+    " i2cdemo read 2 0x51 2 0x10 1\n"
+    "Fill 16 bytes with 0xab at address 0x0 in chip 0x57:\n"
+    " i2cdemo write 2 0x51 1 0x10 1 0x00\n"
+    );
 }
 
 STATIC
 EFI_STATUS
 I2cDemoList (
-    )
+  )
 {
-  EFI_HANDLE *HandleBuffer;
-  EFI_STATUS Status;
-  UINTN ProtocolCount;
-  ROCKCHIP_I2CDEMO_PROTOCOL *I2cDemoProtocol;
-  UINTN i;
-  Status = gBS->LocateHandleBuffer ( ByProtocol,
-                                     &gRockchipI2cDemoProtocolGuid,
-                                     NULL,
-                                     &ProtocolCount,
-                                     &HandleBuffer
-                                   );
+  EFI_HANDLE                 *HandleBuffer;
+  EFI_STATUS                 Status;
+  UINTN                      ProtocolCount;
+  ROCKCHIP_I2CDEMO_PROTOCOL  *I2cDemoProtocol;
+  UINTN                      i;
+
+  Status = gBS->LocateHandleBuffer (
+                  ByProtocol,
+                  &gRockchipI2cDemoProtocolGuid,
+                  NULL,
+                  &ProtocolCount,
+                  &HandleBuffer
+                  );
   if (ProtocolCount == 0) {
     Print (L"0 devices found.\n");
   } else {
@@ -106,17 +109,24 @@ I2cDemoList (
     Status = gBS->OpenProtocol (
                     HandleBuffer[i],
                     &gRockchipI2cDemoProtocolGuid,
-                    (VOID **) &I2cDemoProtocol,
+                    (VOID **)&I2cDemoProtocol,
                     gImageHandle,
                     NULL,
-                    EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL );
-    Print (L"0x%x at bus %d\n", I2C_DEVICE_ADDRESS(I2cDemoProtocol->Identifier),
-        I2C_DEVICE_BUS(I2cDemoProtocol->Identifier));
-    Status = gBS->CloseProtocol ( HandleBuffer[i],
-                                  &gRockchipI2cDemoProtocolGuid,
-                                  gImageHandle,
-                                  NULL );
+                    EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL
+                    );
+    Print (
+      L"0x%x at bus %d\n",
+      I2C_DEVICE_ADDRESS (I2cDemoProtocol->Identifier),
+      I2C_DEVICE_BUS (I2cDemoProtocol->Identifier)
+      );
+    Status = gBS->CloseProtocol (
+                    HandleBuffer[i],
+                    &gRockchipI2cDemoProtocolGuid,
+                    gImageHandle,
+                    NULL
+                    );
   }
+
   Print (L"\n");
   return Status;
 }
@@ -124,44 +134,52 @@ I2cDemoList (
 STATIC
 EFI_STATUS
 I2cDemoLocateProtocol (
- IN  UINT32 Identifier,
- OUT EFI_HANDLE *FoundHandle,
- OUT ROCKCHIP_I2CDEMO_PROTOCOL **FoundI2cDemoProtocol
- )
+  IN  UINT32                     Identifier,
+  OUT EFI_HANDLE                 *FoundHandle,
+  OUT ROCKCHIP_I2CDEMO_PROTOCOL  **FoundI2cDemoProtocol
+  )
 {
-  EFI_HANDLE *HandleBuffer;
-  EFI_STATUS Status;
-  UINTN ProtocolCount;
-  ROCKCHIP_I2CDEMO_PROTOCOL *I2cDemoProtocol;
-  UINTN i;
-  Status = gBS->LocateHandleBuffer ( ByProtocol,
-                                     &gRockchipI2cDemoProtocolGuid,
-                                     NULL,
-                                     &ProtocolCount,
-                                     &HandleBuffer
-                                   );
-  if (EFI_ERROR(Status)) {
+  EFI_HANDLE                 *HandleBuffer;
+  EFI_STATUS                 Status;
+  UINTN                      ProtocolCount;
+  ROCKCHIP_I2CDEMO_PROTOCOL  *I2cDemoProtocol;
+  UINTN                      i;
+
+  Status = gBS->LocateHandleBuffer (
+                  ByProtocol,
+                  &gRockchipI2cDemoProtocolGuid,
+                  NULL,
+                  &ProtocolCount,
+                  &HandleBuffer
+                  );
+  if (EFI_ERROR (Status)) {
     return Status;
   }
+
   for (i = 0; i < ProtocolCount; i++) {
     Status = gBS->OpenProtocol (
                     HandleBuffer[i],
                     &gRockchipI2cDemoProtocolGuid,
-                    (VOID **) &I2cDemoProtocol,
+                    (VOID **)&I2cDemoProtocol,
                     gImageHandle,
                     NULL,
-                    EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL );
+                    EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL
+                    );
 
     if (I2cDemoProtocol->Identifier == Identifier) {
       *FoundI2cDemoProtocol = I2cDemoProtocol;
-      *FoundHandle = HandleBuffer[i];
+      *FoundHandle          = HandleBuffer[i];
       return EFI_SUCCESS;
     }
-    Status = gBS->CloseProtocol ( HandleBuffer[i],
-                                  &gRockchipI2cDemoProtocolGuid,
-                                  gImageHandle,
-                                  NULL );
+
+    Status = gBS->CloseProtocol (
+                    HandleBuffer[i],
+                    &gRockchipI2cDemoProtocolGuid,
+                    gImageHandle,
+                    NULL
+                    );
   }
+
   *FoundI2cDemoProtocol = NULL;
 
   return EFI_UNSUPPORTED;
@@ -174,34 +192,45 @@ ShellCommandRunI2cDemo (
   IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
-  EFI_STATUS              Status;
-  LIST_ENTRY              *CheckPackage;
-  CHAR16                  *ProblemParam;
-  CONST CHAR16            *ValueStr;
-  UINTN                   Bus, Address, XferLength, RegAddress, RegAddressLength, Source;
-  UINT8                   *Buffer;
-  BOOLEAN                 ReadMode, WriteMode;
-  EFI_HANDLE              Handle, ProtHandle;
-  ROCKCHIP_I2CDEMO_PROTOCOL *I2cDemoProtocol = NULL;
-  UINTN                   HandleSize, i;
-  UINTN                   TxData;
+  EFI_STATUS                 Status;
+  LIST_ENTRY                 *CheckPackage;
+  CHAR16                     *ProblemParam;
+  CONST CHAR16               *ValueStr;
+  UINTN                      Bus, Address, XferLength, RegAddress, RegAddressLength, Source;
+  UINT8                      *Buffer;
+  BOOLEAN                    ReadMode, WriteMode;
+  EFI_HANDLE                 Handle, ProtHandle;
+  ROCKCHIP_I2CDEMO_PROTOCOL  *I2cDemoProtocol = NULL;
+  UINTN                      HandleSize, i;
+  UINTN                      TxData;
 
-  Handle = NULL;
-  Source = 0;
+  Handle     = NULL;
+  Source     = 0;
   HandleSize = 2 * sizeof (EFI_HANDLE);
 
-  Status = gBS->LocateHandle (ByProtocol, &gRockchipI2cDemoProtocolGuid, NULL,
-    &HandleSize, &ProtHandle);
-  if (EFI_ERROR(Status)) {
+  Status = gBS->LocateHandle (
+                  ByProtocol,
+                  &gRockchipI2cDemoProtocolGuid,
+                  NULL,
+                  &HandleSize,
+                  &ProtHandle
+                  );
+  if (EFI_ERROR (Status)) {
     Print (L"No I2cDemo protocol, connect I2C stack\n");
-    Status = gBS->LocateHandle (ByProtocol, &gEfiI2cMasterProtocolGuid, NULL,
-      &HandleSize, &ProtHandle);
-    if (EFI_ERROR(Status)) {
+    Status = gBS->LocateHandle (
+                    ByProtocol,
+                    &gEfiI2cMasterProtocolGuid,
+                    NULL,
+                    &HandleSize,
+                    &ProtHandle
+                    );
+    if (EFI_ERROR (Status)) {
       Print (L"Failed to locate I2cMaster protocol, abort!\n");
       return SHELL_ABORTED;
     }
+
     Status = gBS->ConnectController (ProtHandle, NULL, NULL, TRUE);
-    if (EFI_ERROR(Status)) {
+    if (EFI_ERROR (Status)) {
       Print (L"Cannot connect I2C stack, abort!\n");
       return SHELL_ABORTED;
     }
@@ -220,83 +249,84 @@ ShellCommandRunI2cDemo (
   }
 
   if (ShellCommandLineGetFlag (CheckPackage, L"list")) {
-    I2cDemoList();
+    I2cDemoList ();
     return SHELL_SUCCESS;
   }
 
   if (ShellCommandLineGetFlag (CheckPackage, L"help")) {
-    Usage();
+    Usage ();
     return SHELL_SUCCESS;
   }
 
-  ReadMode = ShellCommandLineGetFlag (CheckPackage, L"read");
+  ReadMode  = ShellCommandLineGetFlag (CheckPackage, L"read");
   WriteMode = ShellCommandLineGetFlag (CheckPackage, L"write");
 
   if (!ReadMode && !WriteMode) {
     Print (L"Not support mode given.\n");
-    Usage();
+    Usage ();
     return SHELL_ABORTED;
   }
 
-  if (ShellCommandLineGetCount(CheckPackage) != 6 && ReadMode) {
+  if ((ShellCommandLineGetCount (CheckPackage) != 6) && ReadMode) {
     Print (L"Not enough arguments given.\n");
-    Usage();
+    Usage ();
     return SHELL_ABORTED;
   }
 
-  if (ShellCommandLineGetCount(CheckPackage) != 7 && WriteMode) {
+  if ((ShellCommandLineGetCount (CheckPackage) != 7) && WriteMode) {
     Print (L"Not enough arguments given.\n");
-    Usage();
+    Usage ();
     return SHELL_ABORTED;
   }
 
-  ValueStr = ShellCommandLineGetRawValue(CheckPackage, 1);
-  Bus = ShellHexStrToUintn (ValueStr);
+  ValueStr = ShellCommandLineGetRawValue (CheckPackage, 1);
+  Bus      = ShellHexStrToUintn (ValueStr);
 
-  ValueStr = ShellCommandLineGetRawValue(CheckPackage, 2);
-  Address = ShellHexStrToUintn (ValueStr);
+  ValueStr = ShellCommandLineGetRawValue (CheckPackage, 2);
+  Address  = ShellHexStrToUintn (ValueStr);
 
-  ValueStr = ShellCommandLineGetRawValue(CheckPackage, 3);
+  ValueStr   = ShellCommandLineGetRawValue (CheckPackage, 3);
   XferLength = ShellHexStrToUintn (ValueStr);
 
-  ValueStr = ShellCommandLineGetRawValue(CheckPackage, 4);
+  ValueStr   = ShellCommandLineGetRawValue (CheckPackage, 4);
   RegAddress = ShellHexStrToUintn (ValueStr);
 
-  ValueStr = ShellCommandLineGetRawValue(CheckPackage, 5);
+  ValueStr         = ShellCommandLineGetRawValue (CheckPackage, 5);
   RegAddressLength = ShellHexStrToUintn (ValueStr);
 
   if (WriteMode) {
-    ValueStr = ShellCommandLineGetRawValue(CheckPackage, 6);
-    TxData = ShellHexStrToUintn (ValueStr);
+    ValueStr = ShellCommandLineGetRawValue (CheckPackage, 6);
+    TxData   = ShellHexStrToUintn (ValueStr);
   }
 
-  I2cDemoLocateProtocol (I2C_DEVICE_INDEX(Bus, Address), &Handle, &I2cDemoProtocol);
+  I2cDemoLocateProtocol (I2C_DEVICE_INDEX (Bus, Address), &Handle, &I2cDemoProtocol);
   if (I2cDemoProtocol == NULL) {
     Print (L"Failed to locate I2CDEMO protocol.\n");
     return SHELL_INVALID_PARAMETER;
   }
 
-    Buffer = AllocateZeroPool (XferLength);
-    if (Buffer == NULL) {
-      Status = SHELL_OUT_OF_RESOURCES;
-      Print (L"Error - out of resources.\n");
-      goto out_close;
-    }
+  Buffer = AllocateZeroPool (XferLength);
+  if (Buffer == NULL) {
+    Status = SHELL_OUT_OF_RESOURCES;
+    Print (L"Error - out of resources.\n");
+    goto out_close;
+  }
 
   if (ReadMode) {
-    Status = I2cDemoProtocol->Read(I2cDemoProtocol, (UINT8 *)&RegAddress, RegAddressLength,  Buffer, XferLength);
-    if (!EFI_ERROR(Status)) {
+    Status = I2cDemoProtocol->Read (I2cDemoProtocol, (UINT8 *)&RegAddress, RegAddressLength, Buffer, XferLength);
+    if (!EFI_ERROR (Status)) {
       Print (L"Read data[0 ~ %d]:", XferLength - 1);
-      for (i = 0; i <XferLength; i++ ) {
+      for (i = 0; i < XferLength; i++ ) {
         Print (L" 0x%x", Buffer[i]);
       }
+
       Print (L"\n");
     }
   } else {
-    Status = I2cDemoProtocol->Write(I2cDemoProtocol, (UINT8 *)&RegAddress, RegAddressLength,  (UINT8 *)&TxData, XferLength);
+    Status = I2cDemoProtocol->Write (I2cDemoProtocol, (UINT8 *)&RegAddress, RegAddressLength, (UINT8 *)&TxData, XferLength);
   }
 
-  if (EFI_ERROR(Status)) {
+  if (EFI_ERROR (Status)) {
     Print (L"I2c Operation failed %d.\n", Status);
   } else {
     Print (L"I2c Operation successfully.\n");
@@ -304,12 +334,14 @@ ShellCommandRunI2cDemo (
 
   Status = SHELL_SUCCESS;
 
-    FreePool(Buffer);
+  FreePool (Buffer);
 out_close:
-  gBS->CloseProtocol ( Handle,
-                       &gRockchipI2cDemoProtocolGuid,
-                       gImageHandle,
-                       NULL );
+  gBS->CloseProtocol (
+         Handle,
+         &gRockchipI2cDemoProtocolGuid,
+         gImageHandle,
+         NULL
+         );
 
   return Status;
 }
@@ -321,22 +353,30 @@ ShellI2cDemoTestLibConstructor (
   IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
-
   Print (L"~Filed to add Hii package\n");
   ShellI2cDemoHiiHandle = NULL;
 
   ShellI2cDemoHiiHandle = HiiAddPackages (
-                          &gShellI2cDemoHiiGuid, gImageHandle,
-                          UefiShellI2cDemoLibStrings, NULL
-                          );
+                            &gShellI2cDemoHiiGuid,
+                            gImageHandle,
+                            UefiShellI2cDemoLibStrings,
+                            NULL
+                            );
   if (ShellI2cDemoHiiHandle == NULL) {
     Print (L"Filed to add Hii package\n");
     return EFI_DEVICE_ERROR;
   }
+
   ShellCommandRegisterCommandName (
-     L"i2cdemo", ShellCommandRunI2cDemo, ShellCommandGetManFileNameI2cDemo, 0,
-     L"i2cdemo", TRUE , ShellI2cDemoHiiHandle, STRING_TOKEN (STR_GET_HELP_I2CDEMO)
-     );
+    L"i2cdemo",
+    ShellCommandRunI2cDemo,
+    ShellCommandGetManFileNameI2cDemo,
+    0,
+    L"i2cdemo",
+    TRUE,
+    ShellI2cDemoHiiHandle,
+    STRING_TOKEN (STR_GET_HELP_I2CDEMO)
+    );
 
   return EFI_SUCCESS;
 }
@@ -348,9 +388,9 @@ ShellI2cDemoTestLibDestructor (
   IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
-
   if (ShellI2cDemoHiiHandle != NULL) {
     HiiRemovePackages (ShellI2cDemoHiiHandle);
   }
+
   return EFI_SUCCESS;
 }

edk2-rockchip/Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.c

@@ -23,22 +23,22 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include <Protocol/FirmwareVolumeBlock.h>
 #include <Protocol/NorFlashProtocol.h>
 
-UNI_NOR_FLASH_PROTOCOL *SpiFlashProtocol;
+UNI_NOR_FLASH_PROTOCOL  *SpiFlashProtocol;
 
-CONST CHAR16 gShellSpiFlashFileName[] = L"ShellCommand";
-EFI_HANDLE gShellSfHiiHandle = NULL;
+CONST CHAR16  gShellSpiFlashFileName[] = L"ShellCommand";
+EFI_HANDLE    gShellSfHiiHandle        = NULL;
 
-STATIC CONST SHELL_PARAM_ITEM ParamList[] = {
-  {L"read", TypeFlag},
-  {L"readfile", TypeFlag},
-  {L"write", TypeFlag},
-  {L"writefile", TypeFlag},
-  {L"erase", TypeFlag},
-  {L"update", TypeFlag},
-  {L"updatefile", TypeFlag},
-  {L"help", TypeFlag},
-  {NULL , TypeMax}
-  };
+STATIC CONST SHELL_PARAM_ITEM  ParamList[] = {
+  { L"read",       TypeFlag },
+  { L"readfile",   TypeFlag },
+  { L"write",      TypeFlag },
+  { L"writefile",  TypeFlag },
+  { L"erase",      TypeFlag },
+  { L"update",     TypeFlag },
+  { L"updatefile", TypeFlag },
+  { L"help",       TypeFlag },
+  { NULL,          TypeMax  }
+};
 
 typedef enum {
   READ        = 2,
@@ -55,13 +55,12 @@ typedef enum {
 
   @return The string pointer to the file name.
 **/
-CONST CHAR16*
+CONST CHAR16 *
 EFIAPI
 ShellCommandGetManFileNameSpiFlash (
   VOID
   )
 {
-
   return gShellSpiFlashFileName;
 }
 
@@ -70,42 +69,43 @@ SfUsage (
   VOID
   )
 {
-  Print (L"\nBasic SPI command\n"
-         "sf [read | readfile | write | writefile | erase |"
-         "update | updatefile]"
-         "[<Address> | <FilePath>] <Offset> <Length>\n\n"
-         "Address  - Address in RAM to store/load data\n"
-         "FilePath - Path to file to read/write data from/to\n"
-         "Offset   - Offset from beginning of SPI flash to store/load data\n"
-         "Length   - Number of bytes to send\n"
-         "Examples:\n"
-         "Check if there is response from SPI flash\n"
-         "Read 32 bytes from 0xe00000 of SPI flash into RAM at address 0x100000\n"
-         "  sf read 0x100000 0xe00000 32\n"
-         "Read 0x20 bytes from 0x200000 of SPI flash into RAM at address 0x300000\n"
-         "  sf read 0x300000 0x200000 0x20\n"
-         "Erase 0x10000 bytes from offset 0x100000 of SPI flash\n"
-         "  sf erase 0x100000 0x100000\n"
-         "Write 16 bytes from 0x200000 at RAM into SPI flash at address 0x4000000\n"
-         "  sf write 0x200000 0x4000000 16\n"
-         "Update 100 bytes from 0x100000 at RAM in SPI flash at address 0xe00000\n"
-         "  sf update 0x100000 0xe00000 100\n"
-         "Read 0x3000 bytes from 0x0 of SPI flash into file fs2:file.bin\n"
-         "  sf readfile fs2:file.bin 0x0 0x3000 \n"
-         "Update data in SPI flash at 0x3000000 from file Linux.efi\n"
-         "  sf updatefile Linux.efi 0x3000000\n"
-  );
+  Print (
+    L"\nBasic SPI command\n"
+    "sf [read | readfile | write | writefile | erase |"
+    "update | updatefile]"
+    "[<Address> | <FilePath>] <Offset> <Length>\n\n"
+    "Address  - Address in RAM to store/load data\n"
+    "FilePath - Path to file to read/write data from/to\n"
+    "Offset   - Offset from beginning of SPI flash to store/load data\n"
+    "Length   - Number of bytes to send\n"
+    "Examples:\n"
+    "Check if there is response from SPI flash\n"
+    "Read 32 bytes from 0xe00000 of SPI flash into RAM at address 0x100000\n"
+    "  sf read 0x100000 0xe00000 32\n"
+    "Read 0x20 bytes from 0x200000 of SPI flash into RAM at address 0x300000\n"
+    "  sf read 0x300000 0x200000 0x20\n"
+    "Erase 0x10000 bytes from offset 0x100000 of SPI flash\n"
+    "  sf erase 0x100000 0x100000\n"
+    "Write 16 bytes from 0x200000 at RAM into SPI flash at address 0x4000000\n"
+    "  sf write 0x200000 0x4000000 16\n"
+    "Update 100 bytes from 0x100000 at RAM in SPI flash at address 0xe00000\n"
+    "  sf update 0x100000 0xe00000 100\n"
+    "Read 0x3000 bytes from 0x0 of SPI flash into file fs2:file.bin\n"
+    "  sf readfile fs2:file.bin 0x0 0x3000 \n"
+    "Update data in SPI flash at 0x3000000 from file Linux.efi\n"
+    "  sf updatefile Linux.efi 0x3000000\n"
+    );
 }
 
 STATIC
 EFI_STATUS
 OpenAndPrepareFile (
-  IN CHAR16 *FilePath,
-  SHELL_FILE_HANDLE *FileHandle
+  IN CHAR16          *FilePath,
+  SHELL_FILE_HANDLE  *FileHandle
   )
 {
-  EFI_STATUS Status;
-  UINT64 OpenMode;
+  EFI_STATUS  Status;
+  UINT64      OpenMode;
 
   OpenMode = EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE | EFI_FILE_MODE_CREATE;
 
@@ -115,9 +115,9 @@ OpenAndPrepareFile (
     return Status;
   }
 
-  Status = FileHandleSetPosition(*FileHandle, 0);
+  Status = FileHandleSetPosition (*FileHandle, 0);
 
-  if (EFI_ERROR(Status)) {
+  if (EFI_ERROR (Status)) {
     Print (L"sf: Cannot set file position to first byte\n");
     ShellCloseFile (FileHandle);
     return Status;
@@ -133,7 +133,7 @@ ShellCommandRunSpiFlash (
   IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
-EFI_STATUS              Status;
+  EFI_STATUS            Status;
   LIST_ENTRY            *CheckPackage;
   EFI_PHYSICAL_ADDRESS  Address = 0, Offset = 0;
   SHELL_FILE_HANDLE     FileHandle = NULL;
@@ -147,11 +147,11 @@ EFI_STATUS              Status;
   UINT8                 Flag = 0, CheckFlag = 0;
 
   Status = gBS->LocateProtocol (
-    &gUniNorFlashProtocolGuid,
-    NULL,
-    (VOID **)&SpiFlashProtocol
-  );
-  if (EFI_ERROR(Status)) {
+                  &gUniNorFlashProtocolGuid,
+                  NULL,
+                  (VOID **)&SpiFlashProtocol
+                  );
+  if (EFI_ERROR (Status)) {
     Print (L"sf: Cannot locate SpiFlash protocol\n");
     return SHELL_ABORTED;
   }
@@ -171,7 +171,7 @@ EFI_STATUS              Status;
   }
 
   if (ShellCommandLineGetFlag (CheckPackage, L"help")) {
-    SfUsage();
+    SfUsage ();
     return EFI_SUCCESS;
   }
 
@@ -189,37 +189,37 @@ EFI_STATUS              Status;
     I += CheckFlag & 1;
     if (I > 1) {
       Print (L"sf: Too many flags\n");
-      SfUsage();
+      SfUsage ();
       return SHELL_ABORTED;
     }
   }
 
   switch (Flag) {
-  case READ:
-  case WRITE:
-  case UPDATE:
-    AddressStr = ShellCommandLineGetRawValue (CheckPackage, 1);
-    OffsetStr = ShellCommandLineGetRawValue (CheckPackage, 2);
-    LengthStr = ShellCommandLineGetRawValue (CheckPackage, 3);
-    AddrFlag = TRUE;
-    break;
-  case ERASE:
-    OffsetStr = ShellCommandLineGetRawValue (CheckPackage, 1);
-    LengthStr = ShellCommandLineGetRawValue (CheckPackage, 2);
-    break;
-  case READ_FILE:
-    FileStr = ShellCommandLineGetRawValue (CheckPackage, 1);
-    OffsetStr = ShellCommandLineGetRawValue (CheckPackage, 2);
-    LengthStr = ShellCommandLineGetRawValue (CheckPackage, 3);
-    FileFlag = TRUE;
-    break;
-  case WRITE_FILE:
-  case UPDATE_FILE:
-    FileStr = ShellCommandLineGetRawValue (CheckPackage, 1);
-    OffsetStr = ShellCommandLineGetRawValue (CheckPackage, 2);
-    LengthFlag = FALSE;
-    FileFlag = TRUE;
-    break;
+    case READ:
+    case WRITE:
+    case UPDATE:
+      AddressStr = ShellCommandLineGetRawValue (CheckPackage, 1);
+      OffsetStr  = ShellCommandLineGetRawValue (CheckPackage, 2);
+      LengthStr  = ShellCommandLineGetRawValue (CheckPackage, 3);
+      AddrFlag   = TRUE;
+      break;
+    case ERASE:
+      OffsetStr = ShellCommandLineGetRawValue (CheckPackage, 1);
+      LengthStr = ShellCommandLineGetRawValue (CheckPackage, 2);
+      break;
+    case READ_FILE:
+      FileStr   = ShellCommandLineGetRawValue (CheckPackage, 1);
+      OffsetStr = ShellCommandLineGetRawValue (CheckPackage, 2);
+      LengthStr = ShellCommandLineGetRawValue (CheckPackage, 3);
+      FileFlag  = TRUE;
+      break;
+    case WRITE_FILE:
+    case UPDATE_FILE:
+      FileStr    = ShellCommandLineGetRawValue (CheckPackage, 1);
+      OffsetStr  = ShellCommandLineGetRawValue (CheckPackage, 2);
+      LengthFlag = FALSE;
+      FileFlag   = TRUE;
+      break;
   }
 
   // Read address parameter
@@ -264,8 +264,8 @@ EFI_STATUS              Status;
       Print (L"sf: No FilePath parameter!\n");
       return SHELL_ABORTED;
     } else {
-      FilePath = (CHAR16 *) FileStr;
-      Status = ShellIsFile (FilePath);
+      FilePath = (CHAR16 *)FileStr;
+      Status   = ShellIsFile (FilePath);
       // When read file into flash, file doesn't have to exist
       if (EFI_ERROR (Status) && !(Flag & READ_FILE)) {
         Print (L"sf: Wrong FilePath parameter!\n");
@@ -274,7 +274,7 @@ EFI_STATUS              Status;
     }
 
     Status = OpenAndPrepareFile (FilePath, &FileHandle);
-    if (EFI_ERROR(Status)) {
+    if (EFI_ERROR (Status)) {
       Print (L"sf: Error while preparing file\n");
       return SHELL_ABORTED;
     }
@@ -285,10 +285,11 @@ EFI_STATUS              Status;
       if (EFI_ERROR (Status)) {
         Print (L"sf: Cannot get file size\n");
       }
-      ByteCount = (UINTN) FileSize;
+
+      ByteCount = (UINTN)FileSize;
     }
 
-    FileBuffer = AllocateZeroPool ((UINTN) ByteCount);
+    FileBuffer = AllocateZeroPool ((UINTN)ByteCount);
     if (FileBuffer == NULL) {
       Print (L"sf: Cannot allocate memory\n");
       goto Error_Close_File;
@@ -300,7 +301,7 @@ EFI_STATUS              Status;
       if (EFI_ERROR (Status)) {
         Print (L"sf: Read from file error\n");
         goto Error_Free_Buffer;
-      } else if (ByteCount != (UINTN) FileSize) {
+      } else if (ByteCount != (UINTN)FileSize) {
         Print (L"sf: Not whole file read. Abort\n");
         goto Error_Free_Buffer;
       }
@@ -313,21 +314,21 @@ EFI_STATUS              Status;
   }
 
   switch (Flag) {
-  case READ:
-  case READ_FILE:
-    Status = SpiFlashProtocol->Read (SpiFlashProtocol, Offset, Buffer, ByteCount);
-    break;
-  case ERASE:
-    Status = SpiFlashProtocol->Erase (SpiFlashProtocol, Offset, ByteCount);
-    break;
-  case WRITE:
-  case WRITE_FILE:
-    Status = SpiFlashProtocol->Write (SpiFlashProtocol, Offset, Buffer, ByteCount);
-    break;
-  case UPDATE:
-  case UPDATE_FILE:
-    Status = SpiFlashProtocol->Update (SpiFlashProtocol, Offset, Buffer, ByteCount);
-    break;
+    case READ:
+    case READ_FILE:
+      Status = SpiFlashProtocol->Read (SpiFlashProtocol, Offset, Buffer, ByteCount);
+      break;
+    case ERASE:
+      Status = SpiFlashProtocol->Erase (SpiFlashProtocol, Offset, ByteCount);
+      break;
+    case WRITE:
+    case WRITE_FILE:
+      Status = SpiFlashProtocol->Write (SpiFlashProtocol, Offset, Buffer, ByteCount);
+      break;
+    case UPDATE:
+    case UPDATE_FILE:
+      Status = SpiFlashProtocol->Update (SpiFlashProtocol, Offset, Buffer, ByteCount);
+      break;
   }
 
   if (EFI_ERROR (Status)) {
@@ -336,28 +337,32 @@ EFI_STATUS              Status;
   }
 
   switch (Flag) {
-  case ERASE:
-    Print (L"sf: %d bytes succesfully erased at offset 0x%x\n", ByteCount,
-      Offset);
-    break;
-  case WRITE:
-  case WRITE_FILE:
-    Print (L"sf: Write %d bytes at offset 0x%x\n", ByteCount, Offset);
-    break;
-  case UPDATE:
-  case UPDATE_FILE:
-    Print (L"sf: Update %d bytes at offset 0x%x\n", ByteCount, Offset);
-    break;
-  case READ:
-    Print (L"sf: Read %d bytes from offset 0x%x\n", ByteCount, Offset);
-    break;
-  case READ_FILE:
-    Status = FileHandleWrite (FileHandle, &ByteCount, FileBuffer);
-    if (EFI_ERROR(Status)) {
-      Print (L"sf: Error while writing into file\n");
-      goto Error_Free_Buffer;
-    }
-    break;
+    case ERASE:
+      Print (
+        L"sf: %d bytes succesfully erased at offset 0x%x\n",
+        ByteCount,
+        Offset
+        );
+      break;
+    case WRITE:
+    case WRITE_FILE:
+      Print (L"sf: Write %d bytes at offset 0x%x\n", ByteCount, Offset);
+      break;
+    case UPDATE:
+    case UPDATE_FILE:
+      Print (L"sf: Update %d bytes at offset 0x%x\n", ByteCount, Offset);
+      break;
+    case READ:
+      Print (L"sf: Read %d bytes from offset 0x%x\n", ByteCount, Offset);
+      break;
+    case READ_FILE:
+      Status = FileHandleWrite (FileHandle, &ByteCount, FileBuffer);
+      if (EFI_ERROR (Status)) {
+        Print (L"sf: Error while writing into file\n");
+        goto Error_Free_Buffer;
+      }
+
+      break;
   }
 
   if (FileFlag) {
@@ -387,17 +392,25 @@ ShellSpiFlashLibConstructor (
   gShellSfHiiHandle = NULL;
 
   gShellSfHiiHandle = HiiAddPackages (
-                        &gShellSfHiiGuid, gImageHandle,
-                        UefiShellSpiFlashLibStrings, NULL
+                        &gShellSfHiiGuid,
+                        gImageHandle,
+                        UefiShellSpiFlashLibStrings,
+                        NULL
                         );
   if (gShellSfHiiHandle == NULL) {
     return EFI_DEVICE_ERROR;
   }
 
   ShellCommandRegisterCommandName (
-     L"sf", ShellCommandRunSpiFlash, ShellCommandGetManFileNameSpiFlash, 0,
-     L"sf", TRUE , gShellSfHiiHandle, STRING_TOKEN (STR_GET_HELP_SF)
-     );
+    L"sf",
+    ShellCommandRunSpiFlash,
+    ShellCommandGetManFileNameSpiFlash,
+    0,
+    L"sf",
+    TRUE,
+    gShellSfHiiHandle,
+    STRING_TOKEN (STR_GET_HELP_SF)
+    );
 
   return EFI_SUCCESS;
 }
@@ -409,9 +422,9 @@ ShellSpiFlashLibDestructor (
   IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
-
   if (gShellSfHiiHandle != NULL) {
     HiiRemovePackages (gShellSfHiiHandle);
   }
+
   return EFI_SUCCESS;
 }

edk2-rockchip/Silicon/Rockchip/Drivers/DwcSdhciDxe/DwcSdhciDxe.c

@@ -21,10 +21,10 @@
 
 #include "DwcSdhciDxe.h"
 
-#define EMMC_FORCE_HIGH_SPEED   FixedPcdGetBool(PcdDwcSdhciForceHighSpeed)
-#define EMMC_DISABLE_HS400      FixedPcdGetBool(PcdDwcSdhciDisableHs400)
+#define EMMC_FORCE_HIGH_SPEED  FixedPcdGetBool(PcdDwcSdhciForceHighSpeed)
+#define EMMC_DISABLE_HS400     FixedPcdGetBool(PcdDwcSdhciDisableHs400)
 
-STATIC EFI_HANDLE mSdMmcControllerHandle;
+STATIC EFI_HANDLE  mSdMmcControllerHandle;
 
 /**
   Override function for SDHCI capability bits
@@ -44,17 +44,18 @@ STATIC
 EFI_STATUS
 EFIAPI
 EmmcSdMmcCapability (
-  IN      EFI_HANDLE                      ControllerHandle,
-  IN      UINT8                           Slot,
-  IN OUT  VOID                            *SdMmcHcSlotCapability,
-  IN OUT  UINT32                          *BaseClkFreq
+  IN      EFI_HANDLE  ControllerHandle,
+  IN      UINT8       Slot,
+  IN OUT  VOID        *SdMmcHcSlotCapability,
+  IN OUT  UINT32      *BaseClkFreq
   )
 {
-  SD_MMC_HC_SLOT_CAP *Capability = SdMmcHcSlotCapability;
+  SD_MMC_HC_SLOT_CAP  *Capability = SdMmcHcSlotCapability;
 
   if (SdMmcHcSlotCapability == NULL) {
     return EFI_INVALID_PARAMETER;
   }
+
   if (ControllerHandle != mSdMmcControllerHandle) {
     return EFI_NOT_FOUND;
   }
@@ -72,10 +73,10 @@ EmmcSdMmcCapability (
 
   if (EMMC_FORCE_HIGH_SPEED) {
     Capability->BaseClkFreq = 52;
-    Capability->Sdr50 = 0;
-    Capability->Ddr50 = 0;
-    Capability->Sdr104 = 0;
-    Capability->Hs400 = 0;
+    Capability->Sdr50       = 0;
+    Capability->Ddr50       = 0;
+    Capability->Sdr104      = 0;
+    Capability->Hs400       = 0;
   }
 
   return EFI_SUCCESS;
@@ -101,16 +102,16 @@ STATIC
 EFI_STATUS
 EFIAPI
 EmmcSdMmcNotifyPhase (
-  IN      EFI_HANDLE                      ControllerHandle,
-  IN      UINT8                           Slot,
-  IN      EDKII_SD_MMC_PHASE_TYPE         PhaseType,
-  IN OUT  VOID                            *PhaseData
+  IN      EFI_HANDLE               ControllerHandle,
+  IN      UINT8                    Slot,
+  IN      EDKII_SD_MMC_PHASE_TYPE  PhaseType,
+  IN OUT  VOID                     *PhaseData
   )
 {
-  SD_MMC_BUS_MODE                 *Timing;
-  UINTN                            MaxClockFreq;
-  UINT32                           Value, i;
-  UINT32                           TxClkTapNum;
+  SD_MMC_BUS_MODE  *Timing;
+  UINTN            MaxClockFreq;
+  UINT32           Value, i;
+  UINT32           TxClkTapNum;
 
   DEBUG ((DEBUG_INFO, "%a\n", __FUNCTION__));
 
@@ -121,110 +122,129 @@ EmmcSdMmcNotifyPhase (
   ASSERT (Slot == 0);
 
   switch (PhaseType) {
-  case EdkiiSdMmcInitHostPost:
-    /*
-     * Just before this Notification POWER_CTRL is toggled to power off
-     * and on the card.  On this controller implementation, toggling
-     * power off also removes SDCLK_ENABLE (BIT2) from from CLOCK_CTRL.
-     * Since the clock has already been set up prior to the power toggle,
-     * re-add the SDCLK_ENABLE bit to start the clock.
-     */
-    MmioOr16((UINT32) SD_MMC_HC_CLOCK_CTRL, CLOCK_CTRL_SDCLK_ENABLE);
-    break;
-
-  case EdkiiSdMmcUhsSignaling:
-    if (PhaseData == NULL) {
-      return EFI_INVALID_PARAMETER;
-    }
-
-    Timing = (SD_MMC_BUS_MODE *)PhaseData;
-    if (*Timing == SdMmcMmcHs400) {
-      /* HS400 uses a non-standard setting */
-      MmioOr16((UINT32) SD_MMC_HC_HOST_CTRL2, HOST_CTRL2_HS400);
-    }
-    break;
-
-  case EdkiiSdMmcSwitchClockFreqPost:
-    if (PhaseData == NULL) {
-      return EFI_INVALID_PARAMETER;
-    }
-
-    Timing = (SD_MMC_BUS_MODE *)PhaseData;
-    switch (*Timing) {
-    case SdMmcMmcHs400:
-    case SdMmcMmcHs200:
-      MaxClockFreq = 200000000UL;
+    case EdkiiSdMmcInitHostPost:
+      /*
+       * Just before this Notification POWER_CTRL is toggled to power off
+       * and on the card.  On this controller implementation, toggling
+       * power off also removes SDCLK_ENABLE (BIT2) from from CLOCK_CTRL.
+       * Since the clock has already been set up prior to the power toggle,
+       * re-add the SDCLK_ENABLE bit to start the clock.
+       */
+      MmioOr16 ((UINT32)SD_MMC_HC_CLOCK_CTRL, CLOCK_CTRL_SDCLK_ENABLE);
       break;
-    case SdMmcMmcHsSdr:
-    case SdMmcMmcHsDdr:
-      MaxClockFreq = 52000000UL;
+
+    case EdkiiSdMmcUhsSignaling:
+      if (PhaseData == NULL) {
+        return EFI_INVALID_PARAMETER;
+      }
+
+      Timing = (SD_MMC_BUS_MODE *)PhaseData;
+      if (*Timing == SdMmcMmcHs400) {
+        /* HS400 uses a non-standard setting */
+        MmioOr16 ((UINT32)SD_MMC_HC_HOST_CTRL2, HOST_CTRL2_HS400);
+      }
+
       break;
-    default:
-      MaxClockFreq = 26000000UL;
-      break;
-    }
 
-    DwcSdhciSetClockRate (MaxClockFreq);
+    case EdkiiSdMmcSwitchClockFreqPost:
+      if (PhaseData == NULL) {
+        return EFI_INVALID_PARAMETER;
+      }
 
-    if (MaxClockFreq <= 52000000UL) {
-      MmioWrite32 (EMMC_DLL_CTRL, 0);
-      MmioWrite32 (EMMC_DLL_RXCLK, 0);
-      MmioWrite32 (EMMC_DLL_TXCLK, 0);
-      MmioWrite32 (EMMC_DLL_CMDOUT, 0);
-      MmioWrite32 (EMMC_DLL_STRBIN, EMMC_DLL_DLYENA |
-                   EMMC_DLL_STRBIN_DELAY_NUM_SEL |
-                   EMMC_DLL_STRBIN_DELAY_NUM_DEFAULT << EMMC_DLL_STRBIN_DELAY_NUM_OFFSET);
-      break;
-    }
+      Timing = (SD_MMC_BUS_MODE *)PhaseData;
+      switch (*Timing) {
+        case SdMmcMmcHs400:
+        case SdMmcMmcHs200:
+          MaxClockFreq = 200000000UL;
+          break;
+        case SdMmcMmcHsSdr:
+        case SdMmcMmcHsDdr:
+          MaxClockFreq = 52000000UL;
+          break;
+        default:
+          MaxClockFreq = 26000000UL;
+          break;
+      }
 
-    /* Switch to eMMC mode */
-    MmioOr32 (EMMC_EMMC_CTRL, EMMC_CTRL_CARD_IS_EMMC);
+      DwcSdhciSetClockRate (MaxClockFreq);
 
-    MmioWrite32(EMMC_DLL_CTRL, EMMC_DLL_CTRL_SRST);
-    gBS->Stall (1);
-    MmioWrite32(EMMC_DLL_CTRL, 0);
-
-    MmioWrite32(EMMC_DLL_CTRL, EMMC_DLL_CTRL_START_POINT_DEFAULT |
-      EMMC_DLL_CTRL_INCREMENT_DEFAULT | EMMC_DLL_CTRL_START);
-
-    for (i = 0; i < 500; i++) {
-      Value = MmioRead32(EMMC_DLL_STATUS0);
-      if (Value & EMMC_DLL_STATUS0_DLL_LOCK &&
-          !(Value & EMMC_DLL_STATUS0_DLL_TIMEOUT)) {
+      if (MaxClockFreq <= 52000000UL) {
+        MmioWrite32 (EMMC_DLL_CTRL, 0);
+        MmioWrite32 (EMMC_DLL_RXCLK, 0);
+        MmioWrite32 (EMMC_DLL_TXCLK, 0);
+        MmioWrite32 (EMMC_DLL_CMDOUT, 0);
+        MmioWrite32 (
+          EMMC_DLL_STRBIN,
+          EMMC_DLL_DLYENA |
+          EMMC_DLL_STRBIN_DELAY_NUM_SEL |
+          EMMC_DLL_STRBIN_DELAY_NUM_DEFAULT << EMMC_DLL_STRBIN_DELAY_NUM_OFFSET
+          );
         break;
       }
+
+      /* Switch to eMMC mode */
+      MmioOr32 (EMMC_EMMC_CTRL, EMMC_CTRL_CARD_IS_EMMC);
+
+      MmioWrite32 (EMMC_DLL_CTRL, EMMC_DLL_CTRL_SRST);
       gBS->Stall (1);
-    }
+      MmioWrite32 (EMMC_DLL_CTRL, 0);
 
-    TxClkTapNum = EMMC_DLL_TXCLK_TAPNUM_DEFAULT;
+      MmioWrite32 (
+        EMMC_DLL_CTRL,
+        EMMC_DLL_CTRL_START_POINT_DEFAULT |
+        EMMC_DLL_CTRL_INCREMENT_DEFAULT | EMMC_DLL_CTRL_START
+        );
 
-    if (*Timing == SdMmcMmcHs400) {
-      TxClkTapNum = EMMC_DLL_TXCLK_TAPNUM_90_DEGREES;
+      for (i = 0; i < 500; i++) {
+        Value = MmioRead32 (EMMC_DLL_STATUS0);
+        if (Value & EMMC_DLL_STATUS0_DLL_LOCK &&
+            !(Value & EMMC_DLL_STATUS0_DLL_TIMEOUT))
+        {
+          break;
+        }
 
-      MmioWrite32 (EMMC_DLL_CMDOUT, EMMC_DLL_CMDOUT_SRC_CLK_NEG |
-                                    EMMC_DLL_CMDOUT_EN_SRC_CLK_NEG |
-                                    EMMC_DLL_DLYENA |
-                                    EMMC_DLL_CMDOUT_TAPNUM_90_DEGREES |
-                                    EMMC_DLL_TAPNUM_FROM_SW);
-    }
+        gBS->Stall (1);
+      }
 
-    MmioWrite32(EMMC_DLL_RXCLK, EMMC_DLL_DLYENA);
+      TxClkTapNum = EMMC_DLL_TXCLK_TAPNUM_DEFAULT;
 
-    MmioWrite32(EMMC_DLL_TXCLK, EMMC_DLL_DLYENA |
-      TxClkTapNum | EMMC_DLL_TAPNUM_FROM_SW |
-      EMMC_DLL_NO_INVERTER);
+      if (*Timing == SdMmcMmcHs400) {
+        TxClkTapNum = EMMC_DLL_TXCLK_TAPNUM_90_DEGREES;
 
-    MmioWrite32(EMMC_DLL_STRBIN, EMMC_DLL_DLYENA |
-      EMMC_DLL_STRBIN_TAPNUM_DEFAULT | EMMC_DLL_TAPNUM_FROM_SW);
-    break;
+        MmioWrite32 (
+          EMMC_DLL_CMDOUT,
+          EMMC_DLL_CMDOUT_SRC_CLK_NEG |
+          EMMC_DLL_CMDOUT_EN_SRC_CLK_NEG |
+          EMMC_DLL_DLYENA |
+          EMMC_DLL_CMDOUT_TAPNUM_90_DEGREES |
+          EMMC_DLL_TAPNUM_FROM_SW
+          );
+      }
 
-  default:
-    break;
+      MmioWrite32 (EMMC_DLL_RXCLK, EMMC_DLL_DLYENA);
+
+      MmioWrite32 (
+        EMMC_DLL_TXCLK,
+        EMMC_DLL_DLYENA |
+        TxClkTapNum | EMMC_DLL_TAPNUM_FROM_SW |
+        EMMC_DLL_NO_INVERTER
+        );
+
+      MmioWrite32 (
+        EMMC_DLL_STRBIN,
+        EMMC_DLL_DLYENA |
+        EMMC_DLL_STRBIN_TAPNUM_DEFAULT | EMMC_DLL_TAPNUM_FROM_SW
+        );
+      break;
+
+    default:
+      break;
   }
+
   return EFI_SUCCESS;
 }
 
-STATIC EDKII_SD_MMC_OVERRIDE mSdMmcOverride = {
+STATIC EDKII_SD_MMC_OVERRIDE  mSdMmcOverride = {
   EDKII_SD_MMC_OVERRIDE_PROTOCOL_VERSION,
   EmmcSdMmcCapability,
   EmmcSdMmcNotifyPhase,
@@ -233,12 +253,12 @@ STATIC EDKII_SD_MMC_OVERRIDE mSdMmcOverride = {
 EFI_STATUS
 EFIAPI
 DwcSdhciDxeInitialize (
-  IN EFI_HANDLE         ImageHandle,
-  IN EFI_SYSTEM_TABLE   *SystemTable
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
-  EFI_STATUS                      Status;
-  EFI_HANDLE                      Handle;
+  EFI_STATUS  Status;
+  EFI_HANDLE  Handle;
 
   DEBUG ((DEBUG_BLKIO, "%a\n", __FUNCTION__));
 
@@ -263,13 +283,18 @@ DwcSdhciDxeInitialize (
              NULL,
              &mSdMmcControllerHandle,
              1,
-             DWC_SDHCI_BASE, 0x10000);
+             DWC_SDHCI_BASE,
+             0x10000
+             );
   ASSERT_EFI_ERROR (Status);
 
   Handle = NULL;
-  Status = gBS->InstallProtocolInterface (&Handle,
+  Status = gBS->InstallProtocolInterface (
+                  &Handle,
                   &gEdkiiSdMmcOverrideProtocolGuid,
-                  EFI_NATIVE_INTERFACE, (VOID **)&mSdMmcOverride);
+                  EFI_NATIVE_INTERFACE,
+                  (VOID **)&mSdMmcOverride
+                  );
   ASSERT_EFI_ERROR (Status);
 
   return EFI_SUCCESS;

edk2-rockchip/Silicon/Rockchip/Drivers/DwcSdhciDxe/DwcSdhciDxe.h

@@ -12,39 +12,39 @@
 #ifndef __DWCSDHCIDXE_H__
 #define __DWCSDHCIDXE_H__
 
-#define DWC_SDHCI_BASE          PcdGet32 (PcdDwcSdhciBaseAddress)
+#define DWC_SDHCI_BASE  PcdGet32 (PcdDwcSdhciBaseAddress)
 
-#define SD_MMC_HC_CLOCK_CTRL    (DWC_SDHCI_BASE + 0x2C)
-#define SD_MMC_HC_HOST_CTRL2    (DWC_SDHCI_BASE + 0x3E)
+#define SD_MMC_HC_CLOCK_CTRL  (DWC_SDHCI_BASE + 0x2C)
+#define SD_MMC_HC_HOST_CTRL2  (DWC_SDHCI_BASE + 0x3E)
 
 // eMMC Registers
-#define EMMC_HOST_CTRL3         (DWC_SDHCI_BASE + 0x508)
-#define EMMC_EMMC_CTRL          (DWC_SDHCI_BASE + 0x52C)
-#define EMMC_DLL_CTRL           (DWC_SDHCI_BASE + 0x800)
-#define EMMC_DLL_RXCLK          (DWC_SDHCI_BASE + 0x804)
-#define EMMC_DLL_TXCLK          (DWC_SDHCI_BASE + 0x808)
-#define EMMC_DLL_STRBIN         (DWC_SDHCI_BASE + 0x80C)
-#define EMMC_DLL_CMDOUT         (DWC_SDHCI_BASE + 0x810)
-#define EMMC_DLL_STATUS0        (DWC_SDHCI_BASE + 0x840)
-#define EMMC_DLL_STATUS1        (DWC_SDHCI_BASE + 0x844)
+#define EMMC_HOST_CTRL3   (DWC_SDHCI_BASE + 0x508)
+#define EMMC_EMMC_CTRL    (DWC_SDHCI_BASE + 0x52C)
+#define EMMC_DLL_CTRL     (DWC_SDHCI_BASE + 0x800)
+#define EMMC_DLL_RXCLK    (DWC_SDHCI_BASE + 0x804)
+#define EMMC_DLL_TXCLK    (DWC_SDHCI_BASE + 0x808)
+#define EMMC_DLL_STRBIN   (DWC_SDHCI_BASE + 0x80C)
+#define EMMC_DLL_CMDOUT   (DWC_SDHCI_BASE + 0x810)
+#define EMMC_DLL_STATUS0  (DWC_SDHCI_BASE + 0x840)
+#define EMMC_DLL_STATUS1  (DWC_SDHCI_BASE + 0x844)
 
-#define CLOCK_CTRL_SDCLK_ENABLE            BIT2
+#define CLOCK_CTRL_SDCLK_ENABLE  BIT2
 
-#define HOST_CTRL2_HS400                   (BIT2 | BIT1 | BIT0)
+#define HOST_CTRL2_HS400  (BIT2 | BIT1 | BIT0)
 
-#define EMMC_CTRL_CARD_IS_EMMC             BIT0
+#define EMMC_CTRL_CARD_IS_EMMC  BIT0
 
 #define EMMC_DLL_CTRL_SRST                 BIT1
 #define EMMC_DLL_CTRL_START                BIT0
 #define EMMC_DLL_CTRL_START_POINT_DEFAULT  (5 << 16)
 #define EMMC_DLL_CTRL_INCREMENT_DEFAULT    (2 << 8)
 
-#define EMMC_DLL_NO_INVERTER               BIT29
-#define EMMC_DLL_DLYENA                    BIT27
-#define EMMC_DLL_TAPNUM_FROM_SW            BIT24
+#define EMMC_DLL_NO_INVERTER     BIT29
+#define EMMC_DLL_DLYENA          BIT27
+#define EMMC_DLL_TAPNUM_FROM_SW  BIT24
 
-#define EMMC_DLL_TXCLK_TAPNUM_DEFAULT      (0x10 << 0)
-#define EMMC_DLL_TXCLK_TAPNUM_90_DEGREES   0x9
+#define EMMC_DLL_TXCLK_TAPNUM_DEFAULT     (0x10 << 0)
+#define EMMC_DLL_TXCLK_TAPNUM_90_DEGREES  0x9
 
 #define EMMC_DLL_STRBIN_TAPNUM_DEFAULT     (0x3 << 0)
 #define EMMC_DLL_STRBIN_DELAY_NUM_SEL      BIT26
@@ -55,8 +55,8 @@
 #define EMMC_DLL_CMDOUT_SRC_CLK_NEG        BIT28
 #define EMMC_DLL_CMDOUT_EN_SRC_CLK_NEG     BIT29
 
-#define EMMC_DLL_STATUS0_DLL_LOCK          BIT8
-#define EMMC_DLL_STATUS0_DLL_TIMEOUT       BIT9
+#define EMMC_DLL_STATUS0_DLL_LOCK     BIT8
+#define EMMC_DLL_STATUS0_DLL_TIMEOUT  BIT9
 
 typedef struct {
   UINT32    TimeoutFreq   : 6; // bit 0:5

edk2-rockchip/Silicon/Rockchip/Drivers/ExitBootServicesHookDxe/ExitBootServicesHook.h

@@ -0,0 +1,50 @@
+/** @file
+ *
+ *  Copyright (c) 2024-2025, Mario Bălănică <mariobalanica02@gmail.com>
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#ifndef __EXIT_BOOT_SERVICES_HOOK_H__
+#define __EXIT_BOOT_SERVICES_HOOK_H__
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+#include <Protocol/ExitBootServicesOsNotify.h>
+
+typedef struct {
+  UINT32                           Signature;
+  LIST_ENTRY                       Link;
+  EXIT_BOOT_SERVICES_OS_HANDLER    Handler;
+} EXIT_BOOT_SERVICES_OS_HANDLER_ENTRY;
+#define EXIT_BOOT_SERVICES_OS_HANDLER_ENTRY_SIGNATURE  SIGNATURE_32('E', 'b', 'S', 'h')
+#define EXIT_BOOT_SERVICES_OS_HANDLER_ENTRY_FROM_LINK(a)  \
+  CR (a, EXIT_BOOT_SERVICES_OS_HANDLER_ENTRY, Link, EXIT_BOOT_SERVICES_OS_HANDLER_ENTRY_SIGNATURE)
+
+typedef struct {
+  UINT32                                   Signature;
+  EXIT_BOOT_SERVICES_OS_NOTIFY_PROTOCOL    Notify;
+  LIST_ENTRY                               Handlers;
+} EXIT_BOOT_SERVICES_OS_NOTIFY_INSTANCE;
+#define EXIT_BOOT_SERVICES_OS_NOTIFY_INSTANCE_SIGNATURE  SIGNATURE_32('E', 'b', 'S', 'n')
+#define EXIT_BOOT_SERVICES_OS_NOTIFY_INSTANCE_FROM_THIS(a) \
+  CR (a, EXIT_BOOT_SERVICES_OS_NOTIFY_INSTANCE, Notify, EXIT_BOOT_SERVICES_OS_NOTIFY_INSTANCE_SIGNATURE)
+
+EFI_PHYSICAL_ADDRESS
+FindPeImageBase (
+  IN EFI_PHYSICAL_ADDRESS  Base
+  );
+
+EXIT_BOOT_SERVICES_OS_TYPE
+IdentifyOsType (
+  IN EFI_PHYSICAL_ADDRESS  OsLoaderAddress
+  );
+
+CHAR8 *
+OsTypeToString (
+  IN EXIT_BOOT_SERVICES_OS_TYPE  OsType
+  );
+
+#endif

edk2-rockchip/Silicon/Rockchip/Drivers/ExitBootServicesHookDxe/ExitBootServicesHookDxe.c

@@ -0,0 +1,165 @@
+/** @file
+ *
+ *  Copyright (c) 2024-2025, Mario Bălănică <mariobalanica02@gmail.com>
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include "ExitBootServicesHook.h"
+
+STATIC EFI_EXIT_BOOT_SERVICES  mOriginalExitBootServices;
+
+STATIC
+EFI_STATUS
+EFIAPI
+RegisterHandler (
+  IN EXIT_BOOT_SERVICES_OS_NOTIFY_PROTOCOL  *This,
+  IN EXIT_BOOT_SERVICES_OS_HANDLER          Handler
+  )
+{
+  EXIT_BOOT_SERVICES_OS_NOTIFY_INSTANCE  *Instance;
+  LIST_ENTRY                             *Link;
+  EXIT_BOOT_SERVICES_OS_HANDLER_ENTRY    *Entry;
+
+  if (Handler == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Instance = EXIT_BOOT_SERVICES_OS_NOTIFY_INSTANCE_FROM_THIS (This);
+
+  for ( Link = GetFirstNode (&Instance->Handlers)
+        ; !IsNull (&Instance->Handlers, Link)
+        ; Link = GetNextNode (&Instance->Handlers, Link)
+        )
+  {
+    Entry = EXIT_BOOT_SERVICES_OS_HANDLER_ENTRY_FROM_LINK (Link);
+    if (Entry->Handler == Handler) {
+      return EFI_ALREADY_STARTED;
+    }
+  }
+
+  ASSERT (IsNull (&Instance->Handlers, Link));
+  Entry = AllocatePool (sizeof (*Entry));
+  if (Entry == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  Entry->Signature = EXIT_BOOT_SERVICES_OS_HANDLER_ENTRY_SIGNATURE;
+  Entry->Handler   = Handler;
+  InsertTailList (&Instance->Handlers, &Entry->Link);
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+EFIAPI
+UnregisterHandler (
+  IN EXIT_BOOT_SERVICES_OS_NOTIFY_PROTOCOL  *This,
+  IN EXIT_BOOT_SERVICES_OS_HANDLER          Handler
+  )
+{
+  EXIT_BOOT_SERVICES_OS_NOTIFY_INSTANCE  *Instance;
+  LIST_ENTRY                             *Link;
+  EXIT_BOOT_SERVICES_OS_HANDLER_ENTRY    *Entry;
+
+  if (Handler == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Instance = EXIT_BOOT_SERVICES_OS_NOTIFY_INSTANCE_FROM_THIS (This);
+
+  for ( Link = GetFirstNode (&Instance->Handlers)
+        ; !IsNull (&Instance->Handlers, Link)
+        ; Link = GetNextNode (&Instance->Handlers, Link)
+        )
+  {
+    Entry = EXIT_BOOT_SERVICES_OS_HANDLER_ENTRY_FROM_LINK (Link);
+    if (Entry->Handler == Handler) {
+      RemoveEntryList (&Entry->Link);
+      FreePool (Entry);
+      return EFI_SUCCESS;
+    }
+  }
+
+  return EFI_INVALID_PARAMETER;
+}
+
+STATIC EXIT_BOOT_SERVICES_OS_NOTIFY_INSTANCE  mNotifyInstance = {
+  EXIT_BOOT_SERVICES_OS_NOTIFY_INSTANCE_SIGNATURE,
+  {
+    RegisterHandler,
+    UnregisterHandler
+  },
+  INITIALIZE_LIST_HEAD_VARIABLE (mNotifyInstance.Handlers)
+};
+
+STATIC
+EFI_STATUS
+EFIAPI
+ExitBootServicesHook (
+  IN EFI_HANDLE  ImageHandle,
+  IN UINTN       MapKey
+  )
+{
+  EXIT_BOOT_SERVICES_OS_CONTEXT        Context;
+  LIST_ENTRY                           *Link;
+  EXIT_BOOT_SERVICES_OS_HANDLER_ENTRY  *Entry;
+
+  Context.ReturnAddress = (EFI_PHYSICAL_ADDRESS)RETURN_ADDRESS (0);
+  ASSERT (Context.ReturnAddress != 0);
+
+  Context.OsLoaderAddress = FindPeImageBase (Context.ReturnAddress);
+  Context.OsType          = IdentifyOsType (Context.OsLoaderAddress);
+
+  DEBUG ((
+    DEBUG_INFO,
+    "ExitBootServices: Booting %a OS at 0x%lx\n",
+    OsTypeToString (Context.OsType),
+    Context.OsLoaderAddress
+    ));
+
+  for ( Link = GetFirstNode (&mNotifyInstance.Handlers)
+        ; !IsNull (&mNotifyInstance.Handlers, Link)
+        ; Link = GetNextNode (&mNotifyInstance.Handlers, Link)
+        )
+  {
+    Entry = EXIT_BOOT_SERVICES_OS_HANDLER_ENTRY_FROM_LINK (Link);
+    Entry->Handler (&Context);
+  }
+
+  gBS->ExitBootServices = mOriginalExitBootServices;
+
+  return gBS->ExitBootServices (ImageHandle, MapKey);
+}
+
+EFI_STATUS
+EFIAPI
+ExitBootServicesHookDxeInitialize (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  EFI_STATUS  Status;
+  EFI_HANDLE  Handle;
+
+  Handle = NULL;
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &Handle,
+                  &gExitBootServicesOsNotifyProtocolGuid,
+                  &mNotifyInstance.Notify,
+                  NULL
+                  );
+  if (EFI_ERROR (Status)) {
+    ASSERT_EFI_ERROR (Status);
+    return Status;
+  }
+
+  mOriginalExitBootServices = gBS->ExitBootServices;
+  gBS->ExitBootServices     = ExitBootServicesHook;
+
+  return EFI_SUCCESS;
+}