Update README.md

Platforms: Make UEFI FV size consistent
Increase size to 0x00500000 for remaining platforms.
2026-01-13 07:50:43 +08:00 · 2023-06-01 03:52:28 +03:00 · 2023-06-01 03:40:02 +03:00 · 2023-06-01 03:36:20 +03:00 · 2023-06-01 02:54:54 +03:00 · 2023-06-01 02:43:40 +03:00
229 changed files with 19764 additions and 16663 deletions
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -0,0 +1,68 @@
+name: Build
+on:
+  push:
+    branches:
+      - master
+  pull_request:
+    branches:
+      - master
+  workflow_call:
+
+jobs:
+  build:
+    runs-on: ubuntu-latest
+    strategy:
+      matrix:
+        PLATFORM:
+          - rock-5b
+          - orangepi-5
+          - indiedroid-nova
+          - roc-rk3588s-pc
+          - station-m3
+          - r58x
+          - r58-mini
+          - edge2
+          - nanopc-t6
+          - rock-5a
+          # - rk3588-evb is currently failing
+        CONFIGURATION: [Debug, Release]
+    steps:
+      - name: Checkout
+        uses: actions/checkout@v3
+      - name: Submodule init
+        shell: bash
+        run: git submodule update --init --recursive
+        
+      - name: Install dependencies
+        shell: bash
+        run: |
+          sudo apt-get update && \
+          sudo apt-get install -y \
+          acpica-tools \
+          binutils-aarch64-linux-gnu \
+          build-essential \
+          device-tree-compiler \
+          gettext \
+          git \
+          gcc-aarch64-linux-gnu \
+          libc6-dev-arm64-cross \
+          python3 \
+          python3-pyelftools
+          
+      - name: Get version tag
+        id: get_version_tag
+        shell: bash
+        run: echo "version=$(git describe --tags --always)" >> $GITHUB_OUTPUT
+        
+      - name: Build platform
+        shell: bash
+        run: |  
+         ./build.sh --device ${{matrix.PLATFORM}} --release ${{matrix.CONFIGURATION}}
+          mv RK3588_NOR_FLASH.img ${{matrix.PLATFORM}}_UEFI_${{matrix.CONFIGURATION}}_${{steps.get_version_tag.outputs.version}}.img
+        
+      - name: Upload artifact
+        uses: actions/upload-artifact@v3
+        with:
+          name: ${{matrix.PLATFORM}} UEFI ${{matrix.CONFIGURATION}} image
+          path: ./*.img
+          if-no-files-found: error
--- a/.github/workflows/release.yml
+++ b/.github/workflows/release.yml
@@ -0,0 +1,34 @@
+name: Release
+on:  
+  push:
+    tags:
+      - '*'
+      
+jobs:
+  build_for_release:
+    uses: ./.github/workflows/build.yml
+  
+  release:
+    runs-on: ubuntu-latest
+    needs: build_for_release
+    permissions:
+      contents: write
+    steps:
+      - name: Download all workflow run artifacts
+        uses: actions/download-artifact@v3
+          
+      - name: Create release
+        uses: softprops/action-gh-release@v1
+        with:
+          draft: true
+          prerelease: false
+          files: "*/*Release*.img"
+          fail_on_unmatched_files: true
+          generate_release_notes: true
+          append_body: true
+          body: |
+            ## Usage
+            Flash the board-specific image to SPINOR with rkdevtool / rkdeveloptool or to an EMMC / SD card.
+            If your board is not yet supported, using a similar image may work but beware of potential issues.
+
+            Debug builds can be found in the artifacts of the workflow run for this release.
--- a/README.md
+++ b/README.md
@@ -1,65 +1,174 @@
-# EDK2 UEFI firmware for Rockchip RK35xx platforms
+# EDK2 UEFI firmware for Rockchip RK3588 platforms
+This repository contains an UEFI firmware implementation based on EDK2 for various RK3588 boards.

-**WARNING: This repo is highly experimental**
+## Supported platforms
+- [Radxa ROCK 5B](https://wiki.radxa.com/Rock5/hardware/5b)
+- [Radxa ROCK 5A](https://wiki.radxa.com/Rock5/hardware/5a)
+- [Orange Pi 5](http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-5.html)
+- [ameriDroid Indiedroid Nova](https://indiedroid.us)
+- [Firefly ROC-RK3588S-PC](https://en.t-firefly.com/product/industry/rocrk3588spc)
+- [StationPC Station M3](https://www.stationpc.com/product/stationm3)
+- [Mekotronics R58X](https://www.mekotronics.com/h-pd-75.html)
+- [Mekotronics R58 Mini](https://www.mekotronics.com/h-pd-76.html)
+- [Khadas Edge2](https://www.khadas.com/edge2)
+- [FriendlyELEC NanoPC T6](https://wiki.friendlyelec.com/wiki/index.php/NanoPC-T6)

-## Description
+## Supported peripherals
+Applicable to all platforms unless otherwise noted.

-This repository is based on the official open-source UEFI implementation from Rockchip, which is under active development.
+| Device | Status | Notes |
+| --- | --- | --- |
+| USB 3 / 2.0 / 1.1                  | 🟢 Working     | Host-mode only |
+| PCIe 3.0 (RK3588)                  | 🟡 Partial     | |
+| PCIe 2.1                           | 🔴 Not working | |
+| SATA                               | 🟢 Working     | |
+| SD/eMMC                            | 🟢 Working     | |
+| HDMI output                        | 🟢 Working     | Single display with mode limited at 1080p 60 Hz |
+| USB-C DP output                    | 🔴 Not working | |
+| eDP output                         | 🔴 Not working | |
+| DSI                                | 🔴 Not working | |
+| GMAC Ethernet                      | 🔴 Not working | |
+| UART                               | 🟢 Working     | |
+| GPIO                               | 🟡 Partial     | No pin function support |
+| I2C                                | 🟢 Working     | |
+| SPI                                | 🟢 Working     | |
+| SARADC                             | 🔴 Not working | |
+| PWM                                | ⚪ Untested    | |
+| SPI NOR Flash                      | 🟢 Working     | |
+| Voltage regulators (RK806, RK860)  | 🟢 Working     | |
+| FUSB302 USB-C PD negotiation       | 🔴 Not working | Only present on a few boards (ROCK 5B, Edge2) |

-Therefore, to keep up with the work from Rockchip, we should avoid modifying code from Rockchip in most cases.
+## Supported OSes
+| OS | Version | Tested/supported hardware | Notes |
+| --- | --- | --- | --- |
+| Windows | 10 (1904x), 11 | [Status](https://github.com/worproject/Rockchip-Windows-Drivers#hardware-support-status) ||
+| NetBSD | 10 | HDMI GOP, USB, SATA, UART ||
+| VMware ESXi Arm Fling | 1.12 | HDMI GOP, USB |Need to hide PCIe 3 in ACPI|

-Discussion thread: [Windows / UEFI on Rock 5 (Mega thread)](https://forum.radxa.com/t/windows-uefi-on-rock-5-mega-thread/12924)
+## Installation & usage
+Check out the latest release at: <https://github.com/edk2-porting/edk2-rk35xx/releases>, including install instructions.
+
+## Configuration settings
+The UEFI configuration settings can be viewed and changed using both the UI configuration menu (under `Device Manager` -> `Rockchip Platform Configuration`), as well as the UEFI Shell. To configure using the UEFI Shell, use `setvar` command to read/write the UEFI variables with GUID = `10f41c33-a468-42cd-85ee-7043213f73a3`.
+
+The syntax to read a setting is:
+```
+setvar <NAME> -guid 10f41c33-a468-42cd-85ee-7043213f73a3
+```
+
+The syntax to write a setting is:
+```
+setvar <NAME> -guid 10f41c33-a468-42cd-85ee-7043213f73a3 -bs -rt -nv =<VALUE>
+```
+`VALUE` must be in hexadecimal.
+
+For string-type settings, the syntax to write is:
+```
+setvar <NAME> -guid 10f41c33-a468-42cd-85ee-7043213f73a3 -bs -rt -nv =L"<VALUE>" =0x0000
+```
+
+### CPU Performance
+#### Cluster clocks / voltages
+| Variable                          |    NAME                            |  VALUE                       |
+| --------------------------------- |----------------------------------- |----------------------------- |
+| CPU`x` Clock Preset               | `CpuPerf_CPUxClusterClockPreset`   | Boot default = `0x00000000`<br> Min = `0x00000001`<br> Max = `0x00000002`<br> Custom = `0x00000003` |
+| CPU`x` Custom Clock Preset (MHz)  | `CpuPerf_CPUxClusterClockCustom`   | Hex numeric option, 4-bytes<br> See below. |
+| CPU`x` Voltage Mode               | `CpuPerf_CPUxClusterVoltageMode`   | Auto = `0x00000000` (default)<br> Custom = `0x00000001`|
+| CPU`x` Custom Voltage (uV)        | `CpuPerf_CPUxClusterVoltageCustom` | Hex numeric value, 4-bytes<br> See below. |
+
+`x` can be :
+* `L` for LITTLE cluster
+* `B01` for big cluster #0
+* `B23` for big cluster #1
+
+`CpuPerf_CPUxClusterClockCustom` can have one of the following values:
+* All clusters: `408000000`, `600000000`, `816000000`, `1008000000`, `1200000000`, `1416000000`, `1608000000`, `1800000000`
+* Big cluster additional clocks: `2016000000`, `2208000000`, `2256000000`, `2304000000`, `2352000000`, `2400000000`
+
+`CpuPerf_CPUxClusterVoltageCustom` is the cluster voltage in microvolts. Min: `500000`, Max: `1500000`. 
+Default value depends on cluster type.
+
+### PCIe/SATA/USB Combo PIPE PHY
+| Variable    |    NAME         |  VALUE                       |
+| ----------- |-----------------|----------------------------------- |
+| PHY #0 Mode | `ComboPhy0Mode` | Unconnected = `0x00000000`<br> PCIe = `0x00000001`<br> SATA = `0x00000002` |
+| PHY #1 Mode | `ComboPhy1Mode` | Unconnected = `0x00000000`<br> PCIe = `0x00000001`<br> SATA = `0x00000002` |
+| PHY #2 Mode | `ComboPhy2Mode` | Unconnected = `0x00000000`<br> PCIe = `0x00000001`<br> SATA = `0x00000002`<br> USB3 = `0x00000003` |
+
+Default values and supported options depend on the platform. Check documentation and schematics for more details on PHY wiring.
+
+**Examples:**
+- To read the 'CPUL Clock Preset' setting :
+```
+setvar CpuPerf_CPULClusterClockPreset -guid 10f41c33-a468-42cd-85ee-7043213f73a3
+```
+
+- To change the 'CPUL Clock Preset' setting to 'Maximum' :
+```
+setvar CpuPerf_CPULClusterClockPreset -guid 10f41c33-a468-42cd-85ee-7043213f73a3 -bs -rt -nv =0x00000002
+```

 ## Building
+The firmware can only be built on Linux currently. For Windows use WSL.

-Using Arch Linux as example
+1. Install required packages:

-Install required packages:
-```bash
-sudo pacman -Syu
-sudo pacman -S git base-devel gcc dtc aarch64-linux-gnu-binutils aarch64-linux-gnu-gcc aarch64-linux-gnu-glibc python python-pyelftools iasl --needed
-```
+   For Ubuntu/Debian:
+   ```bash
+   sudo apt install git gcc g++ build-essential gcc-aarch64-linux-gnu iasl python3-pyelftools
+   ```
+   For Arch Linux:
+   ```bash
+   sudo pacman -Syu
+   sudo pacman -S git base-devel gcc dtc aarch64-linux-gnu-binutils aarch64-linux-gnu-gcc aarch64-linux-gnu-glibc python python-pyelftools iasl --needed
+   ```

-Required packages for Ubuntu/Debian:
-```bash
-sudo apt install git gcc g++ build-essential gcc-aarch64-linux-gnu iasl python3-pyelftools
-```
+2. Clone the repository:
+   ```bash
+   git clone https://github.com/edk2-porting/edk2-rk35xx.git --recursive
+   cd edk2-rk35xx
+   ```

-Clone the repository:
-```bash
-git clone https://github.com/edk2-porting/edk2-rk35xx.git --recursive
-cd edk2-rk35xx
-```
-
-Build UEFI (ROCK 5B for example):
-```bash
-./build.sh -d rock-5b
-```
-
-## TODO
- - Create gpt image in build process instead of using the prebuilt one
- - Fix resetting to maskrom
+3. Build UEFI (ROCK 5B for example, check [list of platform configs](https://github.com/edk2-porting/edk2-rk35xx/tree/master/configs)):
+   ```bash
+   ./build.sh --device rock-5b --release Release # (or Debug)
+   ```

 ## Notes
+### ACPI
+ACPI support is limited, with only boot critical devices being currently exposed. It has been tested with Windows, NetBSD and VMware ESXi.

 ### Flash layout
-
 | Address    | Size       | Desc                  | File                   |
-| ---------- | :--------- | --------------------- | ---------------------- |
+| ---------- | ---------- | --------------------- | ---------------------- |
 | 0x00000000 | 0x00004400 | GPT Table             | rk3588_spi_nor_gpt.img |
 | 0x00008000 |            | IDBlock               | idblock.bin            |
 | 0x00088000 |            | IDBlock               | idblock.bin            |
 | 0x00100000 | 0x00500000 | BL33_AP_UEFI FV       | ${DEVICE}_EFI.itb      |
-| 0x007C0000 | 0x00010000 | NV_VARIABLE_STORE     |                        |
-| 0x007D0000 | 0x00010000 | NV_FTW_WORKING header |                        |
-| 0x007E0000 | 0x00010000 | NV_FTW_WORKING data   | NV_DATA.img            |

 ### Memory Map
+| Address    | Size       | Desc                  | File                |
+| ---------- | ---------  | --------------------- | ------------------- |
+| 0x00040000 |            | ATF                   | bl31_0x00040000.bin |
+| 0x000f0000 |            | ATF                   | bl31_0x000f0000.bin |
+| 0x00200000 | 0x00500000 | UEFI FV               | BL33_AP_UEFI.Fv     |
+| 0x007C0000 | 0x00010000 | NV_VARIABLE_STORE     |                     |
+| 0x007D0000 | 0x00010000 | NV_FTW_WORKING        |                     |
+| 0x007E0000 | 0x00010000 | NV_FTW_SPARE          |                     |
+| 0x08400000 |            | OP-TEE                | bl32.bin            |
+| 0xff100000 |            | ATF (PMU_MEM)         | bl31_0xff100000.bin |

-| Address    | Size | Desc          | File                |
-| ---------- | :--: | ------------- | ------------------- |
-| 0x00040000 |      | ATF           | bl31_0x00040000.bin |
-| 0x000f0000 |      | ATF           | bl31_0x000f0000.bin |
-| 0x00200000 |      | UEFI FV       | BL33_AP_UEFI.Fv     |
-| 0x08400000 |      | OP-TEE        | bl32.bin            |
-| 0xff100000 |      | ATF (PMU_MEM) | bl31_0xff100000.bin |
+## Licenses
+The UEFI code and produced FD binary are licensed under the current EDK2 license, which is [BSD-2-Clause-Patent](https://github.com/tianocore/edk2/blob/master/License.txt).
+
+The license of the blobs in the `misc/rkbin/` directory is to be determined. Most of them are built from open-source projects such as U-Boot, Arm Trusted Firmware and OP-TEE.
+
+## Community
+* Radxa forum: <https://forum.radxa.com/t/windows-uefi-on-rock-5-mega-thread/12924>
+* Hack w/ Rockchip Telegram: <https://t.me/UEFIonRockchip>
+* Windows on R Discord: <https://discord.gg/vjHwptUCa3>
+
+## Credits & alternatives
+This firmware is based on Rockchip's initial efforts at <https://gitlab.com/rk3588_linux/rk/uefi-monorepo>.
+
+There's also minimal support for RK356X (likely broken in our repo with no plans of reviving), but there's a much better implementation made by @jaredmcneill at https://github.com/jaredmcneill/quartz64_uefi, from which we also reused some code.
--- a/build.sh
+++ b/build.sh
@@ -8,6 +8,7 @@ function _help(){
 	echo "Options: "
 	echo "	--device DEV, -d DEV:    build for DEV."
 	echo "	--all, -a:               build all devices."
+	echo "	--gui:                   Enable simple-init GUI."
 	echo "	--release MODE, -r MODE: Release mode for building, default is 'DEBUG', 'RELEASE' alternatively."
 	echo "	--toolchain TOOLCHAIN:   Set toolchain, default is 'GCC5'."
 	echo " 	--skip-rootfs-gen:       skip generating SimpleInit rootfs to speed up building."
@@ -58,8 +59,6 @@ function _pack(){
 	echo " => Building 8MB NOR FLASH IMAGE"
 	cp ${WORKSPACE}/Build/${PLATFORM_NAME}/${_MODE}_${TOOLCHAIN}/FV/NOR_FLASH_IMAGE.fd ${WORKSPACE}/RK3588_NOR_FLASH.img

-	# backup NV_DATA at 0x007C0000
-	dd if=${WORKSPACE}/RK3588_NOR_FLASH.img of=${WORKSPACE}/NV_DATA.img bs=1K skip=7936
 	# might be GPT table? size:0x4400
 	dd if=${ROOTDIR}/misc/rk3588_spi_nor_gpt.img of=${WORKSPACE}/RK3588_NOR_FLASH.img
 	# idblock at 0x8000 and 0x88000
@@ -67,8 +66,6 @@ function _pack(){
 	dd if=${WORKSPACE}/idblock.bin of=${WORKSPACE}/RK3588_NOR_FLASH.img bs=1K seek=544
 	# FIT Image at 0x100000
 	dd if=${WORKSPACE}/${DEVICE}_EFI.itb of=${WORKSPACE}/RK3588_NOR_FLASH.img bs=1K seek=1024
-	# restore NV_DATA at 0x007C0000
-	dd if=${WORKSPACE}/NV_DATA.img of=${WORKSPACE}/RK3588_NOR_FLASH.img bs=1K seek=7936
 	cp ${WORKSPACE}/RK3588_NOR_FLASH.img ${ROOTDIR}/
 }

@@ -109,6 +106,8 @@ function _build(){
 		-p "${ROOTDIR}/${DSC_FILE}" \
 		-b "${_MODE}" \
 		-D FIRMWARE_VER="${GITCOMMIT}" \
+		-D ENABLE_SIMPLE_INIT="${BUILD_GUI}" \
+		-D CONFIG_SOC="${SOC}" \
 		||return "$?"

 	_pack
@@ -117,7 +116,7 @@ function _build(){
 	echo "Build done: RK3588_NOR_FLASH.img"
 }

-function _clean(){ rm --one-file-system --recursive --force "${WORKSPACE}" "${OUTDIR}"/boot-*.img "${OUTDIR}"/uefi-*.img*; }
+function _clean(){ rm --one-file-system --recursive --force "${OUTDIR}"/workspace "${OUTDIR}"/RK3588_*.img "${OUTDIR}"/uefi-*.img*; }

 function _distclean(){ if [ -d .git ];then git clean -xdf;else _clean;fi; }

@@ -133,7 +132,8 @@ DISTCLEAN=false
 TOOLCHAIN=GCC5
 export ROOTDIR OUTDIR
 export GEN_ROOTFS=true
-OPTS="$(getopt -o t:d:haCDO:r -l toolchain:,device:,help,all,skip-rootfs-gen,clean,distclean,outputdir:,release: -n 'build.sh' -- "$@")"||exit 1
+export BUILD_GUI=false
+OPTS="$(getopt -o t:d:haCDO:r -l toolchain:,device:,help,all,skip-rootfs-gen,gui,clean,distclean,outputdir:,release: -n 'build.sh' -- "$@")"||exit 1
 eval set -- "${OPTS}"
 while true
 do	case "${1}" in
@@ -143,6 +143,7 @@ do	case "${1}" in
 		-D|--distclean) DISTCLEAN=true;shift;;
 		-O|--outputdir) OUTDIR="${2}";shift 2;;
 		--skip-rootfs-gen) GEN_ROOTFS=false;shift;;
+		--gui) BUILD_GUI=true;shift;;
 		-r|--release) MODE="${2}";shift 2;;
 		-t|--toolchain) TOOLCHAIN="${2}";shift 2;;
 		-h|--help) _help 0;shift;;
@@ -170,8 +171,8 @@ do
 	fi
 done

-[ -n "${_SIMPLE_INIT}" ]||_error "SimpleInit not found, please see README.md"
-[ -f "configs/${DEVICE}.conf" ]||_error "Device configuration not found"
+[ -n "${_SIMPLE_INIT}" ]||[ ${BUILD_GUI} == false ]_error "SimpleInit not found, please see README.md"
+[ -f "configs/${DEVICE}.conf" ]||[ "${DEVICE}" == "all" ]||_error "Device configuration not found"

 export CROSS_COMPILE="${CROSS_COMPILE:-aarch64-linux-gnu-}"
 export GCC5_AARCH64_PREFIX="${CROSS_COMPILE}"
@@ -206,8 +207,11 @@ then
 	for i in configs/*.conf
 	do
 		DEV="$(basename "$i" .conf)"
-		echo "Building ${DEV}"
-		_build "${DEV}"||E="$?"
+		if [ "${DEV}" != "RK3588" ]&&[ "${DEV}" != "RK3568" ]
+		then
+			echo "Building ${DEV}"
+			_build "${DEV}"||E="$?"
+		fi
 	done
 	exit "${E}"
 else
--- a/configs/edge2.conf
+++ b/configs/edge2.conf
@@ -0,0 +1,3 @@
+DSC_FILE=edk2-platforms/Platform/Khadas/Edge2/Edge2.dsc
+PLATFORM_NAME=Edge2
+SOC=RK3588
--- a/configs/indiedroid-nova.conf
+++ b/configs/indiedroid-nova.conf
@@ -0,0 +1,3 @@
+DSC_FILE=edk2-platforms/Platform/Ameridroid/IndiedroidNova/IndiedroidNova.dsc
+PLATFORM_NAME=IndiedroidNova
+SOC=RK3588
--- a/configs/nanopc-t6.conf
+++ b/configs/nanopc-t6.conf
@@ -0,0 +1,3 @@
+DSC_FILE=edk2-platforms/Platform/FriendlyElec/NanoPC-T6/NanoPC-T6.dsc
+PLATFORM_NAME=NanoPC-T6
+SOC=RK3588
--- a/configs/orangepi-5.conf
+++ b/configs/orangepi-5.conf
@@ -0,0 +1,3 @@
+DSC_FILE=edk2-platforms/Platform/OrangePi/OrangePi5/OrangePi5.dsc
+PLATFORM_NAME=OrangePi5
+SOC=RK3588
--- a/configs/r58-mini.conf
+++ b/configs/r58-mini.conf
@@ -0,0 +1,3 @@
+DSC_FILE=edk2-platforms/Platform/Mekotronics/R58-Mini/R58-Mini.dsc
+PLATFORM_NAME=R58-Mini
+SOC=RK3588
--- a/configs/r58x.conf
+++ b/configs/r58x.conf
@@ -0,0 +1,3 @@
+DSC_FILE=edk2-platforms/Platform/Mekotronics/R58X/R58X.dsc
+PLATFORM_NAME=R58X
+SOC=RK3588
--- a/configs/roc-rk3588s-pc.conf
+++ b/configs/roc-rk3588s-pc.conf
@@ -0,0 +1,3 @@
+DSC_FILE=edk2-platforms/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc
+PLATFORM_NAME=ROC-RK3588S-PC
+SOC=RK3588
--- a/configs/rock-5a.conf
+++ b/configs/rock-5a.conf
@@ -0,0 +1,3 @@
+DSC_FILE=edk2-platforms/Platform/Radxa/ROCK5A/ROCK5A.dsc
+PLATFORM_NAME=ROCK5A
+SOC=RK3588
--- a/configs/station-m3.conf
+++ b/configs/station-m3.conf
@@ -0,0 +1,3 @@
+DSC_FILE=edk2-platforms/Platform/StationPC/StationM3/StationM3.dsc
+PLATFORM_NAME=StationM3
+SOC=RK3588
--- a/edk2-platforms/Platform/Ameridroid/Drivers/LogoDxe/Logo.bmp
+++ b/edk2-platforms/Platform/Ameridroid/Drivers/LogoDxe/Logo.bmp
--- a/edk2-platforms/Platform/Ameridroid/Drivers/LogoDxe/Logo.c
+++ b/edk2-platforms/Platform/Ameridroid/Drivers/LogoDxe/Logo.c
@@ -0,0 +1,144 @@
+/** @file
+  Logo DXE Driver, install Edkii Platform Logo protocol.
+
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+  Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Protocol/HiiDatabase.h>
+#include <Protocol/GraphicsOutput.h>
+#include <Protocol/HiiImageEx.h>
+#include <Protocol/PlatformLogo.h>
+#include <Protocol/HiiPackageList.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+
+typedef struct {
+  EFI_IMAGE_ID                          ImageId;
+  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
+  INTN                                  OffsetX;
+  INTN                                  OffsetY;
+} LOGO_ENTRY;
+
+STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
+STATIC EFI_HII_HANDLE            mHiiHandle;
+STATIC LOGO_ENTRY                mLogos[] = {
+  {
+    IMAGE_TOKEN (IMG_LOGO),
+    EdkiiPlatformLogoDisplayAttributeCenter,
+    0,
+    0
+  }
+};
+
+/**
+  Load a platform logo image and return its data and attributes.
+
+  @param This              The pointer to this protocol instance.
+  @param Instance          The visible image instance is found.
+  @param Image             Points to the image.
+  @param Attribute         The display attributes of the image returned.
+  @param OffsetX           The X offset of the image regarding the Attribute.
+  @param OffsetY           The Y offset of the image regarding the Attribute.
+
+  @retval EFI_SUCCESS      The image was fetched successfully.
+  @retval EFI_NOT_FOUND    The specified image could not be found.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GetImage (
+  IN     EDKII_PLATFORM_LOGO_PROTOCOL          *This,
+  IN OUT UINT32                                *Instance,
+     OUT EFI_IMAGE_INPUT                       *Image,
+     OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
+     OUT INTN                                  *OffsetX,
+     OUT INTN                                  *OffsetY
+  )
+{
+  UINT32 Current;
+
+  if (Instance == NULL || Image == NULL ||
+      Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Current = *Instance;
+  if (Current >= ARRAY_SIZE (mLogos)) {
+    return EFI_NOT_FOUND;
+  }
+
+  (*Instance)++;
+  *Attribute = mLogos[Current].Attribute;
+  *OffsetX   = mLogos[Current].OffsetX;
+  *OffsetY   = mLogos[Current].OffsetY;
+
+  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
+                        mLogos[Current].ImageId, Image);
+}
+
+STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+  GetImage
+};
+
+/**
+  Entrypoint of this module.
+
+  This function is the entrypoint of this module. It installs the Edkii
+  Platform Logo protocol.
+
+  @param  ImageHandle       The firmware allocated handle for the EFI image.
+  @param  SystemTable       A pointer to the EFI System Table.
+
+  @retval EFI_SUCCESS       The entry point is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeLogo (
+  IN EFI_HANDLE               ImageHandle,
+  IN EFI_SYSTEM_TABLE         *SystemTable
+  )
+{
+  EFI_STATUS                  Status;
+  EFI_HII_PACKAGE_LIST_HEADER *PackageList;
+  EFI_HII_DATABASE_PROTOCOL   *HiiDatabase;
+  EFI_HANDLE                  Handle;
+
+  Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
+                  (VOID **) &HiiDatabase);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
+                  (VOID **) &mHiiImageEx);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Retrieve HII package list from ImageHandle
+  //
+  Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
+                  (VOID **) &PackageList, ImageHandle, NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR,
+      "HII Image Package with logo not found in PE/COFF resource section\n"));
+    return Status;
+  }
+
+  //
+  // Publish HII package list to HII Database.
+  //
+  Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
+                          &mHiiHandle);
+  if (!EFI_ERROR (Status)) {
+    Handle = NULL;
+    Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
+                    &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
+  }
+  return Status;
+}
--- a/edk2-platforms/Platform/Ameridroid/Drivers/LogoDxe/Logo.idf
+++ b/edk2-platforms/Platform/Ameridroid/Drivers/LogoDxe/Logo.idf
@@ -0,0 +1,10 @@
+// @file
+// Platform Logo image definition file.
+//
+// Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+// Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+
+#image IMG_LOGO Logo.bmp
--- a/edk2-platforms/Platform/Ameridroid/Drivers/LogoDxe/LogoDxe.inf
+++ b/edk2-platforms/Platform/Ameridroid/Drivers/LogoDxe/LogoDxe.inf
@@ -0,0 +1,48 @@
+## @file
+#  The default logo bitmap picture shown on setup screen.
+#
+#  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+#  Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = LogoDxe
+  FILE_GUID                      = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = InitializeLogo
+#
+#  This flag specifies whether HII resource section is generated into PE image.
+#
+  UEFI_HII_RESOURCE_SECTION      = TRUE
+
+[Sources]
+  Logo.bmp
+  Logo.c
+  Logo.idf
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  DebugLib
+
+[Protocols]
+  gEfiHiiDatabaseProtocolGuid        ## CONSUMES
+  gEfiHiiImageExProtocolGuid         ## CONSUMES
+  gEfiHiiPackageListProtocolGuid     ## PRODUCES CONSUMES
+  gEdkiiPlatformLogoProtocolGuid     ## PRODUCES
+
+[Depex]
+  gEfiHiiDatabaseProtocolGuid AND
+  gEfiHiiImageExProtocolGuid
--- a/edk2-platforms/Platform/Ameridroid/IndiedroidNova/AcpiTables/AcpiTables.inf
+++ b/edk2-platforms/Platform/Ameridroid/IndiedroidNova/AcpiTables/AcpiTables.inf
@@ -0,0 +1,64 @@
+#/** @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2019-2021, ARM Limited. All rights reserved.
+#  Copyright (c) Microsoft Corporation. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+  RK_COMMON_ACPI_DIR             = Silicon/Rockchip/RK3588/AcpiTables
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+
+[Sources]
+  Dsdt.asl
+  $(RK_COMMON_ACPI_DIR)/Madt.aslc
+  $(RK_COMMON_ACPI_DIR)/Fadt.aslc
+  $(RK_COMMON_ACPI_DIR)/Gtdt.aslc
+  $(RK_COMMON_ACPI_DIR)/Spcr.aslc
+  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
+  $(RK_COMMON_ACPI_DIR)/RK3588PcieIort.aslc
+  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Rockchip/RockchipPkg.dec
+  Platform/Rockchip/RK3588/RK3588.dec
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
--- a/edk2-platforms/Platform/Ameridroid/IndiedroidNova/AcpiTables/Dsdt.asl
+++ b/edk2-platforms/Platform/Ameridroid/IndiedroidNova/AcpiTables/Dsdt.asl
@@ -0,0 +1,38 @@
+/** @file
+ *
+ *  Differentiated System Definition Table (DSDT)
+ *
+ *  Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ *  Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
+ *  Copyright (c) Microsoft Corporation. All rights reserved.
+ *  Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include "AcpiTables.h"
+
+DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
+{
+  Scope (\_SB_)
+  {
+    include ("Cpu.asl")
+
+    // include ("Pcie.asl")
+    // include ("Sata.asl")
+    include ("Emmc.asl")
+    include ("Sdhc.asl")
+    // include ("Gmac.asl")
+    // include ("Gpio.asl")
+    // include ("I2c.asl")
+    include ("Uart.asl")
+    // include ("Spi.asl")
+
+    // won't work on Windows, will trigger bugcheck by usbehci
+    // include ("Usb2.asl")
+
+    include ("Usb3Host0.asl")
+    include ("Usb3Host2.asl")
+  }
+}
--- a/edk2-platforms/Platform/Ameridroid/IndiedroidNova/IndiedroidNova.dsc
+++ b/edk2-platforms/Platform/Ameridroid/IndiedroidNova/IndiedroidNova.dsc
@@ -0,0 +1,633 @@
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2021-2022, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = IndiedroidNova
+  PLATFORM_GUID                  = d080df36-45e7-11ec-9726-f42a7dcb925d
+  PLATFORM_VERSION               = 0.2
+  DSC_SPECIFICATION              = 0x00010019
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = Platform/Ameridroid/IndiedroidNova/IndiedroidNova.fdf
+
+  DEFINE CONFIG_NO_DEBUGLIB      = TRUE
+
+  #
+  # Must match defines in Silicon/Rockchip/RK3588/Include/VarStoreData.h
+  #
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT  = 0
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_MIN          = 1
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_MAX          = 2
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_CUSTOM       = 3
+
+  DEFINE COMBO_PHY_MODE_UNCONNECTED   = 0
+  DEFINE COMBO_PHY_MODE_PCIE          = 1
+  DEFINE COMBO_PHY_MODE_SATA          = 2
+  DEFINE COMBO_PHY_MODE_USB3          = 3
+
+  #
+  # Network definition
+  #
+  DEFINE NETWORK_SNP_ENABLE             = FALSE
+  DEFINE NETWORK_IP6_ENABLE             = FALSE
+  DEFINE NETWORK_TLS_ENABLE             = FALSE
+  DEFINE NETWORK_HTTP_BOOT_ENABLE       = FALSE
+  DEFINE NETWORK_ISCSI_ENABLE           = FALSE
+  DEFINE NETWORK_VLAN_ENABLE            = FALSE
+!include Silicon/Rockchip/Rockchip.dsc.inc
+!include MdePkg/MdeLibs.dsc.inc
+
+[LibraryClasses.common]
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmPlatformLib|Silicon/Rockchip/RK3588/Library/PlatformLib/PlatformLib.inf
+  AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf
+  CruLib|Silicon/Rockchip/Library/CruLib/CruLib.inf
+
+  DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
+
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+  # UiApp dependencies
+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+
+  #RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+  TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
+
+  # USB Requirements
+  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+
+  # PCIe
+  PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+  #PciHostBridgeLib|Silicon/Rockchip/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+  #PciExpressLib|Silicon/Rockchip/Library/PciExpressLib/PciExpressLib.inf
+  PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+
+
+  # VariableRuntimeDxe Requirements
+  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+  AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+  TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+  VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+
+  AndroidBootImgLib|edk2/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.inf
+
+  RockchipDisplayLib|Silicon/Rockchip/Library/DisplayLib/RockchipDisplayLib.inf
+
+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+  LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf
+
+  # OTP Library
+  OtpLib|Silicon/Rockchip/RK3588/Library/OtpLib/OtpLib.inf
+
+  #
+  # Custom libraries
+  #
+  RockchipPlatformLib|Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+  ResetSystemLib|Silicon/Rockchip/Library/ResetSystemLib/ResetSystemLib.inf
+  PlatformBootManagerLib|Silicon/Rockchip/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+  SerialPortLib|Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf
+  GpioLib|Silicon/Rockchip/RK3588/Library/GpioLib/GpioLib.inf
+  # SCMI Mailbox Transport Layer
+  ArmMtlLib|Silicon/Rockchip/Library/RkMtlLib/RkMtlLib.inf
+
+[LibraryClasses.common.SEC]
+  PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+  ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+  HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
+  MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+  MemoryInitPeiLib|Silicon/Rockchip/RK3588/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
+  PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+  PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+  RockchipPlatformLib|Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+
+[BuildOptions]
+  GCC:*_*_*_PLATFORM_FLAGS = -I$(WORKSPACE)/Silicon/Rockchip/RK3588/Include -I$(WORKSPACE)/Platform/Rockchip/RK3588/Include -I$(WORKSPACE)/Silicon/Rockchip/Include
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+  #  If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+  #  It could be set FALSE to save size.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+
+[PcdsFixedAtBuild.common]
+  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)"
+
+  # System Memory (1GB)
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000
+  gRK3588TokenSpaceGuid.PcdTotalMemorySize|0x200000000
+  
+  # RK3588 CPU profile
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|8
+  gArmPlatformTokenSpaceGuid.PcdClusterCount|1
+
+  # SMBIOS platform config
+  gRockchipTokenSpaceGuid.PcdPlatformName|"Indiedroid Nova"
+  gRockchipTokenSpaceGuid.PcdPlatformVendorName|"ameriDroid"
+  gRockchipTokenSpaceGuid.PcdFamilyName|"Indiedroid"
+  gRockchipTokenSpaceGuid.PcdProductUrl|"http://indiedroid.us"
+  gRockchipTokenSpaceGuid.PcdMemoryVendorName|"TBD"
+
+  # I2C
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 }
+  gRockchipTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0 }
+  gRockchipTokenSpaceGuid.PcdI2cClockFrequency|198000000
+  gRockchipTokenSpaceGuid.PcdI2cBaudRate|100000
+  gRockchipTokenSpaceGuid.PcdI2cBusCount|1
+  gRockchipTokenSpaceGuid.PcdI2cDemoAddresses|{ 0x51 } #/* RTCYM8563TS 0x51@bus2 */
+  gRockchipTokenSpaceGuid.PcdI2cDemoBuses|{ 0x2 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ 2, 3 } # SCMI_CLK_CPUB01, SCMI_CLK_CPUB23
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorMinVoltages|{ UINT32(550000), UINT32(550000) }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorMaxVoltages|{ UINT32(1050000), UINT32(1050000) }
+
+  ## UART2 - Serial Terminal
+  DEFINE SERIAL_BASE = 0xFEB50000 # UART2
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|$(SERIAL_BASE)
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|1500000
+  gHisiTokenSpaceGuid.PcdSerialPortSendDelay|500000
+  gHisiTokenSpaceGuid.PcdUartClkInHz|24000000
+
+  ## SPI - SPI2 for test
+  gRockchipTokenSpaceGuid.SpiTestBaseAddr|0xFEB20000
+  gRockchipTokenSpaceGuid.SpiRK806BaseAddr|0xFEB20000
+  ## PL031 RealTimeClock
+  #gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0xF8003000
+
+  ## NOR FLASH
+  gRockchipTokenSpaceGuid.FspiBaseAddr|0xFE2B0000
+
+  ## CRU
+  gRockchipTokenSpaceGuid.CruBaseAddr|0xFD7C0000
+
+  #gRockchipTokenSpaceGuid.PcdSpiVariableOffset|0x3C0000
+  #
+  # ARM General Interrupt Controller
+  #
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0xfe600000
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xfe600000
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0xfe680000
+
+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3
+
+  # GUID of the UI app
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+
+  gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
+
+  #
+  # DW SD card controller
+  #
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeBaseAddress|0xfe2c0000
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz|100000000
+  gDesignWareTokenSpaceGuid.PcdDwPermitObsoleteDrivers|TRUE
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeFifoDepth|256
+  #
+  # SDHCI controller
+  #
+  gRockchipTokenSpaceGuid.PcdSdhciDxeBaseAddress|0xfe2e0000
+
+  #
+  # PCIe controller
+  #
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress|0xfe150000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress|0xf5000000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress|0xf0000000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize|0x100000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress|0xf0100000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize|0x10000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress|0xf0200000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize|0xe00000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64|0x901000000 #deduct 0x1000000 ECAM space
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64|0x3f000000
+
+  #
+  # Fastboot
+  #
+  gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbVendorId|0x2207
+  gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbProductId|0x0001
+
+  #
+  # USB2 EHCI + OHCI companion controllers
+  #
+  gRockchipTokenSpaceGuid.PcdEhciBaseAddress|0xfc800000
+  gRockchipTokenSpaceGuid.PcdNumEhciController|2
+  gRockchipTokenSpaceGuid.PcdEhciSize|0x40000
+  gRockchipTokenSpaceGuid.PcdOhciSize|0x40000
+
+  #
+  # DWC3 controller
+  #
+  gRockchipTokenSpaceGuid.PcdDwc3BaseAddresses|{ UINT32(0xfc000000), UINT32(0xfc400000), UINT32(0xfcd00000) }
+  gRockchipTokenSpaceGuid.PcdDwc3Size|0x400000
+
+  #
+  # Android Loader
+  #
+  gRK3588TokenSpaceGuid.PcdAndroidBootDevicePath|L"\\EFI\\BOOT\\GRUBAA64.EFI"
+  gRK3588TokenSpaceGuid.PcdSdBootDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00E023F70000000000)/SD(0x0)"
+  gRK3588TokenSpaceGuid.PcdKernelBootArg|L"earlycon=uart8250,mmio32,0xfeb50000 root=PARTUUID=614e0000-0000 rw rootwait"
+  gEmbeddedTokenSpaceGuid.PcdAndroidBootDevicePath|L"VenHw(100C2CFA-B586-4198-9B4C-1683D195B1DA)/HD(3,GPT,7A3F0000-0000-446A-8000-702F00006273,0x8000,0x20000)"
+
+  # ACPI Enable
+  gRK3588TokenSpaceGuid.AcpiEnable|TRUE
+
+  #
+  # Display
+  #
+  gRockchipTokenSpaceGuid.PcdLcdPixelFormat|0x00000001
+  gRockchipTokenSpaceGuid.PcdEdpId|0x00000000 #edp0
+  #gRockchipTokenSpaceGuid.PcdEdpId|0x00000001 #edp1
+  gRockchipTokenSpaceGuid.PcdHdmiId|0x00000000 #hdmi0
+  #gRockchipTokenSpaceGuid.PcdHdmiId|0x00000001 #hdmi1
+
+  #
+  # CPU Performance default values
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX)
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX)
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX)
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|FALSE
+  gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|FALSE
+  gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|FALSE
+  gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE)
+  gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_UNCONNECTED)
+  gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3)
+
+  #  BIT0  - Initialization message.<BR>
+  #  BIT1  - Warning message.<BR>
+  #  BIT2  - Load Event message.<BR>
+  #  BIT3  - File System message.<BR>
+  #  BIT4  - Allocate or Free Pool message.<BR>
+  #  BIT5  - Allocate or Free Page message.<BR>
+  #  BIT6  - Information message.<BR>
+  #  BIT7  - Dispatcher message.<BR>
+  #  BIT8  - Variable message.<BR>
+  #  BIT10 - Boot Manager message.<BR>
+  #  BIT12 - BlockIo Driver message.<BR>
+  #  BIT14 - Network Driver message.<BR>
+  #  BIT16 - UNDI Driver message.<BR>
+  #  BIT17 - LoadFile message.<BR>
+  #  BIT19 - Event message.<BR>
+  #  BIT20 - Global Coherency Database changes message.<BR>
+  #  BIT21 - Memory range cachability changes message.<BR>
+  #  BIT22 - Detailed debug message.<BR>
+  #  BIT31 - Error message.<BR>
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0e
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000000
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0f
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x800B0507
+!endif
+# 0x800B05C7
+# Use 0x807B55FF to enable all debug messages
+
+[PcdsDynamicDefault.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x007C0000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x007CF000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x007D0000
+
+  #
+  # Display
+  #
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x780
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x438
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0
+
+[PcdsDynamicHii.common.DEFAULT]
+  #
+  # CPU Performance
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPreset|L"CpuPerf_CPULClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockCustom|L"CpuPerf_CPULClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|1800
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPreset|L"CpuPerf_CPUB01ClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockCustom|L"CpuPerf_CPUB01ClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|2400
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPreset|L"CpuPerf_CPUB23ClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockCustom|L"CpuPerf_CPUB23ClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|2400
+  gRK3588TokenSpaceGuid.PcdCPULClusterVoltageMode|L"CpuPerf_CPULClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0
+  gRK3588TokenSpaceGuid.PcdCPULClusterVoltageCustom|L"CpuPerf_CPULClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|950000
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterVoltageMode|L"CpuPerf_CPUB01ClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterVoltageCustom|L"CpuPerf_CPUB01ClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|1000000
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterVoltageMode|L"CpuPerf_CPUB23ClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterVoltageCustom|L"CpuPerf_CPUB23ClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|1000000
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY
+  #
+  gRK3588TokenSpaceGuid.PcdComboPhy0Mode|L"ComboPhy0Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault
+  gRK3588TokenSpaceGuid.PcdComboPhy1Mode|L"ComboPhy1Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault
+  gRK3588TokenSpaceGuid.PcdComboPhy2Mode|L"ComboPhy2Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+  #
+  # PEI Phase modules
+  #
+  ArmPlatformPkg/PrePi/PeiUniCore.inf
+  MdeModulePkg/Core/Pei/PeiMain.inf
+  MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+
+  #
+  # DXE
+  #
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+  }
+
+  #
+  # Architectural Protocols
+  #
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+  #EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
+  <LibraryClasses>
+    RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
+  }
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  #PCIe
+  #Silicon/Rockchip/Library/PciExpressLib/PciExpressLib.inf
+  #Silicon/Rockchip/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+  #Silicon/Rockchip/Drivers/PciPlatform/PcieInitDxe.inf
+  ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  #MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+  #MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.inf
+
+  MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+  
+  #
+  # Non-volatile FVB support
+  #
+  Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.inf
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+
+  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf
+  #Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
+  Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf
+  Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
+
+  Platform/Ameridroid/Drivers/LogoDxe/LogoDxe.inf
+
+  #
+  # SCMI Driver
+  #
+  ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf
+
+  #
+  # ACPI Support
+  #
+  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+  Platform/Ameridroid/IndiedroidNova/AcpiTables/AcpiTables.inf
+
+  #
+  # Device tree
+  #
+  EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf {
+  <LibraryClasses>
+    DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefault/DxeDtPlatformDtbLoaderLibDefault.inf
+  }
+
+  #
+  # GPIO
+  #
+  Platform/Rockchip/RK3588/RK3588GpioDxe/RK3588GpioDxe.inf
+
+  #
+  # Virtual Keyboard
+  #
+  EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
+
+  # I2C drivers
+  Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.inf
+  MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
+  Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.inf
+  Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.inf
+  Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.inf
+
+  #
+  # MMC/SD
+  #
+  #EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
+  #Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  Silicon/Rockchip/Drivers/MmcDxe/MmcDxe.inf
+  # sdcard is dwemmc, sdhci is for eMMC.
+  Silicon/Rockchip/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  Silicon/Rockchip/Drivers/SdhciHostDxe/SdhciHostDxe.inf
+
+  #
+  # NOR FLASH
+  #
+  Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.inf
+  Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+
+  #
+  # AHCI Support
+  #
+  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+  #
+  # SPI TEST
+  #
+  # Silicon/Rockchip/Library/SpiLib/SpiTest.inf
+
+  #
+  # SMBIOS Support
+  #
+  Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  
+  #
+  # USB Ohci Controller
+  #
+  Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf
+
+  #
+  # USB Ehci Controller
+  #
+  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+
+  #
+  # USB Dwc3 Controller
+  #
+  Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
+  #
+  # USB Xhci Controller
+  #
+  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+
+  #
+  # USB Host Support
+  #
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+  #
+  # USB Mass Storage Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # USB Kb Support
+  #
+  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+  #
+  # USB Mouse Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+
+  #
+  # USB MouseAbsolutePointer Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointerDxe.inf
+
+  #
+  # USB Peripheral Support
+  #
+  EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
+
+  #
+  # Fastboot
+  #
+  EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
+
+  #
+  # Android Boot applications
+  #
+  EmbeddedPkg/Application/AndroidBoot/AndroidBootApp.inf
+
+  #
+  # UEFI Network Stack
+  #
+!include NetworkPkg/Network.dsc.inc
+  #
+  # AX88772 Ethernet Driver
+  #
+  Drivers/ASIX/Bus/Usb/UsbNetworking/Ax88772c/Ax88772c.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+  FatPkg/EnhancedFatDxe/Fat.inf
+
+  #
+  # Bds
+  #
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  MdeModulePkg/Application/UiApp/UiApp.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  ShellPkg/Application/Shell/Shell.inf {
+    <LibraryClasses>
+      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+      NULL|Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.inf
+      NULL|Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf
+      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+      OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
+      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+      gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+  }
+!ifdef $(INCLUDE_TFTP_COMMAND)
+  ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+!endif #$(INCLUDE_TFTP_COMMAND)
+
+  #
+  # Custom Applications and drivers
+  #
+  Silicon/Rockchip/Applications/MaskromReset/maskrom.inf
+
+  # Platform drivers
+  Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf
+
--- a/edk2-platforms/Platform/Ameridroid/IndiedroidNova/IndiedroidNova.fdf
+++ b/edk2-platforms/Platform/Ameridroid/IndiedroidNova/IndiedroidNova.fdf
@@ -0,0 +1,377 @@
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2021-2022, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.NOR_FLASH_IMAGE]
+BaseAddress   = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
+Size          = 0x00800000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize     = 0x00001000
+NumBlocks     = 0x800
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+0x00200000|0x00500000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = BL33_AP_UEFI
+
+# NV_VARIABLE_STORE
+0x007C0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+
+# NV_FTW_WORKING header
+0x007D0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+# NV_FTW_WORKING data
+0x007E0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+BlockSize          = 0x40
+NumBlocks          = 0         # This FV gets compressed so make it just big enough
+FvAlignment        = 8         # FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  APRIORI DXE {
+    INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+  }
+
+  INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+  #
+  # PI DXE Drivers producing Architectural Protocols (EFI Services)
+  #
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  #
+  # Multiple Console IO support
+  #
+  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+
+  INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+
+  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  #
+  # ACPI Support
+  #
+  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+  INF RuleOverride = ACPITABLE Platform/Ameridroid/IndiedroidNova/AcpiTables/AcpiTables.inf
+
+  #
+  # Device tree
+  #
+  INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf
+  # FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 {
+  #   SECTION RAW = Platform/Rockchip/DeviceTree/rk3588.dtb
+  # }
+
+  #
+  # GPIO
+  #
+  INF Platform/Rockchip/RK3588/RK3588GpioDxe/RK3588GpioDxe.inf
+  #INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf
+
+  #
+  # I2C
+  #
+  INF Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.inf
+  INF MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
+  # INF Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.inf
+  INF Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.inf
+
+  #
+  # Virtual Keyboard
+  #
+  INF EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
+
+  #
+  # Display Support
+  #
+  
+  INF Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf
+  #INF Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
+  INF Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf
+  INF Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
+  INF Platform/Ameridroid/Drivers/LogoDxe/LogoDxe.inf
+
+  INF Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf
+
+  #
+  # SMBIOS Support
+  #
+  INF Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+  INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+
+  #
+  # USB Ehci Controller
+  #
+  INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+
+  #
+  # USB Ohci Controller
+  #
+  INF Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf
+
+  #
+  # USB Dwc3 Controller
+  #
+  INF Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
+  #
+  # USB Xhci Controller
+  #
+  INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+
+  #
+  # USB Host Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+  #
+  # USB Mass Storage Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # USB Kb Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+  #
+  # USB Mouse Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+
+  #
+  # USB MouseAbsolutePointer Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointerDxe.inf
+
+  #
+  # USB Peripheral Support
+  #
+  INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
+
+  #
+  # Fastboot
+  #
+  INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
+
+
+  #PCIe
+  #INF Silicon/Rockchip/Drivers/PciPlatform/PcieInitDxe.inf
+
+  # Required by PCI
+  INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
+  # PCI Support
+  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  #INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+  #INF MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.inf
+
+  #INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+  INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+  #
+  # Android Boot applications
+  #
+  INF EmbeddedPkg/Application/AndroidBoot/AndroidBootApp.inf
+
+  #
+  # UEFI Network Stack
+  #
+!include NetworkPkg/Network.fdf.inc
+
+  #
+  # AX88772 Ethernet Driver for Apple Ethernet Adapter
+  #
+  INF Drivers/ASIX/Bus/Usb/UsbNetworking/Ax88772c/Ax88772c.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF FatPkg/EnhancedFatDxe/Fat.inf
+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  #
+  # Multimedia Card Interface
+  #
+  # INF Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  INF Silicon/Rockchip/Drivers/MmcDxe/MmcDxe.inf
+  # sdcard is dwemmc, sdhci is for eMMC.
+  INF Silicon/Rockchip/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  
+  #
+  # DWC SDHCI (for eMMC slot)
+  #
+  INF Silicon/Rockchip/Drivers/SdhciHostDxe/SdhciHostDxe.inf
+
+  #
+  # AHCI Support
+  #
+  INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+  #
+  # SPI NOR FLASH
+  #
+  INF Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.inf
+
+  #
+  # Non-volatile FVB support
+  #
+  INF Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.inf
+  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+
+  # Human interface
+  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  # Custom
+  INF Silicon/Rockchip/Applications/MaskromReset/maskrom.inf
+  
+  # SCMI Driver
+  INF ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf
+
+  #
+  # UEFI applications
+  #
+  INF ShellPkg/Application/Shell/Shell.inf
+!ifdef $(INCLUDE_TFTP_COMMAND)
+  INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+!endif #$(INCLUDE_TFTP_COMMAND)
+  #INF Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+
+  #
+  # Bds
+  #
+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+[FV.BL33_AP_UEFI]
+FvAlignment        = 8
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+
+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FVMAIN
+    }
+  }
+
+!include Silicon/Rockchip/Rockchip.fdf.inc
+
+!ifdef $(ROCKCHIP_ACPIEN)
+[Rule.Common.DXE_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX	 DXE_DEPEX		Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32	 PE32			$(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI		 STRING="$(MODULE_NAME)" Optional
+    RAW 	 ACPI  Optional 	      |.acpi
+    RAW 	 ASL   Optional 	      |.aml
+  }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW ACPI		   |.acpi
+    RAW ASL		   |.aml
+  }
+!endif
--- a/edk2-platforms/Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-platforms/Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -0,0 +1,267 @@
+/** @file
+*
+*  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include <Base.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/GpioLib.h>
+#include <Library/RK806.h>
+#include <Soc.h>
+
+static struct regulator_init_data rk806_init_data[] = {
+  /* Master PMIC */
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
+ // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+
+  /* No dual PMICs on this platform */
+};
+
+VOID
+EFIAPI
+DwEmmcDxeIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux */
+}
+
+VOID
+EFIAPI
+SdhciEmmcDxeIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux */
+  /* Do not override, set by earlier boot stages. */
+}
+
+#define NS_CRU_BASE         0xFD7C0000
+#define CRU_CLKSEL_CON59    0x03EC
+#define CRU_CLKSEL_CON78    0x0438
+
+VOID
+EFIAPI
+Rk806SpiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
+  PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+}
+
+VOID
+EFIAPI
+Rk806Configure (
+  VOID
+  )
+{
+  UINTN RegCfgIndex;
+
+  RK806Init();
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
+    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+}
+
+VOID
+EFIAPI
+SetCPULittleVoltage (
+  IN UINT32 Microvolts
+  )
+{
+  struct regulator_init_data Rk806CpuLittleSupply =
+        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+
+  RK806RegulatorInit(Rk806CpuLittleSupply);
+}
+
+VOID
+EFIAPI
+NorFspiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  /* Do not override, set by earlier boot stages. */
+}
+
+VOID
+EFIAPI
+GmacIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    /* gmac0 iomux */
+    BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+    BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+    BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+    BUS_IOC->GPIO2C_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+    BUS_IOC->GPIO4C_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0100;
+    BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011;
+    break;
+  case 1:
+    /* gmac1 iomux */
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+NorFspiEnableClock (
+  UINT32 *CruBase
+  )
+{
+  UINTN BaseAddr = (UINTN) CruBase;
+
+  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+}
+
+VOID
+EFIAPI
+I2cIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    /* io mux M2 */
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
+    break;
+  case 1:
+    /* io mux */
+    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
+    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
+    break;
+  case 2:
+    /* io mux */
+    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
+    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
+    PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
+    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    break;
+  case 3:
+    break;
+  case 4:
+    break;
+  case 5:
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+UsbPortPowerEnable (
+  VOID
+  )
+{
+  DEBUG((EFI_D_WARN, "UsbPortPowerEnable called\n"));
+
+  /* Set GPIO4 PA5 output high to enable USB-C VBUS */
+  GpioPinWrite (4, GPIO_PIN_PA5, TRUE);
+  GpioPinSetDirection (4, GPIO_PIN_PA5, GPIO_PIN_OUTPUT);
+}
+
+VOID
+EFIAPI
+Usb2PhyResume (
+  VOID
+  )
+{
+  MmioWrite32(0xfd5d0008, 0x20000000);
+  MmioWrite32(0xfd5d4008, 0x20000000);
+  MmioWrite32(0xfd5d8008, 0x20000000);
+  MmioWrite32(0xfd5dc008, 0x20000000);
+  MmioWrite32(0xfd7f0a10, 0x07000700);
+  MmioWrite32(0xfd7f0a10, 0x07000000);
+}
+
+VOID
+EFIAPI
+UsbDpPhyEnable (
+  VOID
+  )
+{
+  /* enable rx_lfps_en & usbdp_low_pwrn */
+  MmioWrite32(0xfd5c8004, 0x60006000);
+  MmioWrite32(0xfd5cc004, 0x60006000);
+  
+  /* remove rx-termination, we don't support SS yet */
+  MmioWrite32 (0xfd5c800c, 0x00030001);
+  MmioWrite32 (0xfd5cc00c, 0x00030001);
+}
+
+VOID
+EFIAPI
+Pcie30IoInit (
+  VOID
+  )
+{
+  /* Set reset and power IO to gpio output mode */
+  GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
+  GpioPinSetDirection (1, GPIO_PIN_PA4, GPIO_PIN_OUTPUT);
+}
+
+VOID
+EFIAPI
+Pcie30PowerEn (
+  VOID
+  )
+{
+  /* output high to enable power */
+  GpioPinWrite (1, GPIO_PIN_PA4, TRUE);
+}
+
+VOID
+EFIAPI
+Pcie30PeReset (
+  BOOLEAN enable
+  )
+{
+  if(enable)
+    GpioPinWrite (4, GPIO_PIN_PB6, FALSE); /* output low */
+  else
+    GpioPinWrite (4, GPIO_PIN_PB6, TRUE); /* output high */
+}
+
+VOID
+EFIAPI
+PlatformEarlyInit (
+  VOID
+  )
+{
+  // Configure various things specific to this platform
+}
--- a/edk2-platforms/Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+++ b/edk2-platforms/Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.inf
@@ -0,0 +1,43 @@
+#
+#  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = RockchipPlatformLib
+  FILE_GUID                      = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RockchipPlatformLib
+  RKPLATLIB_COMMON_DIR           = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Platform/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  SerialPortLib
+  CruLib
+  GpioLib
+
+[Sources.common]
+  RockchipPlatformLib.c
+  $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c
+  $(RKPLATLIB_COMMON_DIR)/RockchipSdhci.c
+
+[Sources.AARCH64]
+
+[Pcd]
+  gRockchipTokenSpaceGuid.PcdSdhciDxeBaseAddress
+  gRockchipTokenSpaceGuid.PcdI2cBusCount
+
--- a/edk2-platforms/Platform/Firefly/Drivers/LogoDxe/Logo.bmp
+++ b/edk2-platforms/Platform/Firefly/Drivers/LogoDxe/Logo.bmp
--- a/edk2-platforms/Platform/Firefly/Drivers/LogoDxe/Logo.c
+++ b/edk2-platforms/Platform/Firefly/Drivers/LogoDxe/Logo.c
@@ -0,0 +1,144 @@
+/** @file
+  Logo DXE Driver, install Edkii Platform Logo protocol.
+
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+  Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Protocol/HiiDatabase.h>
+#include <Protocol/GraphicsOutput.h>
+#include <Protocol/HiiImageEx.h>
+#include <Protocol/PlatformLogo.h>
+#include <Protocol/HiiPackageList.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+
+typedef struct {
+  EFI_IMAGE_ID                          ImageId;
+  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
+  INTN                                  OffsetX;
+  INTN                                  OffsetY;
+} LOGO_ENTRY;
+
+STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
+STATIC EFI_HII_HANDLE            mHiiHandle;
+STATIC LOGO_ENTRY                mLogos[] = {
+  {
+    IMAGE_TOKEN (IMG_LOGO),
+    EdkiiPlatformLogoDisplayAttributeCenter,
+    0,
+    0
+  }
+};
+
+/**
+  Load a platform logo image and return its data and attributes.
+
+  @param This              The pointer to this protocol instance.
+  @param Instance          The visible image instance is found.
+  @param Image             Points to the image.
+  @param Attribute         The display attributes of the image returned.
+  @param OffsetX           The X offset of the image regarding the Attribute.
+  @param OffsetY           The Y offset of the image regarding the Attribute.
+
+  @retval EFI_SUCCESS      The image was fetched successfully.
+  @retval EFI_NOT_FOUND    The specified image could not be found.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GetImage (
+  IN     EDKII_PLATFORM_LOGO_PROTOCOL          *This,
+  IN OUT UINT32                                *Instance,
+     OUT EFI_IMAGE_INPUT                       *Image,
+     OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
+     OUT INTN                                  *OffsetX,
+     OUT INTN                                  *OffsetY
+  )
+{
+  UINT32 Current;
+
+  if (Instance == NULL || Image == NULL ||
+      Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Current = *Instance;
+  if (Current >= ARRAY_SIZE (mLogos)) {
+    return EFI_NOT_FOUND;
+  }
+
+  (*Instance)++;
+  *Attribute = mLogos[Current].Attribute;
+  *OffsetX   = mLogos[Current].OffsetX;
+  *OffsetY   = mLogos[Current].OffsetY;
+
+  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
+                        mLogos[Current].ImageId, Image);
+}
+
+STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+  GetImage
+};
+
+/**
+  Entrypoint of this module.
+
+  This function is the entrypoint of this module. It installs the Edkii
+  Platform Logo protocol.
+
+  @param  ImageHandle       The firmware allocated handle for the EFI image.
+  @param  SystemTable       A pointer to the EFI System Table.
+
+  @retval EFI_SUCCESS       The entry point is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeLogo (
+  IN EFI_HANDLE               ImageHandle,
+  IN EFI_SYSTEM_TABLE         *SystemTable
+  )
+{
+  EFI_STATUS                  Status;
+  EFI_HII_PACKAGE_LIST_HEADER *PackageList;
+  EFI_HII_DATABASE_PROTOCOL   *HiiDatabase;
+  EFI_HANDLE                  Handle;
+
+  Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
+                  (VOID **) &HiiDatabase);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
+                  (VOID **) &mHiiImageEx);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Retrieve HII package list from ImageHandle
+  //
+  Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
+                  (VOID **) &PackageList, ImageHandle, NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR,
+      "HII Image Package with logo not found in PE/COFF resource section\n"));
+    return Status;
+  }
+
+  //
+  // Publish HII package list to HII Database.
+  //
+  Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
+                          &mHiiHandle);
+  if (!EFI_ERROR (Status)) {
+    Handle = NULL;
+    Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
+                    &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
+  }
+  return Status;
+}
--- a/edk2-platforms/Platform/Firefly/Drivers/LogoDxe/Logo.idf
+++ b/edk2-platforms/Platform/Firefly/Drivers/LogoDxe/Logo.idf
@@ -0,0 +1,10 @@
+// @file
+// Platform Logo image definition file.
+//
+// Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+// Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+
+#image IMG_LOGO Logo.bmp
--- a/edk2-platforms/Platform/Firefly/Drivers/LogoDxe/LogoDxe.inf
+++ b/edk2-platforms/Platform/Firefly/Drivers/LogoDxe/LogoDxe.inf
@@ -0,0 +1,48 @@
+## @file
+#  The default logo bitmap picture shown on setup screen.
+#
+#  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+#  Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = LogoDxe
+  FILE_GUID                      = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = InitializeLogo
+#
+#  This flag specifies whether HII resource section is generated into PE image.
+#
+  UEFI_HII_RESOURCE_SECTION      = TRUE
+
+[Sources]
+  Logo.bmp
+  Logo.c
+  Logo.idf
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  DebugLib
+
+[Protocols]
+  gEfiHiiDatabaseProtocolGuid        ## CONSUMES
+  gEfiHiiImageExProtocolGuid         ## CONSUMES
+  gEfiHiiPackageListProtocolGuid     ## PRODUCES CONSUMES
+  gEdkiiPlatformLogoProtocolGuid     ## PRODUCES
+
+[Depex]
+  gEfiHiiDatabaseProtocolGuid AND
+  gEfiHiiImageExProtocolGuid
--- a/edk2-platforms/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/AcpiTables.inf
+++ b/edk2-platforms/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/AcpiTables.inf
@@ -0,0 +1,64 @@
+#/** @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2019-2021, ARM Limited. All rights reserved.
+#  Copyright (c) Microsoft Corporation. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+  RK_COMMON_ACPI_DIR             = Silicon/Rockchip/RK3588/AcpiTables
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+
+[Sources]
+  Dsdt.asl
+  $(RK_COMMON_ACPI_DIR)/Madt.aslc
+  $(RK_COMMON_ACPI_DIR)/Fadt.aslc
+  $(RK_COMMON_ACPI_DIR)/Gtdt.aslc
+  $(RK_COMMON_ACPI_DIR)/Spcr.aslc
+  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
+  $(RK_COMMON_ACPI_DIR)/RK3588PcieIort.aslc
+  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Rockchip/RockchipPkg.dec
+  Platform/Rockchip/RK3588/RK3588.dec
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
--- a/edk2-platforms/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/Dsdt.asl
+++ b/edk2-platforms/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/Dsdt.asl
@@ -0,0 +1,39 @@
+/** @file
+ *
+ *  Differentiated System Definition Table (DSDT)
+ *
+ *  Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ *  Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
+ *  Copyright (c) Microsoft Corporation. All rights reserved.
+ *  Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include "AcpiTables.h"
+
+DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
+{
+  Scope (\_SB_)
+  {
+    include ("Cpu.asl")
+
+    // include ("Pcie.asl")
+    include ("Sata0.asl")
+    include ("Sata2.asl")
+    include ("Emmc.asl")
+    include ("Sdhc.asl")
+    // include ("Gmac.asl")
+    // include ("Gpio.asl")
+    // include ("I2c.asl")
+    include ("Uart.asl")
+    // include ("Spi.asl")
+
+    // won't work on Windows, will trigger bugcheck by usbehci
+    // include ("Usb2.asl")
+
+    include ("Usb3Host0.asl")
+    include ("Usb3Host2.asl")
+  }
+}
--- a/edk2-platforms/Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-platforms/Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -0,0 +1,303 @@
+/** @file
+*
+*  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include <Base.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/GpioLib.h>
+#include <Library/RK806.h>
+#include <Soc.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+static struct regulator_init_data rk806_init_data[] = {
+  /* Master PMIC */
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
+ // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+
+  /* No dual PMICs on this platform */
+};
+
+VOID
+EFIAPI
+DwEmmcDxeIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux */
+}
+
+VOID
+EFIAPI
+SdhciEmmcDxeIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux */
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+}
+
+#define NS_CRU_BASE         0xFD7C0000
+#define CRU_CLKSEL_CON59    0x03EC
+#define CRU_CLKSEL_CON78    0x0438
+
+VOID
+EFIAPI
+Rk806SpiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
+  PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+}
+
+VOID
+EFIAPI
+Rk806Configure (
+  VOID
+  )
+{
+  UINTN RegCfgIndex;
+
+  RK806Init();
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
+    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+}
+
+VOID
+EFIAPI
+SetCPULittleVoltage (
+  IN UINT32 Microvolts
+  )
+{
+  struct regulator_init_data Rk806CpuLittleSupply =
+        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+
+  RK806RegulatorInit(Rk806CpuLittleSupply);
+}
+
+VOID
+EFIAPI
+NorFspiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
+             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
+#define FSPI_M1
+#if defined(FSPI_M0)
+   /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
+#elif defined(FSPI_M1)
+  /*FSPI M1*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
+#else
+  /*FSPI M2*/
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
+#endif
+}
+
+VOID
+EFIAPI
+GmacIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    /* gmac0 iomux */
+    BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+    BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+    BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+    BUS_IOC->GPIO2C_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+    BUS_IOC->GPIO4C_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0100;
+    BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011;
+    break;
+  case 1:
+    /* gmac1 iomux */
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+NorFspiEnableClock (
+  UINT32 *CruBase
+  )
+{
+  UINTN BaseAddr = (UINTN) CruBase;
+
+  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+}
+
+VOID
+EFIAPI
+I2cIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    /* io mux M2 */
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
+    break;
+  case 1:
+    /* io mux */
+    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
+    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
+    break;
+  case 2:
+    /* io mux */
+    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
+    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
+    PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
+    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    break;
+  case 3:
+    break;
+  case 4:
+    break;
+  case 5:
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+UsbPortPowerEnable (
+  VOID
+  )
+{
+  DEBUG((EFI_D_WARN, "UsbPortPowerEnable called\n"));
+
+  /* Enable USB-C VBUS */
+  GpioPinWrite (1, GPIO_PIN_PB1, TRUE);
+  GpioPinSetDirection (1, GPIO_PIN_PB1, GPIO_PIN_OUTPUT);
+
+  //
+  // Power cycle vcc5v0_host as some USB 3.0 devices won't enumerate
+  // during boot otherwise.
+  //
+  GpioPinSetDirection (1, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
+  GpioPinWrite (1, GPIO_PIN_PB6, FALSE);
+  gBS->Stall (1200000);
+  GpioPinWrite (1, GPIO_PIN_PB6, TRUE);
+}
+
+VOID
+EFIAPI
+Usb2PhyResume (
+  VOID
+  )
+{
+  MmioWrite32(0xfd5d0008, 0x20000000);
+  MmioWrite32(0xfd5d4008, 0x20000000);
+  MmioWrite32(0xfd5d8008, 0x20000000);
+  MmioWrite32(0xfd5dc008, 0x20000000);
+  MmioWrite32(0xfd7f0a10, 0x07000700);
+  MmioWrite32(0xfd7f0a10, 0x07000000);
+}
+
+VOID
+EFIAPI
+UsbDpPhyEnable (
+  VOID
+  )
+{
+  /* enable rx_lfps_en & usbdp_low_pwrn */
+  MmioWrite32(0xfd5c8004, 0x60006000);
+  MmioWrite32(0xfd5cc004, 0x60006000);
+  
+  /* remove rx-termination, we don't support SS yet */
+  MmioWrite32 (0xfd5c800c, 0x00030001);
+  MmioWrite32 (0xfd5cc00c, 0x00030001);
+}
+
+VOID
+EFIAPI
+Pcie30IoInit (
+  VOID
+  )
+{
+  /* Set reset and power IO to gpio output mode */
+  GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
+  GpioPinSetDirection (1, GPIO_PIN_PA4, GPIO_PIN_OUTPUT);
+}
+
+VOID
+EFIAPI
+Pcie30PowerEn (
+  VOID
+  )
+{
+  /* output high to enable power */
+  GpioPinWrite (1, GPIO_PIN_PA4, TRUE);
+}
+
+VOID
+EFIAPI
+Pcie30PeReset (
+  BOOLEAN enable
+  )
+{
+  if(enable)
+    GpioPinWrite (4, GPIO_PIN_PB6, FALSE); /* output low */
+  else
+    GpioPinWrite (4, GPIO_PIN_PB6, TRUE); /* output high */
+}
+
+VOID
+EFIAPI
+PlatformEarlyInit (
+  VOID
+  )
+{
+  /* Enable RGB LED, we got no other power indicator */
+  GpioPinWrite (1, GPIO_PIN_PD5, TRUE);
+  GpioPinSetDirection (1, GPIO_PIN_PD5, GPIO_PIN_OUTPUT);
+  GpioPinWrite (3, GPIO_PIN_PB2, TRUE);
+  GpioPinSetDirection (3, GPIO_PIN_PB2, GPIO_PIN_OUTPUT);
+  GpioPinWrite (3, GPIO_PIN_PC0, TRUE);
+  GpioPinSetDirection (3, GPIO_PIN_PC0, GPIO_PIN_OUTPUT);
+}
--- a/edk2-platforms/Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+++ b/edk2-platforms/Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.inf
@@ -0,0 +1,43 @@
+#
+#  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = RockchipPlatformLib
+  FILE_GUID                      = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RockchipPlatformLib
+  RKPLATLIB_COMMON_DIR           = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Platform/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  SerialPortLib
+  CruLib
+  GpioLib
+
+[Sources.common]
+  RockchipPlatformLib.c
+  $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c
+  $(RKPLATLIB_COMMON_DIR)/RockchipSdhci.c
+
+[Sources.AARCH64]
+
+[Pcd]
+  gRockchipTokenSpaceGuid.PcdSdhciDxeBaseAddress
+  gRockchipTokenSpaceGuid.PcdI2cBusCount
+
--- a/edk2-platforms/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc
+++ b/edk2-platforms/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc
@@ -0,0 +1,32 @@
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2021-2022, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = ROC-RK3588S-PC
+  PLATFORM_GUID                  = d080df36-45e7-11ec-9726-f42a7dcb925d
+  PLATFORM_VERSION               = 0.2
+  DSC_SPECIFICATION              = 0x00010019
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  VENDOR_DIRECTORY               = Platform/Firefly
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.fdf
+
+!include Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc.inc
+
+[PcdsFixedAtBuild.common]
+  # SMBIOS platform config
+  gRockchipTokenSpaceGuid.PcdPlatformName|"ROC-RK3588S-PC"
+  gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Firefly"
+  gRockchipTokenSpaceGuid.PcdFamilyName|"ROC"
+  gRockchipTokenSpaceGuid.PcdProductUrl|"https://en.t-firefly.com/product/industry/rocrk3588spc"
--- a/edk2-platforms/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc.inc
+++ b/edk2-platforms/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc.inc
@@ -0,0 +1,621 @@
+
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2021-2022, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  DEFINE CONFIG_NO_DEBUGLIB      = TRUE
+
+  #
+  # Must match defines in Silicon/Rockchip/RK3588/Include/VarStoreData.h
+  #
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT  = 0
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_MIN          = 1
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_MAX          = 2
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_CUSTOM       = 3
+
+  DEFINE COMBO_PHY_MODE_UNCONNECTED   = 0
+  DEFINE COMBO_PHY_MODE_PCIE          = 1
+  DEFINE COMBO_PHY_MODE_SATA          = 2
+  DEFINE COMBO_PHY_MODE_USB3          = 3
+
+  #
+  # Network definition
+  #
+  DEFINE NETWORK_SNP_ENABLE             = FALSE
+  DEFINE NETWORK_IP6_ENABLE             = FALSE
+  DEFINE NETWORK_TLS_ENABLE             = FALSE
+  DEFINE NETWORK_HTTP_BOOT_ENABLE       = FALSE
+  DEFINE NETWORK_ISCSI_ENABLE           = FALSE
+  DEFINE NETWORK_VLAN_ENABLE            = FALSE
+!include Silicon/Rockchip/Rockchip.dsc.inc
+!include MdePkg/MdeLibs.dsc.inc
+
+[LibraryClasses.common]
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmPlatformLib|Silicon/Rockchip/RK3588/Library/PlatformLib/PlatformLib.inf
+  AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf
+  CruLib|Silicon/Rockchip/Library/CruLib/CruLib.inf
+
+  DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
+
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+  # UiApp dependencies
+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+
+  #RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+  TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
+
+  # USB Requirements
+  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+
+  # PCIe
+  PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+  #PciHostBridgeLib|Silicon/Rockchip/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+  #PciExpressLib|Silicon/Rockchip/Library/PciExpressLib/PciExpressLib.inf
+  PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+
+
+  # VariableRuntimeDxe Requirements
+  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+  AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+  TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+  VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+
+  AndroidBootImgLib|edk2/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.inf
+
+  RockchipDisplayLib|Silicon/Rockchip/Library/DisplayLib/RockchipDisplayLib.inf
+
+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+  LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf
+
+  # OTP Library
+  OtpLib|Silicon/Rockchip/RK3588/Library/OtpLib/OtpLib.inf
+
+  #
+  # Custom libraries
+  #
+  RockchipPlatformLib|Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+  ResetSystemLib|Silicon/Rockchip/Library/ResetSystemLib/ResetSystemLib.inf
+  PlatformBootManagerLib|Silicon/Rockchip/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+  SerialPortLib|Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf
+  GpioLib|Silicon/Rockchip/RK3588/Library/GpioLib/GpioLib.inf
+  # SCMI Mailbox Transport Layer
+  ArmMtlLib|Silicon/Rockchip/Library/RkMtlLib/RkMtlLib.inf
+
+[LibraryClasses.common.SEC]
+  PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+  ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+  HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
+  MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+  MemoryInitPeiLib|Silicon/Rockchip/RK3588/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
+  PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+  PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+  RockchipPlatformLib|Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+
+[BuildOptions]
+  GCC:*_*_*_PLATFORM_FLAGS = -I$(WORKSPACE)/Silicon/Rockchip/RK3588/Include -I$(WORKSPACE)/Platform/Rockchip/RK3588/Include -I$(WORKSPACE)/Silicon/Rockchip/Include
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+  #  If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+  #  It could be set FALSE to save size.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+
+[PcdsFixedAtBuild.common]
+  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)"
+
+  # System Memory (1GB)
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000
+  gRK3588TokenSpaceGuid.PcdTotalMemorySize|0x200000000
+  
+  # RK3588 CPU profile
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|8
+  gArmPlatformTokenSpaceGuid.PcdClusterCount|1
+
+  # SMBIOS platform config
+  gRockchipTokenSpaceGuid.PcdBoardName|"ROC-RK3588S-PC"
+  gRockchipTokenSpaceGuid.PcdBoardVendorName|"Firefly"
+  gRockchipTokenSpaceGuid.PcdMemoryVendorName|"TBD"
+
+  # I2C
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 }
+  gRockchipTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0 }
+  gRockchipTokenSpaceGuid.PcdI2cClockFrequency|198000000
+  gRockchipTokenSpaceGuid.PcdI2cBaudRate|100000
+  gRockchipTokenSpaceGuid.PcdI2cBusCount|1
+  gRockchipTokenSpaceGuid.PcdI2cDemoAddresses|{ 0x51 } #/* RTCYM8563TS 0x51@bus2 */
+  gRockchipTokenSpaceGuid.PcdI2cDemoBuses|{ 0x2 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ 2, 3 } # SCMI_CLK_CPUB01, SCMI_CLK_CPUB23
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorMinVoltages|{ UINT32(550000), UINT32(550000) }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorMaxVoltages|{ UINT32(1050000), UINT32(1050000) }
+
+  ## UART2 - Serial Terminal
+  DEFINE SERIAL_BASE = 0xFEB50000 # UART2
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|$(SERIAL_BASE)
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|1500000
+  gHisiTokenSpaceGuid.PcdSerialPortSendDelay|500000
+  gHisiTokenSpaceGuid.PcdUartClkInHz|24000000
+
+  ## SPI - SPI2 for test
+  gRockchipTokenSpaceGuid.SpiTestBaseAddr|0xFEB20000
+  gRockchipTokenSpaceGuid.SpiRK806BaseAddr|0xFEB20000
+  ## PL031 RealTimeClock
+  #gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0xF8003000
+
+  ## NOR FLASH
+  gRockchipTokenSpaceGuid.FspiBaseAddr|0xFE2B0000
+
+  ## CRU
+  gRockchipTokenSpaceGuid.CruBaseAddr|0xFD7C0000
+
+  #gRockchipTokenSpaceGuid.PcdSpiVariableOffset|0x3C0000
+  #
+  # ARM General Interrupt Controller
+  #
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0xfe600000
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xfe600000
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0xfe680000
+
+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3
+
+  # GUID of the UI app
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+
+  gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
+
+  #
+  # DW SD card controller
+  #
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeBaseAddress|0xfe2c0000
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz|100000000
+  gDesignWareTokenSpaceGuid.PcdDwPermitObsoleteDrivers|TRUE
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeFifoDepth|256
+  #
+  # SDHCI controller
+  #
+  gRockchipTokenSpaceGuid.PcdSdhciDxeBaseAddress|0xfe2e0000
+
+  #
+  # PCIe controller
+  #
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress|0xfe150000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress|0xf5000000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress|0xf0000000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize|0x100000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress|0xf0100000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize|0x10000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress|0xf0200000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize|0xe00000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64|0x901000000 #deduct 0x1000000 ECAM space
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64|0x3f000000
+
+  #
+  # Fastboot
+  #
+  gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbVendorId|0x2207
+  gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbProductId|0x0001
+
+  #
+  # USB2 EHCI + OHCI companion controllers
+  #
+  gRockchipTokenSpaceGuid.PcdEhciBaseAddress|0xfc800000
+  gRockchipTokenSpaceGuid.PcdNumEhciController|2
+  gRockchipTokenSpaceGuid.PcdEhciSize|0x40000
+  gRockchipTokenSpaceGuid.PcdOhciSize|0x40000
+
+  #
+  # DWC3 controller
+  #
+  gRockchipTokenSpaceGuid.PcdDwc3BaseAddresses|{ UINT32(0xfc000000), UINT32(0xfc400000), UINT32(0xfcd00000) }
+  gRockchipTokenSpaceGuid.PcdDwc3Size|0x400000
+
+  #
+  # Android Loader
+  #
+  gRK3588TokenSpaceGuid.PcdAndroidBootDevicePath|L"\\EFI\\BOOT\\GRUBAA64.EFI"
+  gRK3588TokenSpaceGuid.PcdSdBootDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00E023F70000000000)/SD(0x0)"
+  gRK3588TokenSpaceGuid.PcdKernelBootArg|L"earlycon=uart8250,mmio32,0xfeb50000 root=PARTUUID=614e0000-0000 rw rootwait"
+  gEmbeddedTokenSpaceGuid.PcdAndroidBootDevicePath|L"VenHw(100C2CFA-B586-4198-9B4C-1683D195B1DA)/HD(3,GPT,7A3F0000-0000-446A-8000-702F00006273,0x8000,0x20000)"
+
+  # ACPI Enable
+  gRK3588TokenSpaceGuid.AcpiEnable|TRUE
+
+  #
+  # Display
+  #
+  gRockchipTokenSpaceGuid.PcdLcdPixelFormat|0x00000001
+  gRockchipTokenSpaceGuid.PcdEdpId|0x00000000 #edp0
+  #gRockchipTokenSpaceGuid.PcdEdpId|0x00000001 #edp1
+  gRockchipTokenSpaceGuid.PcdHdmiId|0x00000000 #hdmi0
+  #gRockchipTokenSpaceGuid.PcdHdmiId|0x00000001 #hdmi1
+
+  #
+  # CPU Performance default values
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|FALSE
+  gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE)
+  gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_UNCONNECTED)
+  gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3)
+
+  #  BIT0  - Initialization message.<BR>
+  #  BIT1  - Warning message.<BR>
+  #  BIT2  - Load Event message.<BR>
+  #  BIT3  - File System message.<BR>
+  #  BIT4  - Allocate or Free Pool message.<BR>
+  #  BIT5  - Allocate or Free Page message.<BR>
+  #  BIT6  - Information message.<BR>
+  #  BIT7  - Dispatcher message.<BR>
+  #  BIT8  - Variable message.<BR>
+  #  BIT10 - Boot Manager message.<BR>
+  #  BIT12 - BlockIo Driver message.<BR>
+  #  BIT14 - Network Driver message.<BR>
+  #  BIT16 - UNDI Driver message.<BR>
+  #  BIT17 - LoadFile message.<BR>
+  #  BIT19 - Event message.<BR>
+  #  BIT20 - Global Coherency Database changes message.<BR>
+  #  BIT21 - Memory range cachability changes message.<BR>
+  #  BIT22 - Detailed debug message.<BR>
+  #  BIT31 - Error message.<BR>
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0e
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000000
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0f
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x800B0507
+!endif
+# 0x800B05C7
+# Use 0x807B55FF to enable all debug messages
+
+[PcdsDynamicDefault.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x007C0000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x007CF000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x007D0000
+
+  #
+  # Display
+  #
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x780
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x438
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0
+
+[PcdsDynamicHii.common.DEFAULT]
+  #
+  # CPU Performance
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPreset|L"CpuPerf_CPULClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockCustom|L"CpuPerf_CPULClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|1800
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPreset|L"CpuPerf_CPUB01ClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockCustom|L"CpuPerf_CPUB01ClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|2400
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPreset|L"CpuPerf_CPUB23ClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockCustom|L"CpuPerf_CPUB23ClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|2400
+  gRK3588TokenSpaceGuid.PcdCPULClusterVoltageMode|L"CpuPerf_CPULClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0
+  gRK3588TokenSpaceGuid.PcdCPULClusterVoltageCustom|L"CpuPerf_CPULClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|950000
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterVoltageMode|L"CpuPerf_CPUB01ClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterVoltageCustom|L"CpuPerf_CPUB01ClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|1000000
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterVoltageMode|L"CpuPerf_CPUB23ClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterVoltageCustom|L"CpuPerf_CPUB23ClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|1000000
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY
+  #
+  gRK3588TokenSpaceGuid.PcdComboPhy0Mode|L"ComboPhy0Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault
+  gRK3588TokenSpaceGuid.PcdComboPhy1Mode|L"ComboPhy1Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault
+  gRK3588TokenSpaceGuid.PcdComboPhy2Mode|L"ComboPhy2Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault
+  
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+  #
+  # PEI Phase modules
+  #
+  ArmPlatformPkg/PrePi/PeiUniCore.inf
+  MdeModulePkg/Core/Pei/PeiMain.inf
+  MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+
+  #
+  # DXE
+  #
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+  }
+
+  #
+  # Architectural Protocols
+  #
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+  #EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
+  <LibraryClasses>
+    RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
+  }
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  #PCIe
+  #Silicon/Rockchip/Library/PciExpressLib/PciExpressLib.inf
+  #Silicon/Rockchip/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+  #Silicon/Rockchip/Drivers/PciPlatform/PcieInitDxe.inf
+  ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  #MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+  #MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.inf
+
+  MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+  
+  #
+  # Non-volatile FVB support
+  #
+  Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.inf
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+
+  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf
+  #Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
+  Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf
+  Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
+
+  $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf
+
+  #
+  # SCMI Driver
+  #
+  ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf
+
+  #
+  # ACPI Support
+  #
+  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+  Platform/Firefly/ROC-RK3588S-PC/AcpiTables/AcpiTables.inf
+
+  #
+  # Device tree
+  #
+  EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf {
+  <LibraryClasses>
+    DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefault/DxeDtPlatformDtbLoaderLibDefault.inf
+  }
+
+  #
+  # GPIO
+  #
+  Platform/Rockchip/RK3588/RK3588GpioDxe/RK3588GpioDxe.inf
+
+  #
+  # Virtual Keyboard
+  #
+  EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
+
+  # I2C drivers
+  Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.inf
+  MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
+  Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.inf
+  Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.inf
+  Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.inf
+
+  #
+  # MMC/SD
+  #
+  #EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
+  #Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  Silicon/Rockchip/Drivers/MmcDxe/MmcDxe.inf
+  # sdcard is dwemmc, sdhci is for eMMC.
+  Silicon/Rockchip/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  Silicon/Rockchip/Drivers/SdhciHostDxe/SdhciHostDxe.inf
+
+  #
+  # NOR FLASH
+  #
+  Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.inf
+  Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+
+  #
+  # AHCI Support
+  #
+  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+  #
+  # SPI TEST
+  #
+  # Silicon/Rockchip/Library/SpiLib/SpiTest.inf
+
+  #
+  # SMBIOS Support
+  #
+  Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  
+  #
+  # USB Ohci Controller
+  #
+  Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf
+
+  #
+  # USB Ehci Controller
+  #
+  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+
+  #
+  # USB Dwc3 Controller
+  #
+  Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
+  #
+  # USB Xhci Controller
+  #
+  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+
+  #
+  # USB Host Support
+  #
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+  #
+  # USB Mass Storage Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # USB Kb Support
+  #
+  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+  #
+  # USB Mouse Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+
+  #
+  # USB MouseAbsolutePointer Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointerDxe.inf
+
+  #
+  # USB Peripheral Support
+  #
+  EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
+
+  #
+  # Fastboot
+  #
+  EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
+
+  #
+  # Android Boot applications
+  #
+  EmbeddedPkg/Application/AndroidBoot/AndroidBootApp.inf
+
+  #
+  # UEFI Network Stack
+  #
+!include NetworkPkg/Network.dsc.inc
+  #
+  # AX88772 Ethernet Driver
+  #
+  Drivers/ASIX/Bus/Usb/UsbNetworking/Ax88772c/Ax88772c.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+  FatPkg/EnhancedFatDxe/Fat.inf
+
+  #
+  # Bds
+  #
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  MdeModulePkg/Application/UiApp/UiApp.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  ShellPkg/Application/Shell/Shell.inf {
+    <LibraryClasses>
+      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+      NULL|Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.inf
+      NULL|Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf
+      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+      OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
+      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+      gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+  }
+!ifdef $(INCLUDE_TFTP_COMMAND)
+  ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+!endif #$(INCLUDE_TFTP_COMMAND)
+
+  #
+  # Custom Applications and drivers
+  #
+  Silicon/Rockchip/Applications/MaskromReset/maskrom.inf
+
+  # Platform drivers
+  Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf
--- a/edk2-platforms/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.fdf
+++ b/edk2-platforms/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.fdf
@@ -0,0 +1,377 @@
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2021-2022, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.NOR_FLASH_IMAGE]
+BaseAddress   = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
+Size          = 0x00800000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize     = 0x00001000
+NumBlocks     = 0x800
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+0x00200000|0x00500000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = BL33_AP_UEFI
+
+# NV_VARIABLE_STORE
+0x007C0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+
+# NV_FTW_WORKING header
+0x007D0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+# NV_FTW_WORKING data
+0x007E0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+BlockSize          = 0x40
+NumBlocks          = 0         # This FV gets compressed so make it just big enough
+FvAlignment        = 8         # FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  APRIORI DXE {
+    INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+  }
+
+  INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+  #
+  # PI DXE Drivers producing Architectural Protocols (EFI Services)
+  #
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  #
+  # Multiple Console IO support
+  #
+  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+
+  INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+
+  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  #
+  # ACPI Support
+  #
+  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+  INF RuleOverride = ACPITABLE Platform/Firefly/ROC-RK3588S-PC/AcpiTables/AcpiTables.inf
+
+  #
+  # Device tree
+  #
+  INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf
+  # FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 {
+  #   SECTION RAW = Platform/Rockchip/DeviceTree/rk3588.dtb
+  # }
+
+  #
+  # GPIO
+  #
+  INF Platform/Rockchip/RK3588/RK3588GpioDxe/RK3588GpioDxe.inf
+  #INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf
+
+  #
+  # I2C
+  #
+  INF Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.inf
+  INF MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
+  # INF Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.inf
+  INF Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.inf
+
+  #
+  # Virtual Keyboard
+  #
+  INF EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
+
+  #
+  # Display Support
+  #
+  
+  INF Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf
+  #INF Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
+  INF Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf
+  INF Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
+  INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf
+
+  INF Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf
+
+  #
+  # SMBIOS Support
+  #
+  INF Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+  INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+
+  #
+  # USB Ehci Controller
+  #
+  INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+
+  #
+  # USB Ohci Controller
+  #
+  INF Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf
+
+  #
+  # USB Dwc3 Controller
+  #
+  INF Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
+  #
+  # USB Xhci Controller
+  #
+  INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+
+  #
+  # USB Host Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+  #
+  # USB Mass Storage Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # USB Kb Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+  #
+  # USB Mouse Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+
+  #
+  # USB MouseAbsolutePointer Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointerDxe.inf
+
+  #
+  # USB Peripheral Support
+  #
+  INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
+
+  #
+  # Fastboot
+  #
+  INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
+
+
+  #PCIe
+  #INF Silicon/Rockchip/Drivers/PciPlatform/PcieInitDxe.inf
+
+  # Required by PCI
+  INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
+  # PCI Support
+  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  #INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+  #INF MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.inf
+
+  #INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+  INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+  #
+  # Android Boot applications
+  #
+  INF EmbeddedPkg/Application/AndroidBoot/AndroidBootApp.inf
+
+  #
+  # UEFI Network Stack
+  #
+!include NetworkPkg/Network.fdf.inc
+
+  #
+  # AX88772 Ethernet Driver for Apple Ethernet Adapter
+  #
+  INF Drivers/ASIX/Bus/Usb/UsbNetworking/Ax88772c/Ax88772c.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF FatPkg/EnhancedFatDxe/Fat.inf
+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  #
+  # Multimedia Card Interface
+  #
+  # INF Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  INF Silicon/Rockchip/Drivers/MmcDxe/MmcDxe.inf
+  # sdcard is dwemmc, sdhci is for eMMC.
+  INF Silicon/Rockchip/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  
+  #
+  # DWC SDHCI (for eMMC slot)
+  #
+  INF Silicon/Rockchip/Drivers/SdhciHostDxe/SdhciHostDxe.inf
+
+  #
+  # AHCI Support
+  #
+  INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+  #
+  # SPI NOR FLASH
+  #
+  INF Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.inf
+
+  #
+  # Non-volatile FVB support
+  #
+  INF Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.inf
+  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+
+  # Human interface
+  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  # Custom
+  INF Silicon/Rockchip/Applications/MaskromReset/maskrom.inf
+  
+  # SCMI Driver
+  INF ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf
+
+  #
+  # UEFI applications
+  #
+  INF ShellPkg/Application/Shell/Shell.inf
+!ifdef $(INCLUDE_TFTP_COMMAND)
+  INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+!endif #$(INCLUDE_TFTP_COMMAND)
+  #INF Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+
+  #
+  # Bds
+  #
+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+[FV.BL33_AP_UEFI]
+FvAlignment        = 8
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+
+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FVMAIN
+    }
+  }
+
+!include Silicon/Rockchip/Rockchip.fdf.inc
+
+!ifdef $(ROCKCHIP_ACPIEN)
+[Rule.Common.DXE_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX	 DXE_DEPEX		Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32	 PE32			$(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI		 STRING="$(MODULE_NAME)" Optional
+    RAW 	 ACPI  Optional 	      |.acpi
+    RAW 	 ASL   Optional 	      |.aml
+  }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW ACPI		   |.acpi
+    RAW ASL		   |.aml
+  }
+!endif
--- a/edk2-platforms/Platform/FriendlyElec/NanoPC-T6/AcpiTables/AcpiTables.inf
+++ b/edk2-platforms/Platform/FriendlyElec/NanoPC-T6/AcpiTables/AcpiTables.inf
@@ -0,0 +1,64 @@
+#/** @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2019-2021, ARM Limited. All rights reserved.
+#  Copyright (c) Microsoft Corporation. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+  RK_COMMON_ACPI_DIR             = Silicon/Rockchip/RK3588/AcpiTables
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+
+[Sources]
+  Dsdt.asl
+  $(RK_COMMON_ACPI_DIR)/Madt.aslc
+  $(RK_COMMON_ACPI_DIR)/Fadt.aslc
+  $(RK_COMMON_ACPI_DIR)/Gtdt.aslc
+  $(RK_COMMON_ACPI_DIR)/Spcr.aslc
+  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
+  $(RK_COMMON_ACPI_DIR)/RK3588PcieIort.aslc
+  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Rockchip/RockchipPkg.dec
+  Platform/Rockchip/RK3588/RK3588.dec
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
--- a/edk2-platforms/Platform/FriendlyElec/NanoPC-T6/AcpiTables/Dsdt.asl
+++ b/edk2-platforms/Platform/FriendlyElec/NanoPC-T6/AcpiTables/Dsdt.asl
@@ -0,0 +1,41 @@
+/** @file
+ *
+ *  Differentiated System Definition Table (DSDT)
+ *
+ *  Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ *  Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
+ *  Copyright (c) Microsoft Corporation. All rights reserved.
+ *  Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include "AcpiTables.h"
+
+DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
+{
+  Scope (\_SB_)
+  {
+    include ("Cpu.asl")
+
+    include ("Pcie.asl")
+    include ("Sata0.asl")
+    include ("Sata1.asl")
+    include ("Sata2.asl")
+    include ("Emmc.asl")
+    include ("Sdhc.asl")
+    // include ("Gmac.asl")
+    // include ("Gpio.asl")
+    // include ("I2c.asl")
+    include ("Uart.asl")
+    // include ("Spi.asl")
+
+    // won't work on Windows, will trigger bugcheck by usbehci
+    // include ("Usb2.asl")
+
+    include ("Usb3Host0.asl")
+    include ("Usb3Host1.asl")
+    // include ("Usb3Host2.asl")
+  }
+}
--- a/edk2-platforms/Platform/FriendlyElec/NanoPC-T6/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-platforms/Platform/FriendlyElec/NanoPC-T6/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -0,0 +1,297 @@
+/** @file
+*
+*  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include <Base.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/GpioLib.h>
+#include <Library/RK806.h>
+#include <Soc.h>
+
+static struct regulator_init_data rk806_init_data[] = {
+  /* Master PMIC */
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
+  //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+
+  /* No dual PMICs on this platform */
+};
+
+VOID
+EFIAPI
+DwEmmcDxeIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux (microSD socket) */
+  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+}
+
+VOID
+EFIAPI
+SdhciEmmcDxeIoMux (
+  VOID
+  )
+{
+  /* sdhci0 iomux (eMMC socket) */
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+}
+
+#define NS_CRU_BASE         0xFD7C0000
+#define CRU_CLKSEL_CON59    0x03EC
+#define CRU_CLKSEL_CON78    0x0438
+
+VOID
+EFIAPI
+Rk806SpiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
+  PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+}
+
+VOID
+EFIAPI
+Rk806Configure (
+  VOID
+  )
+{
+  UINTN RegCfgIndex;
+
+  RK806Init();
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
+    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+}
+
+VOID
+EFIAPI
+SetCPULittleVoltage (
+  IN UINT32 Microvolts
+  )
+{
+  struct regulator_init_data Rk806CpuLittleSupply =
+        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+
+  RK806RegulatorInit(Rk806CpuLittleSupply);
+}
+
+VOID
+EFIAPI
+NorFspiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
+             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
+#define FSPI_M1
+#if defined(FSPI_M0)
+   /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
+#elif defined(FSPI_M1)
+  /*FSPI M1*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
+#else
+  /*FSPI M2*/
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
+#endif
+}
+
+VOID
+EFIAPI
+GmacIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    /* gmac0 iomux */
+    BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+    BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+    BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+    BUS_IOC->GPIO2C_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+    BUS_IOC->GPIO4C_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0100;
+    BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011;
+    break;
+  case 1:
+    /* gmac1 iomux */
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+NorFspiEnableClock (
+  UINT32 *CruBase
+  )
+{
+  UINTN BaseAddr = (UINTN) CruBase;
+
+  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+}
+
+VOID
+EFIAPI
+I2cIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    /* io mux M2 */
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
+    break;
+  case 1:
+    /* io mux */
+    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
+    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
+    break;
+  case 2:
+    /* io mux */
+    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
+    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
+    PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
+    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    break;
+  case 3:
+    break;
+  case 4:
+    break;
+  case 5:
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+UsbPortPowerEnable (
+  VOID
+  )
+{
+  DEBUG((EFI_D_WARN, "UsbPortPowerEnable called\n"));
+  /* Set GPIO4 PB0 (USB_HOST_PWREN) output high to power USB ports */
+  GpioPinWrite (4, GPIO_PIN_PB0, TRUE);
+  GpioPinSetDirection (4, GPIO_PIN_PB0, GPIO_PIN_OUTPUT);
+
+  /* Set GPIO1 PD2 (TYPEC5V_PWREN) output high to power the type-c port */
+  GpioPinWrite (1, GPIO_PIN_PD2, TRUE);
+  GpioPinSetDirection (1, GPIO_PIN_PD2, GPIO_PIN_OUTPUT);
+
+  // DEBUG((EFI_D_WARN, "Trying to enable on-board LED1\n"));
+  // GpioPinWrite (2, GPIO_PIN_PC0, TRUE);
+  // GpioPinSetDirection (2, GPIO_PIN_PC0, GPIO_PIN_OUTPUT);
+}
+
+VOID
+EFIAPI
+Usb2PhyResume (
+  VOID
+  )
+{
+  MmioWrite32(0xfd5d0008, 0x20000000);
+  MmioWrite32(0xfd5d4008, 0x20000000);
+  MmioWrite32(0xfd5d8008, 0x20000000);
+  MmioWrite32(0xfd5dc008, 0x20000000);
+  MmioWrite32(0xfd7f0a10, 0x07000700);
+  MmioWrite32(0xfd7f0a10, 0x07000000);
+}
+
+VOID
+EFIAPI
+UsbDpPhyEnable (
+  VOID
+  )
+{
+  /* enable rx_lfps_en & usbdp_low_pwrn */
+  MmioWrite32(0xfd5c8004, 0x60006000);
+  MmioWrite32(0xfd5cc004, 0x60006000);
+  
+  /* remove rx-termination, we don't support SS yet */
+  MmioWrite32 (0xfd5c800c, 0x00030001);
+  MmioWrite32 (0xfd5cc00c, 0x00030001);
+}
+
+VOID
+EFIAPI
+Pcie30IoInit (
+  VOID
+  )
+{
+  /* Set reset and power IO to gpio output mode */
+  GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
+  GpioPinSetDirection (2, GPIO_PIN_PC5, GPIO_PIN_OUTPUT);
+}
+
+VOID
+EFIAPI
+Pcie30PowerEn (
+  VOID
+  )
+{
+  /* output high to enable power */
+  GpioPinWrite (2, GPIO_PIN_PC5, TRUE);
+}
+
+VOID
+EFIAPI
+Pcie30PeReset (
+  BOOLEAN enable
+  )
+{
+  if(enable)
+    GpioPinWrite (4, GPIO_PIN_PB6, FALSE); /* output low */
+  else
+    GpioPinWrite (4, GPIO_PIN_PB6, TRUE); /* output high */
+}
+
+VOID
+EFIAPI
+PlatformEarlyInit (
+  VOID
+  )
+{
+  // Configure various things specific to this platform
+}
--- a/edk2-platforms/Platform/FriendlyElec/NanoPC-T6/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+++ b/edk2-platforms/Platform/FriendlyElec/NanoPC-T6/Library/RockchipPlatformLib/RockchipPlatformLib.inf
@@ -0,0 +1,43 @@
+#
+#  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = RockchipPlatformLib
+  FILE_GUID                      = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RockchipPlatformLib
+  RKPLATLIB_COMMON_DIR           = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Platform/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  SerialPortLib
+  CruLib
+  GpioLib
+
+[Sources.common]
+  RockchipPlatformLib.c
+  $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c
+  $(RKPLATLIB_COMMON_DIR)/RockchipSdhci.c
+
+[Sources.AARCH64]
+
+[Pcd]
+  gRockchipTokenSpaceGuid.PcdSdhciDxeBaseAddress
+  gRockchipTokenSpaceGuid.PcdI2cBusCount
+
--- a/edk2-platforms/Platform/FriendlyElec/NanoPC-T6/NanoPC-T6.dsc
+++ b/edk2-platforms/Platform/FriendlyElec/NanoPC-T6/NanoPC-T6.dsc
@@ -0,0 +1,639 @@
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2021-2022, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = NanoPC-T6
+  PLATFORM_GUID                  = d080df36-45e7-11ec-9726-f42a7dcb925d
+  PLATFORM_VERSION               = 0.2
+  DSC_SPECIFICATION              = 0x00010019
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = Platform/FriendlyElec/NanoPC-T6/NanoPC-T6.fdf
+
+  DEFINE CONFIG_NO_DEBUGLIB      = TRUE
+
+  #
+  # Must match defines in Silicon/Rockchip/RK3588/Include/VarStoreData.h
+  #
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT  = 0
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_MIN          = 1
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_MAX          = 2
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_CUSTOM       = 3
+
+  DEFINE COMBO_PHY_MODE_UNCONNECTED   = 0
+  DEFINE COMBO_PHY_MODE_PCIE          = 1
+  DEFINE COMBO_PHY_MODE_SATA          = 2
+  DEFINE COMBO_PHY_MODE_USB3          = 3
+
+  #
+  # Network definition
+  #
+  DEFINE NETWORK_SNP_ENABLE             = FALSE
+  DEFINE NETWORK_IP6_ENABLE             = FALSE
+  DEFINE NETWORK_TLS_ENABLE             = FALSE
+  DEFINE NETWORK_HTTP_BOOT_ENABLE       = FALSE
+  DEFINE NETWORK_ISCSI_ENABLE           = FALSE
+  DEFINE NETWORK_VLAN_ENABLE            = FALSE
+!include Silicon/Rockchip/Rockchip.dsc.inc
+!include MdePkg/MdeLibs.dsc.inc
+
+!if $(ENABLE_SIMPLE_INIT)
+  !include SimpleInit.inc
+!endif
+
+[LibraryClasses.common]
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmPlatformLib|Silicon/Rockchip/RK3588/Library/PlatformLib/PlatformLib.inf
+  AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf
+  CruLib|Silicon/Rockchip/Library/CruLib/CruLib.inf
+
+  DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
+
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+  # UiApp dependencies
+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+
+  #RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+  TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
+
+  # USB Requirements
+  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+
+  # PCIe
+  PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+  PciHostBridgeLib|Silicon/Rockchip/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+  PciExpressLib|Silicon/Rockchip/Library/PciExpressLib/PciExpressLib.inf
+  PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+
+
+  # VariableRuntimeDxe Requirements
+  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+  AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+  TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+  VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+
+  AndroidBootImgLib|edk2/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.inf
+
+  RockchipDisplayLib|Silicon/Rockchip/Library/DisplayLib/RockchipDisplayLib.inf
+
+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+  LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf
+
+  # OTP Library
+  OtpLib|Silicon/Rockchip/RK3588/Library/OtpLib/OtpLib.inf
+
+  #
+  # Custom libraries
+  #
+  RockchipPlatformLib|Platform/FriendlyElec/NanoPC-T6/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+  ResetSystemLib|Silicon/Rockchip/Library/ResetSystemLib/ResetSystemLib.inf
+  PlatformBootManagerLib|Silicon/Rockchip/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+  SerialPortLib|Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf
+  GpioLib|Silicon/Rockchip/RK3588/Library/GpioLib/GpioLib.inf
+  # SCMI Mailbox Transport Layer
+  ArmMtlLib|Silicon/Rockchip/Library/RkMtlLib/RkMtlLib.inf
+
+[LibraryClasses.common.SEC]
+  PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+  ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+  HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
+  MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+  MemoryInitPeiLib|Silicon/Rockchip/RK3588/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
+  PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+  PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+  RockchipPlatformLib|Platform/FriendlyElec/NanoPC-T6/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+
+[BuildOptions]
+  GCC:*_*_*_PLATFORM_FLAGS = -I$(WORKSPACE)/Silicon/Rockchip/RK3588/Include -I$(WORKSPACE)/Platform/Rockchip/RK3588/Include -I$(WORKSPACE)/Silicon/Rockchip/Include
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+  #  If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+  #  It could be set FALSE to save size.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+
+[PcdsFixedAtBuild.common]
+  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)"
+
+  # System Memory (1GB)
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000
+  
+  # RK3588 CPU profile
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|8
+  gArmPlatformTokenSpaceGuid.PcdClusterCount|1
+
+  # SMBIOS platform config
+  gRockchipTokenSpaceGuid.PcdPlatformName|"NanoPC T6"
+  gRockchipTokenSpaceGuid.PcdPlatformVendorName|"FriendlyElec"
+  gRockchipTokenSpaceGuid.PcdFamilyName|"NanoPi 6"
+  gRockchipTokenSpaceGuid.PcdProductUrl|"https://wiki.friendlyelec.com/wiki/index.php/NanoPC-T6"
+  gRockchipTokenSpaceGuid.PcdMemoryVendorName|"TBD"
+
+  # I2C
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 }
+  gRockchipTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0 }
+  gRockchipTokenSpaceGuid.PcdI2cClockFrequency|198000000
+  gRockchipTokenSpaceGuid.PcdI2cBaudRate|100000
+  gRockchipTokenSpaceGuid.PcdI2cBusCount|1
+  gRockchipTokenSpaceGuid.PcdI2cDemoAddresses|{ 0x51 } #/* RTCYM8563TS 0x51@bus2 */
+  gRockchipTokenSpaceGuid.PcdI2cDemoBuses|{ 0x2 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ 2, 3 } # SCMI_CLK_CPUB01, SCMI_CLK_CPUB23
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorMinVoltages|{ UINT32(550000), UINT32(550000) }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorMaxVoltages|{ UINT32(1050000), UINT32(1050000) }
+
+  ## UART2 - Serial Terminal
+  DEFINE SERIAL_BASE = 0xFEB50000 # UART2
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|$(SERIAL_BASE)
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|1500000
+  gHisiTokenSpaceGuid.PcdSerialPortSendDelay|500000
+  gHisiTokenSpaceGuid.PcdUartClkInHz|24000000
+
+  ## SPI - SPI2 for test
+  gRockchipTokenSpaceGuid.SpiTestBaseAddr|0xFEB20000
+  gRockchipTokenSpaceGuid.SpiRK806BaseAddr|0xFEB20000
+  ## PL031 RealTimeClock
+  #gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0xF8003000
+
+  ## NOR FLASH
+  gRockchipTokenSpaceGuid.FspiBaseAddr|0xFE2B0000
+
+  ## CRU
+  gRockchipTokenSpaceGuid.CruBaseAddr|0xFD7C0000
+
+  #gRockchipTokenSpaceGuid.PcdSpiVariableOffset|0x3C0000
+  #
+  # ARM General Interrupt Controller
+  #
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0xfe600000
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xfe600000
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0xfe680000
+
+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3
+
+  # GUID of the UI app
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+
+  gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
+
+  #
+  # DW SD card controller
+  #
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeBaseAddress|0xfe2c0000
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz|100000000
+  gDesignWareTokenSpaceGuid.PcdDwPermitObsoleteDrivers|TRUE
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeFifoDepth|256
+  #
+  # SDHCI controller
+  #
+  gRockchipTokenSpaceGuid.PcdSdhciDxeBaseAddress|0xfe2e0000
+
+  #
+  # PCIe controller
+  #
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress|0xfe150000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress|0xf5000000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress|0xf0000000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize|0x100000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress|0xf0100000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize|0x10000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress|0xf0200000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize|0xe00000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64|0x901000000 #deduct 0x1000000 ECAM space
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64|0x3f000000
+
+  #
+  # Fastboot
+  #
+  gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbVendorId|0x2207
+  gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbProductId|0x0001
+
+  #
+  # USB2 EHCI + OHCI companion controllers
+  #
+  gRockchipTokenSpaceGuid.PcdEhciBaseAddress|0xfc800000
+  gRockchipTokenSpaceGuid.PcdNumEhciController|2
+  gRockchipTokenSpaceGuid.PcdEhciSize|0x40000
+  gRockchipTokenSpaceGuid.PcdOhciSize|0x40000
+
+  #
+  # DWC3 controller
+  #
+  gRockchipTokenSpaceGuid.PcdDwc3BaseAddresses|{ UINT32(0xfc000000), UINT32(0xfc400000) }
+  gRockchipTokenSpaceGuid.PcdDwc3Size|0x400000
+
+  #
+  # Android Loader
+  #
+  gRK3588TokenSpaceGuid.PcdAndroidBootDevicePath|L"\\EFI\\BOOT\\GRUBAA64.EFI"
+  gRK3588TokenSpaceGuid.PcdSdBootDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00E023F70000000000)/SD(0x0)"
+  gRK3588TokenSpaceGuid.PcdKernelBootArg|L"earlycon=uart8250,mmio32,0xfeb50000 root=PARTUUID=614e0000-0000 rw rootwait"
+  gEmbeddedTokenSpaceGuid.PcdAndroidBootDevicePath|L"VenHw(100C2CFA-B586-4198-9B4C-1683D195B1DA)/HD(3,GPT,7A3F0000-0000-446A-8000-702F00006273,0x8000,0x20000)"
+
+  # ACPI Enable
+  gRK3588TokenSpaceGuid.AcpiEnable|TRUE
+
+  #
+  # Display
+  #
+  gRockchipTokenSpaceGuid.PcdLcdPixelFormat|0x00000001
+  gRockchipTokenSpaceGuid.PcdEdpId|0x00000000 #edp0
+  #gRockchipTokenSpaceGuid.PcdEdpId|0x00000001 #edp1
+  gRockchipTokenSpaceGuid.PcdHdmiId|0x00000000 #hdmi0
+  #gRockchipTokenSpaceGuid.PcdHdmiId|0x00000001 #hdmi1
+
+  #
+  # CPU Performance default values
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE)
+  gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_PCIE)
+  gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3)
+
+  #  BIT0  - Initialization message.<BR>
+  #  BIT1  - Warning message.<BR>
+  #  BIT2  - Load Event message.<BR>
+  #  BIT3  - File System message.<BR>
+  #  BIT4  - Allocate or Free Pool message.<BR>
+  #  BIT5  - Allocate or Free Page message.<BR>
+  #  BIT6  - Information message.<BR>
+  #  BIT7  - Dispatcher message.<BR>
+  #  BIT8  - Variable message.<BR>
+  #  BIT10 - Boot Manager message.<BR>
+  #  BIT12 - BlockIo Driver message.<BR>
+  #  BIT14 - Network Driver message.<BR>
+  #  BIT16 - UNDI Driver message.<BR>
+  #  BIT17 - LoadFile message.<BR>
+  #  BIT19 - Event message.<BR>
+  #  BIT20 - Global Coherency Database changes message.<BR>
+  #  BIT21 - Memory range cachability changes message.<BR>
+  #  BIT22 - Detailed debug message.<BR>
+  #  BIT31 - Error message.<BR>
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0e
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000000
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0f
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x800B0507
+!endif
+# 0x800B05C7
+# Use 0x807B55FF to enable all debug messages
+
+[PcdsDynamicDefault.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x007C0000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x007CF000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x007D0000
+
+  #
+  # Display
+  #
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x780
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x438
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0
+
+[PcdsDynamicHii.common.DEFAULT]
+  #
+  # CPU Performance
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPreset|L"CpuPerf_CPULClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockCustom|L"CpuPerf_CPULClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|1800
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPreset|L"CpuPerf_CPUB01ClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockCustom|L"CpuPerf_CPUB01ClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|2400
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPreset|L"CpuPerf_CPUB23ClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockCustom|L"CpuPerf_CPUB23ClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|2400
+  gRK3588TokenSpaceGuid.PcdCPULClusterVoltageMode|L"CpuPerf_CPULClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0
+  gRK3588TokenSpaceGuid.PcdCPULClusterVoltageCustom|L"CpuPerf_CPULClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|950000
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterVoltageMode|L"CpuPerf_CPUB01ClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterVoltageCustom|L"CpuPerf_CPUB01ClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|1000000
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterVoltageMode|L"CpuPerf_CPUB23ClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterVoltageCustom|L"CpuPerf_CPUB23ClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|1000000
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY
+  #
+  gRK3588TokenSpaceGuid.PcdComboPhy0Mode|L"ComboPhy0Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault
+  gRK3588TokenSpaceGuid.PcdComboPhy1Mode|L"ComboPhy1Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault
+  gRK3588TokenSpaceGuid.PcdComboPhy2Mode|L"ComboPhy2Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault
+  
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+  #
+  # PEI Phase modules
+  #
+  ArmPlatformPkg/PrePi/PeiUniCore.inf
+  MdeModulePkg/Core/Pei/PeiMain.inf
+  MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+
+  #
+  # DXE
+  #
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+  }
+
+  #
+  # Architectural Protocols
+  #
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+  #EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
+  <LibraryClasses>
+    RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
+  }
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  #PCIe
+  Silicon/Rockchip/Library/PciExpressLib/PciExpressLib.inf
+  Silicon/Rockchip/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+  Silicon/Rockchip/Drivers/PciPlatform/PcieInitDxe.inf
+  ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+  #MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.inf
+
+  MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+  
+  #
+  # Non-volatile FVB support
+  #
+  Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.inf
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+
+  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf
+  #Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
+  Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf
+  Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
+
+  #
+  # TianoCore logo (splash screen)
+  #
+  MdeModulePkg/Logo/LogoDxe.inf
+
+  #
+  # SCMI Driver
+  #
+  ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf
+
+  #
+  # ACPI Support
+  #
+  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+  Platform/FriendlyElec/NanoPC-T6/AcpiTables/AcpiTables.inf
+
+  #
+  # Device tree
+  #
+  EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf {
+  <LibraryClasses>
+    DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefault/DxeDtPlatformDtbLoaderLibDefault.inf
+  }
+
+  #
+  # GPIO
+  #
+  Platform/Rockchip/RK3588/RK3588GpioDxe/RK3588GpioDxe.inf
+
+  #
+  # Virtual Keyboard
+  #
+  EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
+
+  # I2C drivers
+  Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.inf
+  MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
+  Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.inf
+  Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.inf
+  Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.inf
+
+  #
+  # MMC/SD
+  #
+  #EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
+  #Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  Silicon/Rockchip/Drivers/MmcDxe/MmcDxe.inf
+  Silicon/Rockchip/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  Silicon/Rockchip/Drivers/SdhciHostDxe/SdhciHostDxe.inf
+
+  #
+  # NOR FLASH
+  #
+  Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.inf
+  Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+
+  #
+  # AHCI Support
+  #
+  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+  #
+  # SPI TEST
+  #
+  # Silicon/Rockchip/Library/SpiLib/SpiTest.inf
+
+  #
+  # SMBIOS Support
+  #
+  Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  
+  #
+  # USB Ohci Controller
+  #
+  Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf
+
+  #
+  # USB Ehci Controller
+  #
+  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+
+  #
+  # USB Dwc3 Controller
+  #
+  Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
+  #
+  # USB Xhci Controller
+  #
+  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+
+  #
+  # USB Host Support
+  #
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+  #
+  # USB Mass Storage Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # USB Kb Support
+  #
+  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+  #
+  # USB Mouse Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+
+  #
+  # USB MouseAbsolutePointer Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointerDxe.inf
+
+  #
+  # USB Peripheral Support
+  #
+  EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
+
+  #
+  # Fastboot
+  #
+  EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
+
+  #
+  # Android Boot applications
+  #
+  EmbeddedPkg/Application/AndroidBoot/AndroidBootApp.inf
+
+  #
+  # UEFI Network Stack
+  #
+!include NetworkPkg/Network.dsc.inc
+  #
+  # AX88772 Ethernet Driver
+  #
+  Drivers/ASIX/Bus/Usb/UsbNetworking/Ax88772c/Ax88772c.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+  MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf
+  FatPkg/EnhancedFatDxe/Fat.inf
+
+  #
+  # Bds
+  #
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  MdeModulePkg/Application/UiApp/UiApp.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  ShellPkg/Application/Shell/Shell.inf {
+    <LibraryClasses>
+      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+      NULL|Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.inf
+      NULL|Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf
+      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+      OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
+      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+      gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+  }
+!ifdef $(INCLUDE_TFTP_COMMAND)
+  ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+!endif #$(INCLUDE_TFTP_COMMAND)
+
+  #
+  # Custom Applications and drivers
+  #
+  Silicon/Rockchip/Applications/MaskromReset/maskrom.inf
+
+  # Platform drivers
+  Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf
+
--- a/edk2-platforms/Platform/FriendlyElec/NanoPC-T6/NanoPC-T6.fdf
+++ b/edk2-platforms/Platform/FriendlyElec/NanoPC-T6/NanoPC-T6.fdf
@@ -0,0 +1,384 @@
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2021-2022, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.NOR_FLASH_IMAGE]
+BaseAddress   = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
+Size          = 0x00800000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize     = 0x00001000
+NumBlocks     = 0x800
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+0x00200000|0x00500000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = BL33_AP_UEFI
+
+# NV_VARIABLE_STORE
+0x007C0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+
+# NV_FTW_WORKING header
+0x007D0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+# NV_FTW_WORKING data
+0x007E0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+BlockSize          = 0x40
+NumBlocks          = 0         # This FV gets compressed so make it just big enough
+FvAlignment        = 8         # FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  APRIORI DXE {
+    INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+  }
+
+  INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+  #
+  # PI DXE Drivers producing Architectural Protocols (EFI Services)
+  #
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  #
+  # Multiple Console IO support
+  #
+  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+
+  INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+
+  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  #
+  # ACPI Support
+  #
+  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+  INF RuleOverride = ACPITABLE Platform/FriendlyElec/NanoPC-T6/AcpiTables/AcpiTables.inf
+
+  #
+  # Device tree
+  #
+  INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf
+  # FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 {
+  #   SECTION RAW = Platform/Rockchip/DeviceTree/rk3588.dtb
+  # }
+
+  #
+  # GPIO
+  #
+  INF Platform/Rockchip/RK3588/RK3588GpioDxe/RK3588GpioDxe.inf
+  #INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf
+
+  #
+  # I2C
+  #
+  INF Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.inf
+  INF MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
+  # INF Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.inf
+  INF Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.inf
+
+  #
+  # Virtual Keyboard
+  #
+  INF EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
+
+  #
+  # Display Support
+  #
+  
+  INF Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf
+  #INF Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
+  INF Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf
+  INF Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
+  INF MdeModulePkg/Logo/LogoDxe.inf
+
+  INF Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf
+
+  #
+  # SMBIOS Support
+  #
+  INF Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+  INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+
+  #
+  # USB Ehci Controller
+  #
+  INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+
+  #
+  # USB Ohci Controller
+  #
+  INF Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf
+
+  #
+  # USB Dwc3 Controller
+  #
+  INF Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
+  #
+  # USB Xhci Controller
+  #
+  INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+
+  #
+  # USB Host Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+  #
+  # USB Mass Storage Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # USB Kb Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+  #
+  # USB Mouse Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+
+  #
+  # USB MouseAbsolutePointer Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointerDxe.inf
+
+  #
+  # USB Peripheral Support
+  #
+  INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
+
+  #
+  # Fastboot
+  #
+  INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
+
+
+  #PCIe
+  INF Silicon/Rockchip/Drivers/PciPlatform/PcieInitDxe.inf
+
+  # Required by PCI
+  INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
+  # PCI Support
+  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+  #INF MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.inf
+
+  #INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+  INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+  #
+  # Android Boot applications
+  #
+  INF EmbeddedPkg/Application/AndroidBoot/AndroidBootApp.inf
+
+  #
+  # UEFI Network Stack
+  #
+!include NetworkPkg/Network.fdf.inc
+
+  #
+  # AX88772 Ethernet Driver for Apple Ethernet Adapter
+  #
+  INF Drivers/ASIX/Bus/Usb/UsbNetworking/Ax88772c/Ax88772c.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf
+  INF FatPkg/EnhancedFatDxe/Fat.inf
+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  #
+  # Multimedia Card Interface
+  #
+  # INF Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  INF Silicon/Rockchip/Drivers/MmcDxe/MmcDxe.inf
+  INF Silicon/Rockchip/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  
+  #
+  # DWC SDHCI (for eMMC slot)
+  #
+  INF Silicon/Rockchip/Drivers/SdhciHostDxe/SdhciHostDxe.inf
+
+  #
+  # AHCI Support
+  #
+  INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+  #
+  # SPI NOR FLASH
+  #
+  INF Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.inf
+
+  #
+  # Non-volatile FVB support
+  #
+  INF Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.inf
+  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+
+  # Human interface
+  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  # Custom
+  INF Silicon/Rockchip/Applications/MaskromReset/maskrom.inf
+  
+  # SCMI Driver
+  INF ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf
+
+  #
+  # UEFI applications
+  #
+  INF ShellPkg/Application/Shell/Shell.inf
+!ifdef $(INCLUDE_TFTP_COMMAND)
+  INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+!endif #$(INCLUDE_TFTP_COMMAND)
+  #INF Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+
+  #
+  # Bds
+  #
+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+  #
+  # Simple Init GUI
+  #
+!if $(ENABLE_SIMPLE_INIT)
+  INF src/main/SimpleInitMain.inf
+!endif
+
+[FV.BL33_AP_UEFI]
+FvAlignment        = 8
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+
+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FVMAIN
+    }
+  }
+
+!include Silicon/Rockchip/Rockchip.fdf.inc
+
+!ifdef $(ROCKCHIP_ACPIEN)
+[Rule.Common.DXE_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX	 DXE_DEPEX		Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32	 PE32			$(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI		 STRING="$(MODULE_NAME)" Optional
+    RAW 	 ACPI  Optional 	      |.acpi
+    RAW 	 ASL   Optional 	      |.aml
+  }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW ACPI		   |.acpi
+    RAW ASL		   |.aml
+  }
+!endif
--- a/edk2-platforms/Platform/Khadas/Drivers/LogoDxe/Logo.bmp
+++ b/edk2-platforms/Platform/Khadas/Drivers/LogoDxe/Logo.bmp
--- a/edk2-platforms/Platform/Khadas/Drivers/LogoDxe/Logo.c
+++ b/edk2-platforms/Platform/Khadas/Drivers/LogoDxe/Logo.c
@@ -0,0 +1,144 @@
+/** @file
+  Logo DXE Driver, install Edkii Platform Logo protocol.
+
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+  Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Protocol/HiiDatabase.h>
+#include <Protocol/GraphicsOutput.h>
+#include <Protocol/HiiImageEx.h>
+#include <Protocol/PlatformLogo.h>
+#include <Protocol/HiiPackageList.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+
+typedef struct {
+  EFI_IMAGE_ID                          ImageId;
+  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
+  INTN                                  OffsetX;
+  INTN                                  OffsetY;
+} LOGO_ENTRY;
+
+STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
+STATIC EFI_HII_HANDLE            mHiiHandle;
+STATIC LOGO_ENTRY                mLogos[] = {
+  {
+    IMAGE_TOKEN (IMG_LOGO),
+    EdkiiPlatformLogoDisplayAttributeCenter,
+    0,
+    0
+  }
+};
+
+/**
+  Load a platform logo image and return its data and attributes.
+
+  @param This              The pointer to this protocol instance.
+  @param Instance          The visible image instance is found.
+  @param Image             Points to the image.
+  @param Attribute         The display attributes of the image returned.
+  @param OffsetX           The X offset of the image regarding the Attribute.
+  @param OffsetY           The Y offset of the image regarding the Attribute.
+
+  @retval EFI_SUCCESS      The image was fetched successfully.
+  @retval EFI_NOT_FOUND    The specified image could not be found.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GetImage (
+  IN     EDKII_PLATFORM_LOGO_PROTOCOL          *This,
+  IN OUT UINT32                                *Instance,
+     OUT EFI_IMAGE_INPUT                       *Image,
+     OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
+     OUT INTN                                  *OffsetX,
+     OUT INTN                                  *OffsetY
+  )
+{
+  UINT32 Current;
+
+  if (Instance == NULL || Image == NULL ||
+      Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Current = *Instance;
+  if (Current >= ARRAY_SIZE (mLogos)) {
+    return EFI_NOT_FOUND;
+  }
+
+  (*Instance)++;
+  *Attribute = mLogos[Current].Attribute;
+  *OffsetX   = mLogos[Current].OffsetX;
+  *OffsetY   = mLogos[Current].OffsetY;
+
+  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
+                        mLogos[Current].ImageId, Image);
+}
+
+STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+  GetImage
+};
+
+/**
+  Entrypoint of this module.
+
+  This function is the entrypoint of this module. It installs the Edkii
+  Platform Logo protocol.
+
+  @param  ImageHandle       The firmware allocated handle for the EFI image.
+  @param  SystemTable       A pointer to the EFI System Table.
+
+  @retval EFI_SUCCESS       The entry point is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeLogo (
+  IN EFI_HANDLE               ImageHandle,
+  IN EFI_SYSTEM_TABLE         *SystemTable
+  )
+{
+  EFI_STATUS                  Status;
+  EFI_HII_PACKAGE_LIST_HEADER *PackageList;
+  EFI_HII_DATABASE_PROTOCOL   *HiiDatabase;
+  EFI_HANDLE                  Handle;
+
+  Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
+                  (VOID **) &HiiDatabase);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
+                  (VOID **) &mHiiImageEx);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Retrieve HII package list from ImageHandle
+  //
+  Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
+                  (VOID **) &PackageList, ImageHandle, NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR,
+      "HII Image Package with logo not found in PE/COFF resource section\n"));
+    return Status;
+  }
+
+  //
+  // Publish HII package list to HII Database.
+  //
+  Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
+                          &mHiiHandle);
+  if (!EFI_ERROR (Status)) {
+    Handle = NULL;
+    Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
+                    &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
+  }
+  return Status;
+}
--- a/edk2-platforms/Platform/Khadas/Drivers/LogoDxe/Logo.idf
+++ b/edk2-platforms/Platform/Khadas/Drivers/LogoDxe/Logo.idf
@@ -0,0 +1,10 @@
+// @file
+// Platform Logo image definition file.
+//
+// Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+// Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+
+#image IMG_LOGO Logo.bmp
--- a/edk2-platforms/Platform/Khadas/Drivers/LogoDxe/LogoDxe.inf
+++ b/edk2-platforms/Platform/Khadas/Drivers/LogoDxe/LogoDxe.inf
@@ -0,0 +1,48 @@
+## @file
+#  The default logo bitmap picture shown on setup screen.
+#
+#  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+#  Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = LogoDxe
+  FILE_GUID                      = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = InitializeLogo
+#
+#  This flag specifies whether HII resource section is generated into PE image.
+#
+  UEFI_HII_RESOURCE_SECTION      = TRUE
+
+[Sources]
+  Logo.bmp
+  Logo.c
+  Logo.idf
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  DebugLib
+
+[Protocols]
+  gEfiHiiDatabaseProtocolGuid        ## CONSUMES
+  gEfiHiiImageExProtocolGuid         ## CONSUMES
+  gEfiHiiPackageListProtocolGuid     ## PRODUCES CONSUMES
+  gEdkiiPlatformLogoProtocolGuid     ## PRODUCES
+
+[Depex]
+  gEfiHiiDatabaseProtocolGuid AND
+  gEfiHiiImageExProtocolGuid
--- a/edk2-platforms/Platform/Khadas/Edge2/AcpiTables/AcpiTables.inf
+++ b/edk2-platforms/Platform/Khadas/Edge2/AcpiTables/AcpiTables.inf
@@ -0,0 +1,64 @@
+#/** @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2019-2021, ARM Limited. All rights reserved.
+#  Copyright (c) Microsoft Corporation. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+  RK_COMMON_ACPI_DIR             = Silicon/Rockchip/RK3588/AcpiTables
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+
+[Sources]
+  Dsdt.asl
+  $(RK_COMMON_ACPI_DIR)/Madt.aslc
+  $(RK_COMMON_ACPI_DIR)/Fadt.aslc
+  $(RK_COMMON_ACPI_DIR)/Gtdt.aslc
+  $(RK_COMMON_ACPI_DIR)/Spcr.aslc
+  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
+  $(RK_COMMON_ACPI_DIR)/RK3588PcieIort.aslc
+  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Rockchip/RockchipPkg.dec
+  Platform/Rockchip/RK3588/RK3588.dec
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
--- a/edk2-platforms/Platform/Khadas/Edge2/AcpiTables/Dsdt.asl
+++ b/edk2-platforms/Platform/Khadas/Edge2/AcpiTables/Dsdt.asl
@@ -0,0 +1,38 @@
+/** @file
+ *
+ *  Differentiated System Definition Table (DSDT)
+ *
+ *  Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ *  Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
+ *  Copyright (c) Microsoft Corporation. All rights reserved.
+ *  Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include "AcpiTables.h"
+
+DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
+{
+  Scope (\_SB_)
+  {
+    include ("Cpu.asl")
+
+    // include ("Pcie.asl")
+    include ("Sata2.asl")
+    include ("Emmc.asl")
+    include ("Sdhc.asl")
+    // include ("Gmac.asl")
+    // include ("Gpio.asl")
+    // include ("I2c.asl")
+    include ("Uart.asl")
+    // include ("Spi.asl")
+
+    // won't work on Windows, will trigger bugcheck by usbehci
+    // include ("Usb2.asl")
+
+    include ("Usb3Host0.asl")
+    include ("Usb3Host2.asl")
+  }
+}
--- a/edk2-platforms/Platform/Khadas/Edge2/Edge2.dsc
+++ b/edk2-platforms/Platform/Khadas/Edge2/Edge2.dsc
@@ -0,0 +1,633 @@
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2021-2022, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = Edge2
+  PLATFORM_GUID                  = d080df36-45e7-11ec-9726-f42a7dcb925d
+  PLATFORM_VERSION               = 0.2
+  DSC_SPECIFICATION              = 0x00010019
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = Platform/Khadas/Edge2/Edge2.fdf
+
+  DEFINE CONFIG_NO_DEBUGLIB      = TRUE
+
+  #
+  # Must match defines in Silicon/Rockchip/RK3588/Include/VarStoreData.h
+  #
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT  = 0
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_MIN          = 1
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_MAX          = 2
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_CUSTOM       = 3
+
+  DEFINE COMBO_PHY_MODE_UNCONNECTED   = 0
+  DEFINE COMBO_PHY_MODE_PCIE          = 1
+  DEFINE COMBO_PHY_MODE_SATA          = 2
+  DEFINE COMBO_PHY_MODE_USB3          = 3
+
+  #
+  # Network definition
+  #
+  DEFINE NETWORK_SNP_ENABLE             = FALSE
+  DEFINE NETWORK_IP6_ENABLE             = FALSE
+  DEFINE NETWORK_TLS_ENABLE             = FALSE
+  DEFINE NETWORK_HTTP_BOOT_ENABLE       = FALSE
+  DEFINE NETWORK_ISCSI_ENABLE           = FALSE
+  DEFINE NETWORK_VLAN_ENABLE            = FALSE
+!include Silicon/Rockchip/Rockchip.dsc.inc
+!include MdePkg/MdeLibs.dsc.inc
+
+[LibraryClasses.common]
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmPlatformLib|Silicon/Rockchip/RK3588/Library/PlatformLib/PlatformLib.inf
+  AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf
+  CruLib|Silicon/Rockchip/Library/CruLib/CruLib.inf
+
+  DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
+
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+  # UiApp dependencies
+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+
+  #RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+  TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
+
+  # USB Requirements
+  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+
+  # PCIe
+  PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+  #PciHostBridgeLib|Silicon/Rockchip/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+  #PciExpressLib|Silicon/Rockchip/Library/PciExpressLib/PciExpressLib.inf
+  PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+
+
+  # VariableRuntimeDxe Requirements
+  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+  AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+  TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+  VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+
+  AndroidBootImgLib|edk2/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.inf
+
+  RockchipDisplayLib|Silicon/Rockchip/Library/DisplayLib/RockchipDisplayLib.inf
+
+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+  LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf
+
+  # OTP Library
+  OtpLib|Silicon/Rockchip/RK3588/Library/OtpLib/OtpLib.inf
+
+  #
+  # Custom libraries
+  #
+  RockchipPlatformLib|Platform/Khadas/Edge2/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+  ResetSystemLib|Silicon/Rockchip/Library/ResetSystemLib/ResetSystemLib.inf
+  PlatformBootManagerLib|Silicon/Rockchip/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+  SerialPortLib|Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf
+  GpioLib|Silicon/Rockchip/RK3588/Library/GpioLib/GpioLib.inf
+  # SCMI Mailbox Transport Layer
+  ArmMtlLib|Silicon/Rockchip/Library/RkMtlLib/RkMtlLib.inf
+
+[LibraryClasses.common.SEC]
+  PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+  ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+  HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
+  MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+  MemoryInitPeiLib|Silicon/Rockchip/RK3588/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
+  PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+  PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+  RockchipPlatformLib|Platform/Khadas/Edge2/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+
+[BuildOptions]
+  GCC:*_*_*_PLATFORM_FLAGS = -I$(WORKSPACE)/Silicon/Rockchip/RK3588/Include -I$(WORKSPACE)/Platform/Rockchip/RK3588/Include -I$(WORKSPACE)/Silicon/Rockchip/Include
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+  #  If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+  #  It could be set FALSE to save size.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+
+[PcdsFixedAtBuild.common]
+  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)"
+
+  # System Memory (1GB)
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000
+  gRK3588TokenSpaceGuid.PcdTotalMemorySize|0x200000000
+  
+  # RK3588 CPU profile
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|8
+  gArmPlatformTokenSpaceGuid.PcdClusterCount|1
+
+  # SMBIOS platform config
+  gRockchipTokenSpaceGuid.PcdPlatformName|"Edge2"
+  gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Khadas"
+  gRockchipTokenSpaceGuid.PcdFamilyName|"Edge"
+  gRockchipTokenSpaceGuid.PcdProductUrl|"https://www.khadas.com/edge2"
+  gRockchipTokenSpaceGuid.PcdMemoryVendorName|"TBD"
+
+  # I2C
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 }
+  gRockchipTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0 }
+  gRockchipTokenSpaceGuid.PcdI2cClockFrequency|198000000
+  gRockchipTokenSpaceGuid.PcdI2cBaudRate|100000
+  gRockchipTokenSpaceGuid.PcdI2cBusCount|1
+  gRockchipTokenSpaceGuid.PcdI2cDemoAddresses|{ 0x51 } #/* RTCYM8563TS 0x51@bus2 */
+  gRockchipTokenSpaceGuid.PcdI2cDemoBuses|{ 0x2 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ 2, 3 } # SCMI_CLK_CPUB01, SCMI_CLK_CPUB23
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorMinVoltages|{ UINT32(550000), UINT32(550000) }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorMaxVoltages|{ UINT32(1050000), UINT32(1050000) }
+
+  ## UART2 - Serial Terminal
+  DEFINE SERIAL_BASE = 0xFEB50000 # UART2
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|$(SERIAL_BASE)
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|1500000
+  gHisiTokenSpaceGuid.PcdSerialPortSendDelay|500000
+  gHisiTokenSpaceGuid.PcdUartClkInHz|24000000
+
+  ## SPI - SPI2 for test
+  gRockchipTokenSpaceGuid.SpiTestBaseAddr|0xFEB20000
+  gRockchipTokenSpaceGuid.SpiRK806BaseAddr|0xFEB20000
+  ## PL031 RealTimeClock
+  #gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0xF8003000
+
+  ## NOR FLASH
+  gRockchipTokenSpaceGuid.FspiBaseAddr|0xFE2B0000
+
+  ## CRU
+  gRockchipTokenSpaceGuid.CruBaseAddr|0xFD7C0000
+
+  #gRockchipTokenSpaceGuid.PcdSpiVariableOffset|0x3C0000
+  #
+  # ARM General Interrupt Controller
+  #
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0xfe600000
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xfe600000
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0xfe680000
+
+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3
+
+  # GUID of the UI app
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+
+  gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
+
+  #
+  # DW SD card controller
+  #
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeBaseAddress|0xfe2c0000
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz|100000000
+  gDesignWareTokenSpaceGuid.PcdDwPermitObsoleteDrivers|TRUE
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeFifoDepth|256
+  #
+  # SDHCI controller
+  #
+  gRockchipTokenSpaceGuid.PcdSdhciDxeBaseAddress|0xfe2e0000
+
+  #
+  # PCIe controller
+  #
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress|0xfe150000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress|0xf5000000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress|0xf0000000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize|0x100000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress|0xf0100000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize|0x10000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress|0xf0200000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize|0xe00000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64|0x901000000 #deduct 0x1000000 ECAM space
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64|0x3f000000
+
+  #
+  # Fastboot
+  #
+  gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbVendorId|0x2207
+  gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbProductId|0x0001
+
+  #
+  # USB2 EHCI + OHCI companion controllers
+  #
+  gRockchipTokenSpaceGuid.PcdEhciBaseAddress|0xfc800000
+  gRockchipTokenSpaceGuid.PcdNumEhciController|2
+  gRockchipTokenSpaceGuid.PcdEhciSize|0x40000
+  gRockchipTokenSpaceGuid.PcdOhciSize|0x40000
+
+  #
+  # DWC3 controller
+  #
+  gRockchipTokenSpaceGuid.PcdDwc3BaseAddresses|{ UINT32(0xfc000000), UINT32(0xfc400000), UINT32(0xfcd00000) }
+  gRockchipTokenSpaceGuid.PcdDwc3Size|0x400000
+
+  #
+  # Android Loader
+  #
+  gRK3588TokenSpaceGuid.PcdAndroidBootDevicePath|L"\\EFI\\BOOT\\GRUBAA64.EFI"
+  gRK3588TokenSpaceGuid.PcdSdBootDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00E023F70000000000)/SD(0x0)"
+  gRK3588TokenSpaceGuid.PcdKernelBootArg|L"earlycon=uart8250,mmio32,0xfeb50000 root=PARTUUID=614e0000-0000 rw rootwait"
+  gEmbeddedTokenSpaceGuid.PcdAndroidBootDevicePath|L"VenHw(100C2CFA-B586-4198-9B4C-1683D195B1DA)/HD(3,GPT,7A3F0000-0000-446A-8000-702F00006273,0x8000,0x20000)"
+
+  # ACPI Enable
+  gRK3588TokenSpaceGuid.AcpiEnable|TRUE
+
+  #
+  # Display
+  #
+  gRockchipTokenSpaceGuid.PcdLcdPixelFormat|0x00000001
+  gRockchipTokenSpaceGuid.PcdEdpId|0x00000000 #edp0
+  #gRockchipTokenSpaceGuid.PcdEdpId|0x00000001 #edp1
+  gRockchipTokenSpaceGuid.PcdHdmiId|0x00000000 #hdmi0
+  #gRockchipTokenSpaceGuid.PcdHdmiId|0x00000001 #hdmi1
+
+  #
+  # CPU Performance default values
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|FALSE
+  gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|FALSE
+  gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE)
+  gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_UNCONNECTED)
+  gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3)
+
+  #  BIT0  - Initialization message.<BR>
+  #  BIT1  - Warning message.<BR>
+  #  BIT2  - Load Event message.<BR>
+  #  BIT3  - File System message.<BR>
+  #  BIT4  - Allocate or Free Pool message.<BR>
+  #  BIT5  - Allocate or Free Page message.<BR>
+  #  BIT6  - Information message.<BR>
+  #  BIT7  - Dispatcher message.<BR>
+  #  BIT8  - Variable message.<BR>
+  #  BIT10 - Boot Manager message.<BR>
+  #  BIT12 - BlockIo Driver message.<BR>
+  #  BIT14 - Network Driver message.<BR>
+  #  BIT16 - UNDI Driver message.<BR>
+  #  BIT17 - LoadFile message.<BR>
+  #  BIT19 - Event message.<BR>
+  #  BIT20 - Global Coherency Database changes message.<BR>
+  #  BIT21 - Memory range cachability changes message.<BR>
+  #  BIT22 - Detailed debug message.<BR>
+  #  BIT31 - Error message.<BR>
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0e
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000000
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0f
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x800B0507
+!endif
+# 0x800B05C7
+# Use 0x807B55FF to enable all debug messages
+
+[PcdsDynamicDefault.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x007C0000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x007CF000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x007D0000
+
+  #
+  # Display
+  #
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x780
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x438
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0
+
+[PcdsDynamicHii.common.DEFAULT]
+  #
+  # CPU Performance
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPreset|L"CpuPerf_CPULClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockCustom|L"CpuPerf_CPULClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|1800
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPreset|L"CpuPerf_CPUB01ClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockCustom|L"CpuPerf_CPUB01ClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|2400
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPreset|L"CpuPerf_CPUB23ClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockCustom|L"CpuPerf_CPUB23ClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|2400
+  gRK3588TokenSpaceGuid.PcdCPULClusterVoltageMode|L"CpuPerf_CPULClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0
+  gRK3588TokenSpaceGuid.PcdCPULClusterVoltageCustom|L"CpuPerf_CPULClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|950000
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterVoltageMode|L"CpuPerf_CPUB01ClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterVoltageCustom|L"CpuPerf_CPUB01ClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|1000000
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterVoltageMode|L"CpuPerf_CPUB23ClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterVoltageCustom|L"CpuPerf_CPUB23ClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|1000000
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY
+  #
+  gRK3588TokenSpaceGuid.PcdComboPhy0Mode|L"ComboPhy0Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault
+  gRK3588TokenSpaceGuid.PcdComboPhy1Mode|L"ComboPhy1Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault
+  gRK3588TokenSpaceGuid.PcdComboPhy2Mode|L"ComboPhy2Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault
+  
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+  #
+  # PEI Phase modules
+  #
+  ArmPlatformPkg/PrePi/PeiUniCore.inf
+  MdeModulePkg/Core/Pei/PeiMain.inf
+  MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+
+  #
+  # DXE
+  #
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+  }
+
+  #
+  # Architectural Protocols
+  #
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+  #EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
+  <LibraryClasses>
+    RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
+  }
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  #PCIe
+  #Silicon/Rockchip/Library/PciExpressLib/PciExpressLib.inf
+  #Silicon/Rockchip/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+  #Silicon/Rockchip/Drivers/PciPlatform/PcieInitDxe.inf
+  ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  #MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+  #MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.inf
+
+  MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+  
+  #
+  # Non-volatile FVB support
+  #
+  Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.inf
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+
+  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf
+  #Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
+  Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf
+  Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
+
+  Platform/Khadas/Drivers/LogoDxe/LogoDxe.inf
+
+  #
+  # SCMI Driver
+  #
+  ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf
+
+  #
+  # ACPI Support
+  #
+  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+  Platform/Khadas/Edge2/AcpiTables/AcpiTables.inf
+
+  #
+  # Device tree
+  #
+  EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf {
+  <LibraryClasses>
+    DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefault/DxeDtPlatformDtbLoaderLibDefault.inf
+  }
+
+  #
+  # GPIO
+  #
+  Platform/Rockchip/RK3588/RK3588GpioDxe/RK3588GpioDxe.inf
+
+  #
+  # Virtual Keyboard
+  #
+  EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
+
+  # I2C drivers
+  Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.inf
+  MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
+  Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.inf
+  Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.inf
+  Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.inf
+
+  #
+  # MMC/SD
+  #
+  #EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
+  #Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  Silicon/Rockchip/Drivers/MmcDxe/MmcDxe.inf
+  # sdcard is dwemmc, sdhci is for eMMC.
+  Silicon/Rockchip/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  Silicon/Rockchip/Drivers/SdhciHostDxe/SdhciHostDxe.inf
+
+  #
+  # NOR FLASH
+  #
+  Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.inf
+  Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+
+  #
+  # AHCI Support
+  #
+  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+  #
+  # SPI TEST
+  #
+  # Silicon/Rockchip/Library/SpiLib/SpiTest.inf
+
+  #
+  # SMBIOS Support
+  #
+  Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  
+  #
+  # USB Ohci Controller
+  #
+  Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf
+
+  #
+  # USB Ehci Controller
+  #
+  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+
+  #
+  # USB Dwc3 Controller
+  #
+  Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
+  #
+  # USB Xhci Controller
+  #
+  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+
+  #
+  # USB Host Support
+  #
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+  #
+  # USB Mass Storage Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # USB Kb Support
+  #
+  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+  #
+  # USB Mouse Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+
+  #
+  # USB MouseAbsolutePointer Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointerDxe.inf
+
+  #
+  # USB Peripheral Support
+  #
+  EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
+
+  #
+  # Fastboot
+  #
+  EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
+
+  #
+  # Android Boot applications
+  #
+  EmbeddedPkg/Application/AndroidBoot/AndroidBootApp.inf
+
+  #
+  # UEFI Network Stack
+  #
+!include NetworkPkg/Network.dsc.inc
+  #
+  # AX88772 Ethernet Driver
+  #
+  Drivers/ASIX/Bus/Usb/UsbNetworking/Ax88772c/Ax88772c.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+  FatPkg/EnhancedFatDxe/Fat.inf
+
+  #
+  # Bds
+  #
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  MdeModulePkg/Application/UiApp/UiApp.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  ShellPkg/Application/Shell/Shell.inf {
+    <LibraryClasses>
+      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+      NULL|Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.inf
+      NULL|Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf
+      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+      OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
+      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+      gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+  }
+!ifdef $(INCLUDE_TFTP_COMMAND)
+  ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+!endif #$(INCLUDE_TFTP_COMMAND)
+
+  #
+  # Custom Applications and drivers
+  #
+  Silicon/Rockchip/Applications/MaskromReset/maskrom.inf
+
+  # Platform drivers
+  Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf
+
--- a/edk2-platforms/Platform/Khadas/Edge2/Edge2.fdf
+++ b/edk2-platforms/Platform/Khadas/Edge2/Edge2.fdf
@@ -0,0 +1,377 @@
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2021-2022, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.NOR_FLASH_IMAGE]
+BaseAddress   = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
+Size          = 0x00800000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize     = 0x00001000
+NumBlocks     = 0x800
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+0x00200000|0x00500000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = BL33_AP_UEFI
+
+# NV_VARIABLE_STORE
+0x007C0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+
+# NV_FTW_WORKING header
+0x007D0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+# NV_FTW_WORKING data
+0x007E0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+BlockSize          = 0x40
+NumBlocks          = 0         # This FV gets compressed so make it just big enough
+FvAlignment        = 8         # FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  APRIORI DXE {
+    INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+  }
+
+  INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+  #
+  # PI DXE Drivers producing Architectural Protocols (EFI Services)
+  #
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  #
+  # Multiple Console IO support
+  #
+  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+
+  INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+
+  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  #
+  # ACPI Support
+  #
+  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+  INF RuleOverride = ACPITABLE Platform/Khadas/Edge2/AcpiTables/AcpiTables.inf
+
+  #
+  # Device tree
+  #
+  INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf
+  # FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 {
+  #   SECTION RAW = Platform/Rockchip/DeviceTree/rk3588.dtb
+  # }
+
+  #
+  # GPIO
+  #
+  INF Platform/Rockchip/RK3588/RK3588GpioDxe/RK3588GpioDxe.inf
+  #INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf
+
+  #
+  # I2C
+  #
+  INF Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.inf
+  INF MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
+  # INF Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.inf
+  INF Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.inf
+
+  #
+  # Virtual Keyboard
+  #
+  INF EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
+
+  #
+  # Display Support
+  #
+  
+  INF Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf
+  #INF Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
+  INF Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf
+  INF Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
+  INF Platform/Khadas/Drivers/LogoDxe/LogoDxe.inf
+
+  INF Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf
+
+  #
+  # SMBIOS Support
+  #
+  INF Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+  INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+
+  #
+  # USB Ehci Controller
+  #
+  INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+
+  #
+  # USB Ohci Controller
+  #
+  INF Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf
+
+  #
+  # USB Dwc3 Controller
+  #
+  INF Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
+  #
+  # USB Xhci Controller
+  #
+  INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+
+  #
+  # USB Host Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+  #
+  # USB Mass Storage Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # USB Kb Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+  #
+  # USB Mouse Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+
+  #
+  # USB MouseAbsolutePointer Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointerDxe.inf
+
+  #
+  # USB Peripheral Support
+  #
+  INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
+
+  #
+  # Fastboot
+  #
+  INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
+
+
+  #PCIe
+  #INF Silicon/Rockchip/Drivers/PciPlatform/PcieInitDxe.inf
+
+  # Required by PCI
+  INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
+  # PCI Support
+  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  #INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+  #INF MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.inf
+
+  #INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+  INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+  #
+  # Android Boot applications
+  #
+  INF EmbeddedPkg/Application/AndroidBoot/AndroidBootApp.inf
+
+  #
+  # UEFI Network Stack
+  #
+!include NetworkPkg/Network.fdf.inc
+
+  #
+  # AX88772 Ethernet Driver for Apple Ethernet Adapter
+  #
+  INF Drivers/ASIX/Bus/Usb/UsbNetworking/Ax88772c/Ax88772c.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF FatPkg/EnhancedFatDxe/Fat.inf
+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  #
+  # Multimedia Card Interface
+  #
+  # INF Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  INF Silicon/Rockchip/Drivers/MmcDxe/MmcDxe.inf
+  # sdcard is dwemmc, sdhci is for eMMC.
+  INF Silicon/Rockchip/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  
+  #
+  # DWC SDHCI (for eMMC slot)
+  #
+  INF Silicon/Rockchip/Drivers/SdhciHostDxe/SdhciHostDxe.inf
+
+  #
+  # AHCI Support
+  #
+  INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+  #
+  # SPI NOR FLASH
+  #
+  INF Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.inf
+
+  #
+  # Non-volatile FVB support
+  #
+  INF Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.inf
+  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+
+  # Human interface
+  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  # Custom
+  INF Silicon/Rockchip/Applications/MaskromReset/maskrom.inf
+  
+  # SCMI Driver
+  INF ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf
+
+  #
+  # UEFI applications
+  #
+  INF ShellPkg/Application/Shell/Shell.inf
+!ifdef $(INCLUDE_TFTP_COMMAND)
+  INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+!endif #$(INCLUDE_TFTP_COMMAND)
+  #INF Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+
+  #
+  # Bds
+  #
+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+[FV.BL33_AP_UEFI]
+FvAlignment        = 8
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+
+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FVMAIN
+    }
+  }
+
+!include Silicon/Rockchip/Rockchip.fdf.inc
+
+!ifdef $(ROCKCHIP_ACPIEN)
+[Rule.Common.DXE_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX	 DXE_DEPEX		Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32	 PE32			$(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI		 STRING="$(MODULE_NAME)" Optional
+    RAW 	 ACPI  Optional 	      |.acpi
+    RAW 	 ASL   Optional 	      |.aml
+  }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW ACPI		   |.acpi
+    RAW ASL		   |.aml
+  }
+!endif
--- a/edk2-platforms/Platform/Khadas/Edge2/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-platforms/Platform/Khadas/Edge2/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -0,0 +1,289 @@
+/** @file
+*
+*  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include <Base.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/GpioLib.h>
+#include <Library/RK806.h>
+#include <Soc.h>
+
+static struct regulator_init_data rk806_init_data[] = {
+  /* Master PMIC */
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
+  //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+
+  /* No dual PMICs on this platform */
+};
+
+VOID
+EFIAPI
+DwEmmcDxeIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux */
+}
+
+VOID
+EFIAPI
+SdhciEmmcDxeIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux */
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+}
+
+#define NS_CRU_BASE         0xFD7C0000
+#define CRU_CLKSEL_CON59    0x03EC
+#define CRU_CLKSEL_CON78    0x0438
+
+VOID
+EFIAPI
+Rk806SpiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
+  PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+}
+
+VOID
+EFIAPI
+Rk806Configure (
+  VOID
+  )
+{
+  UINTN RegCfgIndex;
+
+  RK806Init();
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
+    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+}
+
+VOID
+EFIAPI
+SetCPULittleVoltage (
+  IN UINT32 Microvolts
+  )
+{
+  struct regulator_init_data Rk806CpuLittleSupply =
+        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+
+  RK806RegulatorInit(Rk806CpuLittleSupply);
+}
+
+VOID
+EFIAPI
+NorFspiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
+             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
+#define FSPI_M1
+#if defined(FSPI_M0)
+   /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
+#elif defined(FSPI_M1)
+  /*FSPI M1*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
+#else
+  /*FSPI M2*/
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
+#endif
+}
+
+VOID
+EFIAPI
+GmacIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    /* gmac0 iomux */
+    BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+    BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+    BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+    BUS_IOC->GPIO2C_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+    BUS_IOC->GPIO4C_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0100;
+    BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011;
+    break;
+  case 1:
+    /* gmac1 iomux */
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+NorFspiEnableClock (
+  UINT32 *CruBase
+  )
+{
+  UINTN BaseAddr = (UINTN) CruBase;
+
+  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+}
+
+VOID
+EFIAPI
+I2cIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    /* io mux M2 */
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
+    break;
+  case 1:
+    /* io mux */
+    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
+    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
+    break;
+  case 2:
+    /* io mux */
+    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
+    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
+    PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
+    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    break;
+  case 3:
+    break;
+  case 4:
+    break;
+  case 5:
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+UsbPortPowerEnable (
+  VOID
+  )
+{
+  DEBUG((EFI_D_WARN, "UsbPortPowerEnable called\n"));
+
+  /* Set VCC_5V0_PWREN_H */
+  GpioPinWrite (4, GPIO_PIN_PA2, TRUE);
+  GpioPinSetDirection (4, GPIO_PIN_PA2, GPIO_PIN_OUTPUT);
+
+  /* Set USB_HOST_PWREN_H */
+  GpioPinWrite (1, GPIO_PIN_PB1, TRUE);
+  GpioPinSetDirection (1, GPIO_PIN_PB1, GPIO_PIN_OUTPUT);
+
+  /* Set TYPEC0_PWR_EN */
+  GpioPinWrite (3, GPIO_PIN_PA4, TRUE);
+  GpioPinSetDirection (3, GPIO_PIN_PA4, GPIO_PIN_OUTPUT);
+}
+
+VOID
+EFIAPI
+Usb2PhyResume (
+  VOID
+  )
+{
+  MmioWrite32(0xfd5d0008, 0x20000000);
+  MmioWrite32(0xfd5d4008, 0x20000000);
+  MmioWrite32(0xfd5d8008, 0x20000000);
+  MmioWrite32(0xfd5dc008, 0x20000000);
+  MmioWrite32(0xfd7f0a10, 0x07000700);
+  MmioWrite32(0xfd7f0a10, 0x07000000);
+}
+
+VOID
+EFIAPI
+UsbDpPhyEnable (
+  VOID
+  )
+{
+  /* enable rx_lfps_en & usbdp_low_pwrn */
+  MmioWrite32(0xfd5c8004, 0x60006000);
+  MmioWrite32(0xfd5cc004, 0x60006000);
+  
+  /* remove rx-termination, we don't support SS yet */
+  MmioWrite32 (0xfd5c800c, 0x00030001);
+  MmioWrite32 (0xfd5cc00c, 0x00030001);
+}
+
+VOID
+EFIAPI
+Pcie30IoInit (
+  VOID
+  )
+{
+  /* not applicable */
+}
+
+VOID
+EFIAPI
+Pcie30PowerEn (
+  VOID
+  )
+{
+  /* not applicable */
+}
+
+VOID
+EFIAPI
+Pcie30PeReset (
+  BOOLEAN enable
+  )
+{
+  /* not applicable */
+}
+
+VOID
+EFIAPI
+PlatformEarlyInit (
+  VOID
+  )
+{
+  // Configure various things specific to this platform
+}
--- a/edk2-platforms/Platform/Khadas/Edge2/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+++ b/edk2-platforms/Platform/Khadas/Edge2/Library/RockchipPlatformLib/RockchipPlatformLib.inf
@@ -0,0 +1,43 @@
+#
+#  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = RockchipPlatformLib
+  FILE_GUID                      = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RockchipPlatformLib
+  RKPLATLIB_COMMON_DIR           = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Platform/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  SerialPortLib
+  CruLib
+  GpioLib
+
+[Sources.common]
+  RockchipPlatformLib.c
+  $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c
+  $(RKPLATLIB_COMMON_DIR)/RockchipSdhci.c
+
+[Sources.AARCH64]
+
+[Pcd]
+  gRockchipTokenSpaceGuid.PcdSdhciDxeBaseAddress
+  gRockchipTokenSpaceGuid.PcdI2cBusCount
+
--- a/edk2-platforms/Platform/Mekotronics/Drivers/LogoDxe/Logo.bmp
+++ b/edk2-platforms/Platform/Mekotronics/Drivers/LogoDxe/Logo.bmp
--- a/edk2-platforms/Platform/Mekotronics/Drivers/LogoDxe/Logo.c
+++ b/edk2-platforms/Platform/Mekotronics/Drivers/LogoDxe/Logo.c
@@ -0,0 +1,144 @@
+/** @file
+  Logo DXE Driver, install Edkii Platform Logo protocol.
+
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+  Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Protocol/HiiDatabase.h>
+#include <Protocol/GraphicsOutput.h>
+#include <Protocol/HiiImageEx.h>
+#include <Protocol/PlatformLogo.h>
+#include <Protocol/HiiPackageList.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+
+typedef struct {
+  EFI_IMAGE_ID                          ImageId;
+  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
+  INTN                                  OffsetX;
+  INTN                                  OffsetY;
+} LOGO_ENTRY;
+
+STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
+STATIC EFI_HII_HANDLE            mHiiHandle;
+STATIC LOGO_ENTRY                mLogos[] = {
+  {
+    IMAGE_TOKEN (IMG_LOGO),
+    EdkiiPlatformLogoDisplayAttributeCenter,
+    0,
+    0
+  }
+};
+
+/**
+  Load a platform logo image and return its data and attributes.
+
+  @param This              The pointer to this protocol instance.
+  @param Instance          The visible image instance is found.
+  @param Image             Points to the image.
+  @param Attribute         The display attributes of the image returned.
+  @param OffsetX           The X offset of the image regarding the Attribute.
+  @param OffsetY           The Y offset of the image regarding the Attribute.
+
+  @retval EFI_SUCCESS      The image was fetched successfully.
+  @retval EFI_NOT_FOUND    The specified image could not be found.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GetImage (
+  IN     EDKII_PLATFORM_LOGO_PROTOCOL          *This,
+  IN OUT UINT32                                *Instance,
+     OUT EFI_IMAGE_INPUT                       *Image,
+     OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
+     OUT INTN                                  *OffsetX,
+     OUT INTN                                  *OffsetY
+  )
+{
+  UINT32 Current;
+
+  if (Instance == NULL || Image == NULL ||
+      Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Current = *Instance;
+  if (Current >= ARRAY_SIZE (mLogos)) {
+    return EFI_NOT_FOUND;
+  }
+
+  (*Instance)++;
+  *Attribute = mLogos[Current].Attribute;
+  *OffsetX   = mLogos[Current].OffsetX;
+  *OffsetY   = mLogos[Current].OffsetY;
+
+  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
+                        mLogos[Current].ImageId, Image);
+}
+
+STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+  GetImage
+};
+
+/**
+  Entrypoint of this module.
+
+  This function is the entrypoint of this module. It installs the Edkii
+  Platform Logo protocol.
+
+  @param  ImageHandle       The firmware allocated handle for the EFI image.
+  @param  SystemTable       A pointer to the EFI System Table.
+
+  @retval EFI_SUCCESS       The entry point is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeLogo (
+  IN EFI_HANDLE               ImageHandle,
+  IN EFI_SYSTEM_TABLE         *SystemTable
+  )
+{
+  EFI_STATUS                  Status;
+  EFI_HII_PACKAGE_LIST_HEADER *PackageList;
+  EFI_HII_DATABASE_PROTOCOL   *HiiDatabase;
+  EFI_HANDLE                  Handle;
+
+  Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
+                  (VOID **) &HiiDatabase);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
+                  (VOID **) &mHiiImageEx);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Retrieve HII package list from ImageHandle
+  //
+  Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
+                  (VOID **) &PackageList, ImageHandle, NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR,
+      "HII Image Package with logo not found in PE/COFF resource section\n"));
+    return Status;
+  }
+
+  //
+  // Publish HII package list to HII Database.
+  //
+  Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
+                          &mHiiHandle);
+  if (!EFI_ERROR (Status)) {
+    Handle = NULL;
+    Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
+                    &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
+  }
+  return Status;
+}
--- a/edk2-platforms/Platform/Mekotronics/Drivers/LogoDxe/Logo.idf
+++ b/edk2-platforms/Platform/Mekotronics/Drivers/LogoDxe/Logo.idf
@@ -0,0 +1,10 @@
+// @file
+// Platform Logo image definition file.
+//
+// Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+// Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+
+#image IMG_LOGO Logo.bmp
--- a/edk2-platforms/Platform/Mekotronics/Drivers/LogoDxe/LogoDxe.inf
+++ b/edk2-platforms/Platform/Mekotronics/Drivers/LogoDxe/LogoDxe.inf
@@ -0,0 +1,48 @@
+## @file
+#  The default logo bitmap picture shown on setup screen.
+#
+#  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+#  Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = LogoDxe
+  FILE_GUID                      = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = InitializeLogo
+#
+#  This flag specifies whether HII resource section is generated into PE image.
+#
+  UEFI_HII_RESOURCE_SECTION      = TRUE
+
+[Sources]
+  Logo.bmp
+  Logo.c
+  Logo.idf
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  DebugLib
+
+[Protocols]
+  gEfiHiiDatabaseProtocolGuid        ## CONSUMES
+  gEfiHiiImageExProtocolGuid         ## CONSUMES
+  gEfiHiiPackageListProtocolGuid     ## PRODUCES CONSUMES
+  gEdkiiPlatformLogoProtocolGuid     ## PRODUCES
+
+[Depex]
+  gEfiHiiDatabaseProtocolGuid AND
+  gEfiHiiImageExProtocolGuid
--- a/edk2-platforms/Platform/Mekotronics/R58-Mini/AcpiTables/AcpiTables.inf
+++ b/edk2-platforms/Platform/Mekotronics/R58-Mini/AcpiTables/AcpiTables.inf
@@ -0,0 +1,64 @@
+#/** @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2019-2021, ARM Limited. All rights reserved.
+#  Copyright (c) Microsoft Corporation. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+  RK_COMMON_ACPI_DIR             = Silicon/Rockchip/RK3588/AcpiTables
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+
+[Sources]
+  Dsdt.asl
+  $(RK_COMMON_ACPI_DIR)/Madt.aslc
+  $(RK_COMMON_ACPI_DIR)/Fadt.aslc
+  $(RK_COMMON_ACPI_DIR)/Gtdt.aslc
+  $(RK_COMMON_ACPI_DIR)/Spcr.aslc
+  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
+  $(RK_COMMON_ACPI_DIR)/RK3588PcieIort.aslc
+  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Rockchip/RockchipPkg.dec
+  Platform/Rockchip/RK3588/RK3588.dec
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
--- a/edk2-platforms/Platform/Mekotronics/R58-Mini/AcpiTables/Dsdt.asl
+++ b/edk2-platforms/Platform/Mekotronics/R58-Mini/AcpiTables/Dsdt.asl
@@ -0,0 +1,40 @@
+/** @file
+ *
+ *  Differentiated System Definition Table (DSDT)
+ *
+ *  Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ *  Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
+ *  Copyright (c) Microsoft Corporation. All rights reserved.
+ *  Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include "AcpiTables.h"
+
+DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
+{
+  Scope (\_SB_)
+  {
+    include ("Cpu.asl")
+
+    // include ("Pcie.asl")
+    include ("Sata0.asl")
+    include ("Sata2.asl")
+    include ("Emmc.asl")
+    include ("Sdhc.asl")
+    // include ("Gmac.asl")
+    // include ("Gpio.asl")
+    // include ("I2c.asl")
+    include ("Uart.asl")
+    // include ("Spi.asl")
+
+    // won't work on Windows, will trigger bugcheck by usbehci
+    // include ("Usb2.asl")
+
+    include ("Usb3Host0.asl")
+    include ("Usb3Host1.asl")
+    include ("Usb3Host2.asl")
+  }
+}
--- a/edk2-platforms/Platform/Mekotronics/R58-Mini/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-platforms/Platform/Mekotronics/R58-Mini/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -0,0 +1,290 @@
+/** @file
+*
+*  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include <Base.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/GpioLib.h>
+#include <Library/RK806.h>
+#include <Soc.h>
+
+static struct regulator_init_data rk806_init_data[] = {
+  /* Master PMIC */
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
+  //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+
+  /* No dual PMICs on this platform */
+};
+
+VOID
+EFIAPI
+DwEmmcDxeIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux (microSD socket) */
+  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+}
+
+VOID
+EFIAPI
+SdhciEmmcDxeIoMux (
+  VOID
+  )
+{
+  /* sdhci0 iomux (eMMC socket) */
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+}
+
+#define NS_CRU_BASE         0xFD7C0000
+#define CRU_CLKSEL_CON59    0x03EC
+#define CRU_CLKSEL_CON78    0x0438
+
+VOID
+EFIAPI
+Rk806SpiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
+  PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+}
+
+VOID
+EFIAPI
+Rk806Configure (
+  VOID
+  )
+{
+  UINTN RegCfgIndex;
+
+  RK806Init();
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
+    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+}
+
+VOID
+EFIAPI
+SetCPULittleVoltage (
+  IN UINT32 Microvolts
+  )
+{
+  struct regulator_init_data Rk806CpuLittleSupply =
+        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+
+  RK806RegulatorInit(Rk806CpuLittleSupply);
+}
+
+VOID
+EFIAPI
+NorFspiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
+             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
+#define FSPI_M1
+#if defined(FSPI_M0)
+   /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
+#elif defined(FSPI_M1)
+  /*FSPI M1*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
+#else
+  /*FSPI M2*/
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
+#endif
+}
+
+VOID
+EFIAPI
+GmacIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    /* gmac0 iomux */
+    BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+    BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+    BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+    BUS_IOC->GPIO2C_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+    BUS_IOC->GPIO4C_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0100;
+    BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011;
+    break;
+  case 1:
+    /* gmac1 iomux */
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+NorFspiEnableClock (
+  UINT32 *CruBase
+  )
+{
+  UINTN BaseAddr = (UINTN) CruBase;
+
+  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+}
+
+VOID
+EFIAPI
+I2cIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    /* io mux M2 */
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
+    break;
+  case 1:
+    /* io mux */
+    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
+    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
+    break;
+  case 2:
+    /* io mux */
+    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
+    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
+    PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
+    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    break;
+  case 3:
+    break;
+  case 4:
+    break;
+  case 5:
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+UsbPortPowerEnable (
+  VOID
+  )
+{
+  DEBUG((EFI_D_WARN, "UsbPortPowerEnable called\n"));
+
+  /* Enable USB-C VBUS */
+  GpioPinWrite (4, GPIO_PIN_PA7, TRUE);
+  GpioPinSetDirection (4, GPIO_PIN_PA7, GPIO_PIN_OUTPUT);
+
+  /* Enable USB HOST VBUS */
+  GpioPinWrite (4, GPIO_PIN_PB0, TRUE);
+  GpioPinSetDirection (4, GPIO_PIN_PB0, GPIO_PIN_OUTPUT);
+}
+
+VOID
+EFIAPI
+Usb2PhyResume (
+  VOID
+  )
+{
+  MmioWrite32(0xfd5d0008, 0x20000000);
+  MmioWrite32(0xfd5d4008, 0x20000000);
+  MmioWrite32(0xfd5d8008, 0x20000000);
+  MmioWrite32(0xfd5dc008, 0x20000000);
+  MmioWrite32(0xfd7f0a10, 0x07000700);
+  MmioWrite32(0xfd7f0a10, 0x07000000);
+}
+
+VOID
+EFIAPI
+UsbDpPhyEnable (
+  VOID
+  )
+{
+  /* enable rx_lfps_en & usbdp_low_pwrn */
+  MmioWrite32(0xfd5c8004, 0x60006000);
+  MmioWrite32(0xfd5cc004, 0x60006000);
+  
+  /* remove rx-termination, we don't support SS yet */
+  MmioWrite32 (0xfd5c800c, 0x00030001);
+  MmioWrite32 (0xfd5cc00c, 0x00030001);
+}
+
+VOID
+EFIAPI
+Pcie30IoInit (
+  VOID
+  )
+{
+  /* not applicable */
+}
+
+VOID
+EFIAPI
+Pcie30PowerEn (
+  VOID
+  )
+{
+  /* not applicable */
+}
+
+VOID
+EFIAPI
+Pcie30PeReset (
+  BOOLEAN enable
+  )
+{
+  /* not applicable */
+}
+
+VOID
+EFIAPI
+PlatformEarlyInit (
+  VOID
+  )
+{
+  /* Enable power LED */
+  GpioPinWrite (3, GPIO_PIN_PB7, TRUE);
+  GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT);
+}
--- a/edk2-platforms/Platform/Mekotronics/R58-Mini/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+++ b/edk2-platforms/Platform/Mekotronics/R58-Mini/Library/RockchipPlatformLib/RockchipPlatformLib.inf
@@ -0,0 +1,43 @@
+#
+#  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = RockchipPlatformLib
+  FILE_GUID                      = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RockchipPlatformLib
+  RKPLATLIB_COMMON_DIR           = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Platform/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  SerialPortLib
+  CruLib
+  GpioLib
+
+[Sources.common]
+  RockchipPlatformLib.c
+  $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c
+  $(RKPLATLIB_COMMON_DIR)/RockchipSdhci.c
+
+[Sources.AARCH64]
+
+[Pcd]
+  gRockchipTokenSpaceGuid.PcdSdhciDxeBaseAddress
+  gRockchipTokenSpaceGuid.PcdI2cBusCount
+
--- a/edk2-platforms/Platform/Mekotronics/R58-Mini/R58-Mini.dsc
+++ b/edk2-platforms/Platform/Mekotronics/R58-Mini/R58-Mini.dsc
@@ -0,0 +1,637 @@
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2021-2022, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = R58-Mini
+  PLATFORM_GUID                  = d080df36-45e7-11ec-9726-f42a7dcb925d
+  PLATFORM_VERSION               = 0.2
+  DSC_SPECIFICATION              = 0x00010019
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = Platform/Mekotronics/R58-Mini/R58-Mini.fdf
+
+  DEFINE CONFIG_NO_DEBUGLIB      = TRUE
+
+  #
+  # Must match defines in Silicon/Rockchip/RK3588/Include/VarStoreData.h
+  #
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT  = 0
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_MIN          = 1
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_MAX          = 2
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_CUSTOM       = 3
+
+  DEFINE COMBO_PHY_MODE_UNCONNECTED   = 0
+  DEFINE COMBO_PHY_MODE_PCIE          = 1
+  DEFINE COMBO_PHY_MODE_SATA          = 2
+  DEFINE COMBO_PHY_MODE_USB3          = 3
+
+  #
+  # Network definition
+  #
+  DEFINE NETWORK_SNP_ENABLE             = FALSE
+  DEFINE NETWORK_IP6_ENABLE             = FALSE
+  DEFINE NETWORK_TLS_ENABLE             = FALSE
+  DEFINE NETWORK_HTTP_BOOT_ENABLE       = FALSE
+  DEFINE NETWORK_ISCSI_ENABLE           = FALSE
+  DEFINE NETWORK_VLAN_ENABLE            = FALSE
+!include Silicon/Rockchip/Rockchip.dsc.inc
+!include MdePkg/MdeLibs.dsc.inc
+
+!if $(ENABLE_SIMPLE_INIT)
+  !include SimpleInit.inc
+!endif
+
+[LibraryClasses.common]
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmPlatformLib|Silicon/Rockchip/RK3588/Library/PlatformLib/PlatformLib.inf
+  AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf
+  CruLib|Silicon/Rockchip/Library/CruLib/CruLib.inf
+
+  DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
+
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+  # UiApp dependencies
+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+
+  #RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+  TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
+
+  # USB Requirements
+  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+
+  # PCIe
+  PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+  PciHostBridgeLib|Silicon/Rockchip/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+  PciExpressLib|Silicon/Rockchip/Library/PciExpressLib/PciExpressLib.inf
+  PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+
+
+  # VariableRuntimeDxe Requirements
+  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+  AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+  TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+  VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+
+  AndroidBootImgLib|edk2/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.inf
+
+  RockchipDisplayLib|Silicon/Rockchip/Library/DisplayLib/RockchipDisplayLib.inf
+
+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+  LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf
+
+  # OTP Library
+  OtpLib|Silicon/Rockchip/RK3588/Library/OtpLib/OtpLib.inf
+
+  #
+  # Custom libraries
+  #
+  RockchipPlatformLib|Platform/Mekotronics/R58-Mini/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+  ResetSystemLib|Silicon/Rockchip/Library/ResetSystemLib/ResetSystemLib.inf
+  PlatformBootManagerLib|Silicon/Rockchip/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+  SerialPortLib|Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf
+  GpioLib|Silicon/Rockchip/RK3588/Library/GpioLib/GpioLib.inf
+  # SCMI Mailbox Transport Layer
+  ArmMtlLib|Silicon/Rockchip/Library/RkMtlLib/RkMtlLib.inf
+
+[LibraryClasses.common.SEC]
+  PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+  ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+  HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
+  MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+  MemoryInitPeiLib|Silicon/Rockchip/RK3588/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
+  PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+  PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+  RockchipPlatformLib|Platform/Mekotronics/R58-Mini/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+
+[BuildOptions]
+  GCC:*_*_*_PLATFORM_FLAGS = -I$(WORKSPACE)/Silicon/Rockchip/RK3588/Include -I$(WORKSPACE)/Platform/Rockchip/RK3588/Include -I$(WORKSPACE)/Silicon/Rockchip/Include
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+  #  If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+  #  It could be set FALSE to save size.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+
+[PcdsFixedAtBuild.common]
+  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)"
+
+  # System Memory (1GB)
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000
+  
+  # RK3588 CPU profile
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|8
+  gArmPlatformTokenSpaceGuid.PcdClusterCount|1
+
+  # SMBIOS platform config
+  gRockchipTokenSpaceGuid.PcdPlatformName|"R58 Mini"
+  gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Mekotronics"
+  gRockchipTokenSpaceGuid.PcdFamilyName|"R58"
+  gRockchipTokenSpaceGuid.PcdProductUrl|"https://www.mekotronics.com/h-pd-76.html"
+  gRockchipTokenSpaceGuid.PcdBoardName|"MINI-PC-RK3588-4D32-V1.0"
+  gRockchipTokenSpaceGuid.PcdMemoryVendorName|"TBD"
+
+  # I2C
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 }
+  gRockchipTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0 }
+  gRockchipTokenSpaceGuid.PcdI2cClockFrequency|198000000
+  gRockchipTokenSpaceGuid.PcdI2cBaudRate|100000
+  gRockchipTokenSpaceGuid.PcdI2cBusCount|1
+  gRockchipTokenSpaceGuid.PcdI2cDemoAddresses|{ 0x51 } #/* RTCYM8563TS 0x51@bus2 */
+  gRockchipTokenSpaceGuid.PcdI2cDemoBuses|{ 0x2 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ 2, 3 } # SCMI_CLK_CPUB01, SCMI_CLK_CPUB23
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorMinVoltages|{ UINT32(550000), UINT32(550000) }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorMaxVoltages|{ UINT32(1050000), UINT32(1050000) }
+
+  ## UART2 - Serial Terminal
+  DEFINE SERIAL_BASE = 0xFEB50000 # UART2
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|$(SERIAL_BASE)
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|1500000
+  gHisiTokenSpaceGuid.PcdSerialPortSendDelay|500000
+  gHisiTokenSpaceGuid.PcdUartClkInHz|24000000
+
+  ## SPI - SPI2 for test
+  gRockchipTokenSpaceGuid.SpiTestBaseAddr|0xFEB20000
+  gRockchipTokenSpaceGuid.SpiRK806BaseAddr|0xFEB20000
+  ## PL031 RealTimeClock
+  #gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0xF8003000
+
+  ## NOR FLASH
+  gRockchipTokenSpaceGuid.FspiBaseAddr|0xFE2B0000
+
+  ## CRU
+  gRockchipTokenSpaceGuid.CruBaseAddr|0xFD7C0000
+
+  #gRockchipTokenSpaceGuid.PcdSpiVariableOffset|0x3C0000
+  #
+  # ARM General Interrupt Controller
+  #
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0xfe600000
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xfe600000
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0xfe680000
+
+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3
+
+  # GUID of the UI app
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+
+  gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
+
+  #
+  # DW SD card controller
+  #
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeBaseAddress|0xfe2c0000
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz|100000000
+  gDesignWareTokenSpaceGuid.PcdDwPermitObsoleteDrivers|TRUE
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeFifoDepth|256
+  #
+  # SDHCI controller
+  #
+  gRockchipTokenSpaceGuid.PcdSdhciDxeBaseAddress|0xfe2e0000
+
+  #
+  # PCIe controller
+  #
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress|0xfe150000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress|0xf5000000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress|0xf0000000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize|0x100000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress|0xf0100000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize|0x10000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress|0xf0200000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize|0xe00000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64|0x901000000 #deduct 0x1000000 ECAM space
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64|0x3f000000
+
+  #
+  # Fastboot
+  #
+  gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbVendorId|0x2207
+  gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbProductId|0x0001
+
+  #
+  # USB2 EHCI + OHCI companion controllers
+  #
+  gRockchipTokenSpaceGuid.PcdEhciBaseAddress|0xfc800000
+  gRockchipTokenSpaceGuid.PcdNumEhciController|2
+  gRockchipTokenSpaceGuid.PcdEhciSize|0x40000
+  gRockchipTokenSpaceGuid.PcdOhciSize|0x40000
+
+  #
+  # DWC3 controller
+  #
+  gRockchipTokenSpaceGuid.PcdDwc3BaseAddresses|{ UINT32(0xfc000000), UINT32(0xfc400000), UINT32(0xfcd00000) }
+  gRockchipTokenSpaceGuid.PcdDwc3Size|0x400000
+
+  #
+  # Android Loader
+  #
+  gRK3588TokenSpaceGuid.PcdAndroidBootDevicePath|L"\\EFI\\BOOT\\GRUBAA64.EFI"
+  gRK3588TokenSpaceGuid.PcdSdBootDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00E023F70000000000)/SD(0x0)"
+  gRK3588TokenSpaceGuid.PcdKernelBootArg|L"earlycon=uart8250,mmio32,0xfeb50000 root=PARTUUID=614e0000-0000 rw rootwait"
+  gEmbeddedTokenSpaceGuid.PcdAndroidBootDevicePath|L"VenHw(100C2CFA-B586-4198-9B4C-1683D195B1DA)/HD(3,GPT,7A3F0000-0000-446A-8000-702F00006273,0x8000,0x20000)"
+
+  # ACPI Enable
+  gRK3588TokenSpaceGuid.AcpiEnable|TRUE
+
+  #
+  # Display
+  #
+  gRockchipTokenSpaceGuid.PcdLcdPixelFormat|0x00000001
+  gRockchipTokenSpaceGuid.PcdEdpId|0x00000000 #edp0
+  #gRockchipTokenSpaceGuid.PcdEdpId|0x00000001 #edp1
+  gRockchipTokenSpaceGuid.PcdHdmiId|0x00000000 #hdmi0
+  #gRockchipTokenSpaceGuid.PcdHdmiId|0x00000001 #hdmi1
+
+  #
+  # CPU Performance default values
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|FALSE
+  gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_SATA)
+  gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_UNCONNECTED)
+  gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3)
+
+  #  BIT0  - Initialization message.<BR>
+  #  BIT1  - Warning message.<BR>
+  #  BIT2  - Load Event message.<BR>
+  #  BIT3  - File System message.<BR>
+  #  BIT4  - Allocate or Free Pool message.<BR>
+  #  BIT5  - Allocate or Free Page message.<BR>
+  #  BIT6  - Information message.<BR>
+  #  BIT7  - Dispatcher message.<BR>
+  #  BIT8  - Variable message.<BR>
+  #  BIT10 - Boot Manager message.<BR>
+  #  BIT12 - BlockIo Driver message.<BR>
+  #  BIT14 - Network Driver message.<BR>
+  #  BIT16 - UNDI Driver message.<BR>
+  #  BIT17 - LoadFile message.<BR>
+  #  BIT19 - Event message.<BR>
+  #  BIT20 - Global Coherency Database changes message.<BR>
+  #  BIT21 - Memory range cachability changes message.<BR>
+  #  BIT22 - Detailed debug message.<BR>
+  #  BIT31 - Error message.<BR>
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0e
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000000
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0f
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x800B0507
+!endif
+# 0x800B05C7
+# Use 0x807B55FF to enable all debug messages
+
+[PcdsDynamicDefault.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x007C0000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x007CF000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x007D0000
+
+  #
+  # Display
+  #
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x780
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x438
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0
+
+[PcdsDynamicHii.common.DEFAULT]
+  #
+  # CPU Performance
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPreset|L"CpuPerf_CPULClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockCustom|L"CpuPerf_CPULClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|1800
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPreset|L"CpuPerf_CPUB01ClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockCustom|L"CpuPerf_CPUB01ClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|2400
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPreset|L"CpuPerf_CPUB23ClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockCustom|L"CpuPerf_CPUB23ClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|2400
+  gRK3588TokenSpaceGuid.PcdCPULClusterVoltageMode|L"CpuPerf_CPULClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0
+  gRK3588TokenSpaceGuid.PcdCPULClusterVoltageCustom|L"CpuPerf_CPULClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|950000
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterVoltageMode|L"CpuPerf_CPUB01ClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterVoltageCustom|L"CpuPerf_CPUB01ClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|1000000
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterVoltageMode|L"CpuPerf_CPUB23ClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterVoltageCustom|L"CpuPerf_CPUB23ClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|1000000
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY
+  #
+  gRK3588TokenSpaceGuid.PcdComboPhy0Mode|L"ComboPhy0Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault
+  gRK3588TokenSpaceGuid.PcdComboPhy1Mode|L"ComboPhy1Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault
+  gRK3588TokenSpaceGuid.PcdComboPhy2Mode|L"ComboPhy2Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault
+  
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+  #
+  # PEI Phase modules
+  #
+  ArmPlatformPkg/PrePi/PeiUniCore.inf
+  MdeModulePkg/Core/Pei/PeiMain.inf
+  MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+
+  #
+  # DXE
+  #
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+  }
+
+  #
+  # Architectural Protocols
+  #
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+  #EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
+  <LibraryClasses>
+    RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
+  }
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  #PCIe
+  Silicon/Rockchip/Library/PciExpressLib/PciExpressLib.inf
+  Silicon/Rockchip/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+  Silicon/Rockchip/Drivers/PciPlatform/PcieInitDxe.inf
+  ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+  #MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.inf
+
+  MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+  
+  #
+  # Non-volatile FVB support
+  #
+  Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.inf
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+
+  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf
+  #Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
+  Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf
+  Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
+
+  Platform/Mekotronics/Drivers/LogoDxe/LogoDxe.inf
+
+  #
+  # SCMI Driver
+  #
+  ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf
+
+  #
+  # ACPI Support
+  #
+  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+  Platform/Mekotronics/R58-Mini/AcpiTables/AcpiTables.inf
+
+  #
+  # Device tree
+  #
+  EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf {
+  <LibraryClasses>
+    DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefault/DxeDtPlatformDtbLoaderLibDefault.inf
+  }
+
+  #
+  # GPIO
+  #
+  Platform/Rockchip/RK3588/RK3588GpioDxe/RK3588GpioDxe.inf
+
+  #
+  # Virtual Keyboard
+  #
+  EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
+
+  # I2C drivers
+  Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.inf
+  MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
+  Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.inf
+  Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.inf
+  Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.inf
+
+  #
+  # MMC/SD
+  #
+  #EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
+  #Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  Silicon/Rockchip/Drivers/MmcDxe/MmcDxe.inf
+  Silicon/Rockchip/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  Silicon/Rockchip/Drivers/SdhciHostDxe/SdhciHostDxe.inf
+
+  #
+  # NOR FLASH
+  #
+  Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.inf
+  Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+
+  #
+  # AHCI Support
+  #
+  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+  #
+  # SPI TEST
+  #
+  # Silicon/Rockchip/Library/SpiLib/SpiTest.inf
+
+  #
+  # SMBIOS Support
+  #
+  Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  
+  #
+  # USB Ohci Controller
+  #
+  Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf
+
+  #
+  # USB Ehci Controller
+  #
+  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+
+  #
+  # USB Dwc3 Controller
+  #
+  Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
+  #
+  # USB Xhci Controller
+  #
+  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+
+  #
+  # USB Host Support
+  #
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+  #
+  # USB Mass Storage Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # USB Kb Support
+  #
+  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+  #
+  # USB Mouse Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+
+  #
+  # USB MouseAbsolutePointer Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointerDxe.inf
+
+  #
+  # USB Peripheral Support
+  #
+  EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
+
+  #
+  # Fastboot
+  #
+  EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
+
+  #
+  # Android Boot applications
+  #
+  EmbeddedPkg/Application/AndroidBoot/AndroidBootApp.inf
+
+  #
+  # UEFI Network Stack
+  #
+!include NetworkPkg/Network.dsc.inc
+  #
+  # AX88772 Ethernet Driver
+  #
+  Drivers/ASIX/Bus/Usb/UsbNetworking/Ax88772c/Ax88772c.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+  MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf
+  FatPkg/EnhancedFatDxe/Fat.inf
+
+  #
+  # Bds
+  #
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  MdeModulePkg/Application/UiApp/UiApp.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  ShellPkg/Application/Shell/Shell.inf {
+    <LibraryClasses>
+      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+      NULL|Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.inf
+      NULL|Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf
+      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+      OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
+      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+      gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+  }
+!ifdef $(INCLUDE_TFTP_COMMAND)
+  ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+!endif #$(INCLUDE_TFTP_COMMAND)
+
+  #
+  # Custom Applications and drivers
+  #
+  Silicon/Rockchip/Applications/MaskromReset/maskrom.inf
+
+  # Platform drivers
+  Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf
+
--- a/edk2-platforms/Platform/Mekotronics/R58-Mini/R58-Mini.fdf
+++ b/edk2-platforms/Platform/Mekotronics/R58-Mini/R58-Mini.fdf
@@ -0,0 +1,384 @@
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2021-2022, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.NOR_FLASH_IMAGE]
+BaseAddress   = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
+Size          = 0x00800000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize     = 0x00001000
+NumBlocks     = 0x800
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+0x00200000|0x00500000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = BL33_AP_UEFI
+
+# NV_VARIABLE_STORE
+0x007C0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+
+# NV_FTW_WORKING header
+0x007D0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+# NV_FTW_WORKING data
+0x007E0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+BlockSize          = 0x40
+NumBlocks          = 0         # This FV gets compressed so make it just big enough
+FvAlignment        = 8         # FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  APRIORI DXE {
+    INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+  }
+
+  INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+  #
+  # PI DXE Drivers producing Architectural Protocols (EFI Services)
+  #
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  #
+  # Multiple Console IO support
+  #
+  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+
+  INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+
+  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  #
+  # ACPI Support
+  #
+  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+  INF RuleOverride = ACPITABLE Platform/Mekotronics/R58-Mini/AcpiTables/AcpiTables.inf
+
+  #
+  # Device tree
+  #
+  INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf
+  # FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 {
+  #   SECTION RAW = Platform/Rockchip/DeviceTree/rk3588.dtb
+  # }
+
+  #
+  # GPIO
+  #
+  INF Platform/Rockchip/RK3588/RK3588GpioDxe/RK3588GpioDxe.inf
+  #INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf
+
+  #
+  # I2C
+  #
+  INF Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.inf
+  INF MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
+  # INF Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.inf
+  INF Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.inf
+
+  #
+  # Virtual Keyboard
+  #
+  INF EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
+
+  #
+  # Display Support
+  #
+  
+  INF Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf
+  #INF Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
+  INF Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf
+  INF Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
+  INF Platform/Mekotronics/Drivers/LogoDxe/LogoDxe.inf
+
+  INF Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf
+
+  #
+  # SMBIOS Support
+  #
+  INF Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+  INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+
+  #
+  # USB Ehci Controller
+  #
+  INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+
+  #
+  # USB Ohci Controller
+  #
+  INF Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf
+
+  #
+  # USB Dwc3 Controller
+  #
+  INF Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
+  #
+  # USB Xhci Controller
+  #
+  INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+
+  #
+  # USB Host Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+  #
+  # USB Mass Storage Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # USB Kb Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+  #
+  # USB Mouse Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+
+  #
+  # USB MouseAbsolutePointer Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointerDxe.inf
+
+  #
+  # USB Peripheral Support
+  #
+  INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
+
+  #
+  # Fastboot
+  #
+  INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
+
+
+  #PCIe
+  #INF Silicon/Rockchip/Drivers/PciPlatform/PcieInitDxe.inf
+
+  # Required by PCI
+  #INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
+  # PCI Support
+  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+  #INF MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.inf
+
+  #INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+  INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+  #
+  # Android Boot applications
+  #
+  INF EmbeddedPkg/Application/AndroidBoot/AndroidBootApp.inf
+
+  #
+  # UEFI Network Stack
+  #
+!include NetworkPkg/Network.fdf.inc
+
+  #
+  # AX88772 Ethernet Driver for Apple Ethernet Adapter
+  #
+  INF Drivers/ASIX/Bus/Usb/UsbNetworking/Ax88772c/Ax88772c.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf
+  INF FatPkg/EnhancedFatDxe/Fat.inf
+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  #
+  # Multimedia Card Interface
+  #
+  # INF Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  INF Silicon/Rockchip/Drivers/MmcDxe/MmcDxe.inf
+  #INF Silicon/Rockchip/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  
+  #
+  # DWC SDHCI (for eMMC slot)
+  #
+  INF Silicon/Rockchip/Drivers/SdhciHostDxe/SdhciHostDxe.inf
+
+  #
+  # AHCI Support
+  #
+  INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+  #
+  # SPI NOR FLASH
+  #
+  INF Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.inf
+
+  #
+  # Non-volatile FVB support
+  #
+  INF Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.inf
+  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+
+  # Human interface
+  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  # Custom
+  INF Silicon/Rockchip/Applications/MaskromReset/maskrom.inf
+  
+  # SCMI Driver
+  INF ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf
+
+  #
+  # UEFI applications
+  #
+  INF ShellPkg/Application/Shell/Shell.inf
+!ifdef $(INCLUDE_TFTP_COMMAND)
+  INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+!endif #$(INCLUDE_TFTP_COMMAND)
+  #INF Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+
+  #
+  # Bds
+  #
+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+  #
+  # Simple Init GUI
+  #
+!if $(ENABLE_SIMPLE_INIT)
+  INF src/main/SimpleInitMain.inf
+!endif
+
+[FV.BL33_AP_UEFI]
+FvAlignment        = 8
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+
+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FVMAIN
+    }
+  }
+
+!include Silicon/Rockchip/Rockchip.fdf.inc
+
+!ifdef $(ROCKCHIP_ACPIEN)
+[Rule.Common.DXE_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX	 DXE_DEPEX		Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32	 PE32			$(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI		 STRING="$(MODULE_NAME)" Optional
+    RAW 	 ACPI  Optional 	      |.acpi
+    RAW 	 ASL   Optional 	      |.aml
+  }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW ACPI		   |.acpi
+    RAW ASL		   |.aml
+  }
+!endif
--- a/edk2-platforms/Platform/Mekotronics/R58X/AcpiTables/AcpiTables.inf
+++ b/edk2-platforms/Platform/Mekotronics/R58X/AcpiTables/AcpiTables.inf
@@ -0,0 +1,64 @@
+#/** @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2019-2021, ARM Limited. All rights reserved.
+#  Copyright (c) Microsoft Corporation. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+  RK_COMMON_ACPI_DIR             = Silicon/Rockchip/RK3588/AcpiTables
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+
+[Sources]
+  Dsdt.asl
+  $(RK_COMMON_ACPI_DIR)/Madt.aslc
+  $(RK_COMMON_ACPI_DIR)/Fadt.aslc
+  $(RK_COMMON_ACPI_DIR)/Gtdt.aslc
+  $(RK_COMMON_ACPI_DIR)/Spcr.aslc
+  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
+  $(RK_COMMON_ACPI_DIR)/RK3588PcieIort.aslc
+  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Rockchip/RockchipPkg.dec
+  Platform/Rockchip/RK3588/RK3588.dec
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
--- a/edk2-platforms/Platform/Mekotronics/R58X/AcpiTables/Dsdt.asl
+++ b/edk2-platforms/Platform/Mekotronics/R58X/AcpiTables/Dsdt.asl
@@ -0,0 +1,41 @@
+/** @file
+ *
+ *  Differentiated System Definition Table (DSDT)
+ *
+ *  Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ *  Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
+ *  Copyright (c) Microsoft Corporation. All rights reserved.
+ *  Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include "AcpiTables.h"
+
+DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
+{
+  Scope (\_SB_)
+  {
+    include ("Cpu.asl")
+
+    include ("Pcie.asl")
+    include ("Sata0.asl")
+    include ("Sata1.asl")
+    include ("Sata2.asl")
+    include ("Emmc.asl")
+    include ("Sdhc.asl")
+    // include ("Gmac.asl")
+    // include ("Gpio.asl")
+    // include ("I2c.asl")
+    include ("Uart.asl")
+    // include ("Spi.asl")
+
+    // won't work on Windows, will trigger bugcheck by usbehci
+    // include ("Usb2.asl")
+
+    include ("Usb3Host0.asl")
+    include ("Usb3Host1.asl")
+    include ("Usb3Host2.asl")
+  }
+}
--- a/edk2-platforms/Platform/Mekotronics/R58X/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-platforms/Platform/Mekotronics/R58X/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -0,0 +1,296 @@
+/** @file
+*
+*  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include <Base.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/GpioLib.h>
+#include <Library/RK806.h>
+#include <Soc.h>
+
+static struct regulator_init_data rk806_init_data[] = {
+  /* Master PMIC */
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
+  //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+
+  /* No dual PMICs on this platform */
+};
+
+VOID
+EFIAPI
+DwEmmcDxeIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux (microSD socket) */
+  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+}
+
+VOID
+EFIAPI
+SdhciEmmcDxeIoMux (
+  VOID
+  )
+{
+  /* sdhci0 iomux (eMMC socket) */
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+}
+
+#define NS_CRU_BASE         0xFD7C0000
+#define CRU_CLKSEL_CON59    0x03EC
+#define CRU_CLKSEL_CON78    0x0438
+
+VOID
+EFIAPI
+Rk806SpiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
+  PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+}
+
+VOID
+EFIAPI
+Rk806Configure (
+  VOID
+  )
+{
+  UINTN RegCfgIndex;
+
+  RK806Init();
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
+    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+}
+
+VOID
+EFIAPI
+SetCPULittleVoltage (
+  IN UINT32 Microvolts
+  )
+{
+  struct regulator_init_data Rk806CpuLittleSupply =
+        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+
+  RK806RegulatorInit(Rk806CpuLittleSupply);
+}
+
+VOID
+EFIAPI
+NorFspiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
+             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
+#define FSPI_M1
+#if defined(FSPI_M0)
+   /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
+#elif defined(FSPI_M1)
+  /*FSPI M1*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
+#else
+  /*FSPI M2*/
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
+#endif
+}
+
+VOID
+EFIAPI
+GmacIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    /* gmac0 iomux */
+    BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+    BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+    BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+    BUS_IOC->GPIO2C_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+    BUS_IOC->GPIO4C_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0100;
+    BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011;
+    break;
+  case 1:
+    /* gmac1 iomux */
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+NorFspiEnableClock (
+  UINT32 *CruBase
+  )
+{
+  UINTN BaseAddr = (UINTN) CruBase;
+
+  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+}
+
+VOID
+EFIAPI
+I2cIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    /* io mux M2 */
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
+    break;
+  case 1:
+    /* io mux */
+    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
+    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
+    break;
+  case 2:
+    /* io mux */
+    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
+    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
+    PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
+    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    break;
+  case 3:
+    break;
+  case 4:
+    break;
+  case 5:
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+UsbPortPowerEnable (
+  VOID
+  )
+{
+  DEBUG((EFI_D_WARN, "UsbPortPowerEnable called\n"));
+
+  /* Enable USB-C VBUS */
+  GpioPinWrite (4, GPIO_PIN_PA7, TRUE);
+  GpioPinSetDirection (4, GPIO_PIN_PA7, GPIO_PIN_OUTPUT);
+
+  /* Enable USB HOST VBUS */
+  GpioPinWrite (4, GPIO_PIN_PB0, TRUE);
+  GpioPinSetDirection (4, GPIO_PIN_PB0, GPIO_PIN_OUTPUT);
+}
+
+VOID
+EFIAPI
+Usb2PhyResume (
+  VOID
+  )
+{
+  MmioWrite32(0xfd5d0008, 0x20000000);
+  MmioWrite32(0xfd5d4008, 0x20000000);
+  MmioWrite32(0xfd5d8008, 0x20000000);
+  MmioWrite32(0xfd5dc008, 0x20000000);
+  MmioWrite32(0xfd7f0a10, 0x07000700);
+  MmioWrite32(0xfd7f0a10, 0x07000000);
+}
+
+VOID
+EFIAPI
+UsbDpPhyEnable (
+  VOID
+  )
+{
+  /* enable rx_lfps_en & usbdp_low_pwrn */
+  MmioWrite32(0xfd5c8004, 0x60006000);
+  MmioWrite32(0xfd5cc004, 0x60006000);
+  
+  /* remove rx-termination, we don't support SS yet */
+  MmioWrite32 (0xfd5c800c, 0x00030001);
+  MmioWrite32 (0xfd5cc00c, 0x00030001);
+}
+
+VOID
+EFIAPI
+Pcie30IoInit (
+  VOID
+  )
+{
+  /* Set reset and power IO to gpio output mode */
+  GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
+  GpioPinSetDirection (1, GPIO_PIN_PC4, GPIO_PIN_OUTPUT);
+}
+
+VOID
+EFIAPI
+Pcie30PowerEn (
+  VOID
+  )
+{
+  /* output high to enable power */
+  GpioPinWrite (1, GPIO_PIN_PC4, TRUE);
+}
+
+VOID
+EFIAPI
+Pcie30PeReset (
+  BOOLEAN enable
+  )
+{
+  if(enable)
+    GpioPinWrite (4, GPIO_PIN_PB6, FALSE); /* output low */
+  else
+    GpioPinWrite (4, GPIO_PIN_PB6, TRUE); /* output high */
+}
+
+VOID
+EFIAPI
+PlatformEarlyInit (
+  VOID
+  )
+{
+  /* Enable power LED */
+  GpioPinWrite (3, GPIO_PIN_PB7, TRUE);
+  GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT);
+}
--- a/edk2-platforms/Platform/Mekotronics/R58X/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+++ b/edk2-platforms/Platform/Mekotronics/R58X/Library/RockchipPlatformLib/RockchipPlatformLib.inf
@@ -0,0 +1,43 @@
+#
+#  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = RockchipPlatformLib
+  FILE_GUID                      = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RockchipPlatformLib
+  RKPLATLIB_COMMON_DIR           = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Platform/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  SerialPortLib
+  CruLib
+  GpioLib
+
+[Sources.common]
+  RockchipPlatformLib.c
+  $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c
+  $(RKPLATLIB_COMMON_DIR)/RockchipSdhci.c
+
+[Sources.AARCH64]
+
+[Pcd]
+  gRockchipTokenSpaceGuid.PcdSdhciDxeBaseAddress
+  gRockchipTokenSpaceGuid.PcdI2cBusCount
+
--- a/edk2-platforms/Platform/Mekotronics/R58X/R58X.dsc
+++ b/edk2-platforms/Platform/Mekotronics/R58X/R58X.dsc
@@ -0,0 +1,637 @@
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2021-2022, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = R58X
+  PLATFORM_GUID                  = d080df36-45e7-11ec-9726-f42a7dcb925d
+  PLATFORM_VERSION               = 0.2
+  DSC_SPECIFICATION              = 0x00010019
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = Platform/Mekotronics/R58X/R58X.fdf
+
+  DEFINE CONFIG_NO_DEBUGLIB      = TRUE
+
+  #
+  # Must match defines in Silicon/Rockchip/RK3588/Include/VarStoreData.h
+  #
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT  = 0
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_MIN          = 1
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_MAX          = 2
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_CUSTOM       = 3
+
+  DEFINE COMBO_PHY_MODE_UNCONNECTED   = 0
+  DEFINE COMBO_PHY_MODE_PCIE          = 1
+  DEFINE COMBO_PHY_MODE_SATA          = 2
+  DEFINE COMBO_PHY_MODE_USB3          = 3
+
+  #
+  # Network definition
+  #
+  DEFINE NETWORK_SNP_ENABLE             = FALSE
+  DEFINE NETWORK_IP6_ENABLE             = FALSE
+  DEFINE NETWORK_TLS_ENABLE             = FALSE
+  DEFINE NETWORK_HTTP_BOOT_ENABLE       = FALSE
+  DEFINE NETWORK_ISCSI_ENABLE           = FALSE
+  DEFINE NETWORK_VLAN_ENABLE            = FALSE
+!include Silicon/Rockchip/Rockchip.dsc.inc
+!include MdePkg/MdeLibs.dsc.inc
+
+!if $(ENABLE_SIMPLE_INIT)
+  !include SimpleInit.inc
+!endif
+
+[LibraryClasses.common]
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmPlatformLib|Silicon/Rockchip/RK3588/Library/PlatformLib/PlatformLib.inf
+  AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf
+  CruLib|Silicon/Rockchip/Library/CruLib/CruLib.inf
+
+  DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
+
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+  # UiApp dependencies
+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+
+  #RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+  TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
+
+  # USB Requirements
+  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+
+  # PCIe
+  PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+  PciHostBridgeLib|Silicon/Rockchip/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+  PciExpressLib|Silicon/Rockchip/Library/PciExpressLib/PciExpressLib.inf
+  PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+
+
+  # VariableRuntimeDxe Requirements
+  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+  AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+  TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+  VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+
+  AndroidBootImgLib|edk2/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.inf
+
+  RockchipDisplayLib|Silicon/Rockchip/Library/DisplayLib/RockchipDisplayLib.inf
+
+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+  LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf
+
+  # OTP Library
+  OtpLib|Silicon/Rockchip/RK3588/Library/OtpLib/OtpLib.inf
+
+  #
+  # Custom libraries
+  #
+  RockchipPlatformLib|Platform/Mekotronics/R58X/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+  ResetSystemLib|Silicon/Rockchip/Library/ResetSystemLib/ResetSystemLib.inf
+  PlatformBootManagerLib|Silicon/Rockchip/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+  SerialPortLib|Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf
+  GpioLib|Silicon/Rockchip/RK3588/Library/GpioLib/GpioLib.inf
+  # SCMI Mailbox Transport Layer
+  ArmMtlLib|Silicon/Rockchip/Library/RkMtlLib/RkMtlLib.inf
+
+[LibraryClasses.common.SEC]
+  PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+  ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+  HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
+  MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+  MemoryInitPeiLib|Silicon/Rockchip/RK3588/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
+  PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+  PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+  RockchipPlatformLib|Platform/Mekotronics/R58X/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+
+[BuildOptions]
+  GCC:*_*_*_PLATFORM_FLAGS = -I$(WORKSPACE)/Silicon/Rockchip/RK3588/Include -I$(WORKSPACE)/Platform/Rockchip/RK3588/Include -I$(WORKSPACE)/Silicon/Rockchip/Include
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+  #  If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+  #  It could be set FALSE to save size.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+
+[PcdsFixedAtBuild.common]
+  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)"
+
+  # System Memory (1GB)
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000
+  
+  # RK3588 CPU profile
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|8
+  gArmPlatformTokenSpaceGuid.PcdClusterCount|1
+
+  # SMBIOS platform config
+  gRockchipTokenSpaceGuid.PcdPlatformName|"R58X"
+  gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Mekotronics"
+  gRockchipTokenSpaceGuid.PcdFamilyName|"R58"
+  gRockchipTokenSpaceGuid.PcdProductUrl|"https://www.mekotronics.com/h-pd-75.html"
+  gRockchipTokenSpaceGuid.PcdBoardName|"EDGE-RK3588-4D32-V1.2"
+  gRockchipTokenSpaceGuid.PcdMemoryVendorName|"TBD"
+
+  # I2C
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 }
+  gRockchipTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0 }
+  gRockchipTokenSpaceGuid.PcdI2cClockFrequency|198000000
+  gRockchipTokenSpaceGuid.PcdI2cBaudRate|100000
+  gRockchipTokenSpaceGuid.PcdI2cBusCount|1
+  gRockchipTokenSpaceGuid.PcdI2cDemoAddresses|{ 0x51 } #/* RTCYM8563TS 0x51@bus2 */
+  gRockchipTokenSpaceGuid.PcdI2cDemoBuses|{ 0x2 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ 2, 3 } # SCMI_CLK_CPUB01, SCMI_CLK_CPUB23
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorMinVoltages|{ UINT32(550000), UINT32(550000) }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorMaxVoltages|{ UINT32(1050000), UINT32(1050000) }
+
+  ## UART2 - Serial Terminal
+  DEFINE SERIAL_BASE = 0xFEB50000 # UART2
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|$(SERIAL_BASE)
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|1500000
+  gHisiTokenSpaceGuid.PcdSerialPortSendDelay|500000
+  gHisiTokenSpaceGuid.PcdUartClkInHz|24000000
+
+  ## SPI - SPI2 for test
+  gRockchipTokenSpaceGuid.SpiTestBaseAddr|0xFEB20000
+  gRockchipTokenSpaceGuid.SpiRK806BaseAddr|0xFEB20000
+  ## PL031 RealTimeClock
+  #gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0xF8003000
+
+  ## NOR FLASH
+  gRockchipTokenSpaceGuid.FspiBaseAddr|0xFE2B0000
+
+  ## CRU
+  gRockchipTokenSpaceGuid.CruBaseAddr|0xFD7C0000
+
+  #gRockchipTokenSpaceGuid.PcdSpiVariableOffset|0x3C0000
+  #
+  # ARM General Interrupt Controller
+  #
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0xfe600000
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xfe600000
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0xfe680000
+
+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3
+
+  # GUID of the UI app
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+
+  gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
+
+  #
+  # DW SD card controller
+  #
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeBaseAddress|0xfe2c0000
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz|100000000
+  gDesignWareTokenSpaceGuid.PcdDwPermitObsoleteDrivers|TRUE
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeFifoDepth|256
+  #
+  # SDHCI controller
+  #
+  gRockchipTokenSpaceGuid.PcdSdhciDxeBaseAddress|0xfe2e0000
+
+  #
+  # PCIe controller
+  #
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress|0xfe150000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress|0xf5000000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress|0xf0000000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize|0x100000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress|0xf0100000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize|0x10000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress|0xf0200000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize|0xe00000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64|0x901000000 #deduct 0x1000000 ECAM space
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64|0x3f000000
+
+  #
+  # Fastboot
+  #
+  gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbVendorId|0x2207
+  gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbProductId|0x0001
+
+  #
+  # USB2 EHCI + OHCI companion controllers
+  #
+  gRockchipTokenSpaceGuid.PcdEhciBaseAddress|0xfc800000
+  gRockchipTokenSpaceGuid.PcdNumEhciController|2
+  gRockchipTokenSpaceGuid.PcdEhciSize|0x40000
+  gRockchipTokenSpaceGuid.PcdOhciSize|0x40000
+
+  #
+  # DWC3 controller
+  #
+  gRockchipTokenSpaceGuid.PcdDwc3BaseAddresses|{ UINT32(0xfc000000), UINT32(0xfc400000), UINT32(0xfcd00000) }
+  gRockchipTokenSpaceGuid.PcdDwc3Size|0x400000
+
+  #
+  # Android Loader
+  #
+  gRK3588TokenSpaceGuid.PcdAndroidBootDevicePath|L"\\EFI\\BOOT\\GRUBAA64.EFI"
+  gRK3588TokenSpaceGuid.PcdSdBootDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00E023F70000000000)/SD(0x0)"
+  gRK3588TokenSpaceGuid.PcdKernelBootArg|L"earlycon=uart8250,mmio32,0xfeb50000 root=PARTUUID=614e0000-0000 rw rootwait"
+  gEmbeddedTokenSpaceGuid.PcdAndroidBootDevicePath|L"VenHw(100C2CFA-B586-4198-9B4C-1683D195B1DA)/HD(3,GPT,7A3F0000-0000-446A-8000-702F00006273,0x8000,0x20000)"
+
+  # ACPI Enable
+  gRK3588TokenSpaceGuid.AcpiEnable|TRUE
+
+  #
+  # Display
+  #
+  gRockchipTokenSpaceGuid.PcdLcdPixelFormat|0x00000001
+  gRockchipTokenSpaceGuid.PcdEdpId|0x00000000 #edp0
+  #gRockchipTokenSpaceGuid.PcdEdpId|0x00000001 #edp1
+  gRockchipTokenSpaceGuid.PcdHdmiId|0x00000000 #hdmi0
+  #gRockchipTokenSpaceGuid.PcdHdmiId|0x00000001 #hdmi1
+
+  #
+  # CPU Performance default values
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_SATA)
+  gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_PCIE)
+  gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3)
+
+  #  BIT0  - Initialization message.<BR>
+  #  BIT1  - Warning message.<BR>
+  #  BIT2  - Load Event message.<BR>
+  #  BIT3  - File System message.<BR>
+  #  BIT4  - Allocate or Free Pool message.<BR>
+  #  BIT5  - Allocate or Free Page message.<BR>
+  #  BIT6  - Information message.<BR>
+  #  BIT7  - Dispatcher message.<BR>
+  #  BIT8  - Variable message.<BR>
+  #  BIT10 - Boot Manager message.<BR>
+  #  BIT12 - BlockIo Driver message.<BR>
+  #  BIT14 - Network Driver message.<BR>
+  #  BIT16 - UNDI Driver message.<BR>
+  #  BIT17 - LoadFile message.<BR>
+  #  BIT19 - Event message.<BR>
+  #  BIT20 - Global Coherency Database changes message.<BR>
+  #  BIT21 - Memory range cachability changes message.<BR>
+  #  BIT22 - Detailed debug message.<BR>
+  #  BIT31 - Error message.<BR>
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0e
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000000
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0f
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x800B0507
+!endif
+# 0x800B05C7
+# Use 0x807B55FF to enable all debug messages
+
+[PcdsDynamicDefault.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x007C0000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x007CF000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x007D0000
+
+  #
+  # Display
+  #
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x780
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x438
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0
+
+[PcdsDynamicHii.common.DEFAULT]
+  #
+  # CPU Performance
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPreset|L"CpuPerf_CPULClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockCustom|L"CpuPerf_CPULClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|1800
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPreset|L"CpuPerf_CPUB01ClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockCustom|L"CpuPerf_CPUB01ClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|2400
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPreset|L"CpuPerf_CPUB23ClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockCustom|L"CpuPerf_CPUB23ClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|2400
+  gRK3588TokenSpaceGuid.PcdCPULClusterVoltageMode|L"CpuPerf_CPULClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0
+  gRK3588TokenSpaceGuid.PcdCPULClusterVoltageCustom|L"CpuPerf_CPULClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|950000
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterVoltageMode|L"CpuPerf_CPUB01ClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterVoltageCustom|L"CpuPerf_CPUB01ClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|1000000
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterVoltageMode|L"CpuPerf_CPUB23ClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterVoltageCustom|L"CpuPerf_CPUB23ClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|1000000
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY
+  #
+  gRK3588TokenSpaceGuid.PcdComboPhy0Mode|L"ComboPhy0Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault
+  gRK3588TokenSpaceGuid.PcdComboPhy1Mode|L"ComboPhy1Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault
+  gRK3588TokenSpaceGuid.PcdComboPhy2Mode|L"ComboPhy2Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault
+  
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+  #
+  # PEI Phase modules
+  #
+  ArmPlatformPkg/PrePi/PeiUniCore.inf
+  MdeModulePkg/Core/Pei/PeiMain.inf
+  MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+
+  #
+  # DXE
+  #
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+  }
+
+  #
+  # Architectural Protocols
+  #
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+  #EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
+  <LibraryClasses>
+    RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
+  }
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  #PCIe
+  Silicon/Rockchip/Library/PciExpressLib/PciExpressLib.inf
+  Silicon/Rockchip/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+  Silicon/Rockchip/Drivers/PciPlatform/PcieInitDxe.inf
+  ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+  #MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.inf
+
+  MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+  
+  #
+  # Non-volatile FVB support
+  #
+  Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.inf
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+
+  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf
+  #Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
+  Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf
+  Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
+
+  Platform/Mekotronics/Drivers/LogoDxe/LogoDxe.inf
+
+  #
+  # SCMI Driver
+  #
+  ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf
+
+  #
+  # ACPI Support
+  #
+  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+  Platform/Mekotronics/R58X/AcpiTables/AcpiTables.inf
+
+  #
+  # Device tree
+  #
+  EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf {
+  <LibraryClasses>
+    DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefault/DxeDtPlatformDtbLoaderLibDefault.inf
+  }
+
+  #
+  # GPIO
+  #
+  Platform/Rockchip/RK3588/RK3588GpioDxe/RK3588GpioDxe.inf
+
+  #
+  # Virtual Keyboard
+  #
+  EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
+
+  # I2C drivers
+  Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.inf
+  MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
+  Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.inf
+  Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.inf
+  Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.inf
+
+  #
+  # MMC/SD
+  #
+  #EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
+  #Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  Silicon/Rockchip/Drivers/MmcDxe/MmcDxe.inf
+  Silicon/Rockchip/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  Silicon/Rockchip/Drivers/SdhciHostDxe/SdhciHostDxe.inf
+
+  #
+  # NOR FLASH
+  #
+  Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.inf
+  Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+
+  #
+  # AHCI Support
+  #
+  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+  #
+  # SPI TEST
+  #
+  # Silicon/Rockchip/Library/SpiLib/SpiTest.inf
+
+  #
+  # SMBIOS Support
+  #
+  Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  
+  #
+  # USB Ohci Controller
+  #
+  Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf
+
+  #
+  # USB Ehci Controller
+  #
+  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+
+  #
+  # USB Dwc3 Controller
+  #
+  Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
+  #
+  # USB Xhci Controller
+  #
+  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+
+  #
+  # USB Host Support
+  #
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+  #
+  # USB Mass Storage Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # USB Kb Support
+  #
+  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+  #
+  # USB Mouse Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+
+  #
+  # USB MouseAbsolutePointer Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointerDxe.inf
+
+  #
+  # USB Peripheral Support
+  #
+  EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
+
+  #
+  # Fastboot
+  #
+  EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
+
+  #
+  # Android Boot applications
+  #
+  EmbeddedPkg/Application/AndroidBoot/AndroidBootApp.inf
+
+  #
+  # UEFI Network Stack
+  #
+!include NetworkPkg/Network.dsc.inc
+  #
+  # AX88772 Ethernet Driver
+  #
+  Drivers/ASIX/Bus/Usb/UsbNetworking/Ax88772c/Ax88772c.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+  MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf
+  FatPkg/EnhancedFatDxe/Fat.inf
+
+  #
+  # Bds
+  #
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  MdeModulePkg/Application/UiApp/UiApp.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  ShellPkg/Application/Shell/Shell.inf {
+    <LibraryClasses>
+      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+      NULL|Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.inf
+      NULL|Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf
+      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+      OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
+      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+      gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+  }
+!ifdef $(INCLUDE_TFTP_COMMAND)
+  ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+!endif #$(INCLUDE_TFTP_COMMAND)
+
+  #
+  # Custom Applications and drivers
+  #
+  Silicon/Rockchip/Applications/MaskromReset/maskrom.inf
+
+  # Platform drivers
+  Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf
+
--- a/edk2-platforms/Platform/Mekotronics/R58X/R58X.fdf
+++ b/edk2-platforms/Platform/Mekotronics/R58X/R58X.fdf
@@ -0,0 +1,384 @@
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2021-2022, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.NOR_FLASH_IMAGE]
+BaseAddress   = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
+Size          = 0x00800000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize     = 0x00001000
+NumBlocks     = 0x800
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+0x00200000|0x00500000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = BL33_AP_UEFI
+
+# NV_VARIABLE_STORE
+0x007C0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+
+# NV_FTW_WORKING header
+0x007D0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+# NV_FTW_WORKING data
+0x007E0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+BlockSize          = 0x40
+NumBlocks          = 0         # This FV gets compressed so make it just big enough
+FvAlignment        = 8         # FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  APRIORI DXE {
+    INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+  }
+
+  INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+  #
+  # PI DXE Drivers producing Architectural Protocols (EFI Services)
+  #
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  #
+  # Multiple Console IO support
+  #
+  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+
+  INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+
+  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  #
+  # ACPI Support
+  #
+  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+  INF RuleOverride = ACPITABLE Platform/Mekotronics/R58X/AcpiTables/AcpiTables.inf
+
+  #
+  # Device tree
+  #
+  INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf
+  # FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 {
+  #   SECTION RAW = Platform/Rockchip/DeviceTree/rk3588.dtb
+  # }
+
+  #
+  # GPIO
+  #
+  INF Platform/Rockchip/RK3588/RK3588GpioDxe/RK3588GpioDxe.inf
+  #INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf
+
+  #
+  # I2C
+  #
+  INF Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.inf
+  INF MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
+  # INF Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.inf
+  INF Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.inf
+
+  #
+  # Virtual Keyboard
+  #
+  INF EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
+
+  #
+  # Display Support
+  #
+  
+  INF Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf
+  #INF Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
+  INF Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf
+  INF Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
+  INF Platform/Mekotronics/Drivers/LogoDxe/LogoDxe.inf
+
+  INF Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf
+
+  #
+  # SMBIOS Support
+  #
+  INF Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+  INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+
+  #
+  # USB Ehci Controller
+  #
+  INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+
+  #
+  # USB Ohci Controller
+  #
+  INF Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf
+
+  #
+  # USB Dwc3 Controller
+  #
+  INF Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
+  #
+  # USB Xhci Controller
+  #
+  INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+
+  #
+  # USB Host Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+  #
+  # USB Mass Storage Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # USB Kb Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+  #
+  # USB Mouse Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+
+  #
+  # USB MouseAbsolutePointer Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointerDxe.inf
+
+  #
+  # USB Peripheral Support
+  #
+  INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
+
+  #
+  # Fastboot
+  #
+  INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
+
+
+  #PCIe
+  INF Silicon/Rockchip/Drivers/PciPlatform/PcieInitDxe.inf
+
+  # Required by PCI
+  INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
+  # PCI Support
+  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+  #INF MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.inf
+
+  #INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+  INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+  #
+  # Android Boot applications
+  #
+  INF EmbeddedPkg/Application/AndroidBoot/AndroidBootApp.inf
+
+  #
+  # UEFI Network Stack
+  #
+!include NetworkPkg/Network.fdf.inc
+
+  #
+  # AX88772 Ethernet Driver for Apple Ethernet Adapter
+  #
+  INF Drivers/ASIX/Bus/Usb/UsbNetworking/Ax88772c/Ax88772c.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf
+  INF FatPkg/EnhancedFatDxe/Fat.inf
+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  #
+  # Multimedia Card Interface
+  #
+  # INF Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  INF Silicon/Rockchip/Drivers/MmcDxe/MmcDxe.inf
+  #INF Silicon/Rockchip/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  
+  #
+  # DWC SDHCI (for eMMC slot)
+  #
+  INF Silicon/Rockchip/Drivers/SdhciHostDxe/SdhciHostDxe.inf
+
+  #
+  # AHCI Support
+  #
+  INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+  #
+  # SPI NOR FLASH
+  #
+  INF Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.inf
+
+  #
+  # Non-volatile FVB support
+  #
+  INF Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.inf
+  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+
+  # Human interface
+  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  # Custom
+  INF Silicon/Rockchip/Applications/MaskromReset/maskrom.inf
+  
+  # SCMI Driver
+  INF ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf
+
+  #
+  # UEFI applications
+  #
+  INF ShellPkg/Application/Shell/Shell.inf
+!ifdef $(INCLUDE_TFTP_COMMAND)
+  INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+!endif #$(INCLUDE_TFTP_COMMAND)
+  #INF Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+
+  #
+  # Bds
+  #
+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+  #
+  # Simple Init GUI
+  #
+!if $(ENABLE_SIMPLE_INIT)
+  INF src/main/SimpleInitMain.inf
+!endif
+
+[FV.BL33_AP_UEFI]
+FvAlignment        = 8
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+
+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FVMAIN
+    }
+  }
+
+!include Silicon/Rockchip/Rockchip.fdf.inc
+
+!ifdef $(ROCKCHIP_ACPIEN)
+[Rule.Common.DXE_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX	 DXE_DEPEX		Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32	 PE32			$(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI		 STRING="$(MODULE_NAME)" Optional
+    RAW 	 ACPI  Optional 	      |.acpi
+    RAW 	 ASL   Optional 	      |.aml
+  }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW ACPI		   |.acpi
+    RAW ASL		   |.aml
+  }
+!endif
--- a/edk2-platforms/Platform/OrangePi/Drivers/LogoDxe/Logo.bmp
+++ b/edk2-platforms/Platform/OrangePi/Drivers/LogoDxe/Logo.bmp
--- a/edk2-platforms/Platform/OrangePi/Drivers/LogoDxe/Logo.c
+++ b/edk2-platforms/Platform/OrangePi/Drivers/LogoDxe/Logo.c
@@ -0,0 +1,144 @@
+/** @file
+  Logo DXE Driver, install Edkii Platform Logo protocol.
+
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+  Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Protocol/HiiDatabase.h>
+#include <Protocol/GraphicsOutput.h>
+#include <Protocol/HiiImageEx.h>
+#include <Protocol/PlatformLogo.h>
+#include <Protocol/HiiPackageList.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+
+typedef struct {
+  EFI_IMAGE_ID                          ImageId;
+  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
+  INTN                                  OffsetX;
+  INTN                                  OffsetY;
+} LOGO_ENTRY;
+
+STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
+STATIC EFI_HII_HANDLE            mHiiHandle;
+STATIC LOGO_ENTRY                mLogos[] = {
+  {
+    IMAGE_TOKEN (IMG_LOGO),
+    EdkiiPlatformLogoDisplayAttributeCenter,
+    0,
+    0
+  }
+};
+
+/**
+  Load a platform logo image and return its data and attributes.
+
+  @param This              The pointer to this protocol instance.
+  @param Instance          The visible image instance is found.
+  @param Image             Points to the image.
+  @param Attribute         The display attributes of the image returned.
+  @param OffsetX           The X offset of the image regarding the Attribute.
+  @param OffsetY           The Y offset of the image regarding the Attribute.
+
+  @retval EFI_SUCCESS      The image was fetched successfully.
+  @retval EFI_NOT_FOUND    The specified image could not be found.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GetImage (
+  IN     EDKII_PLATFORM_LOGO_PROTOCOL          *This,
+  IN OUT UINT32                                *Instance,
+     OUT EFI_IMAGE_INPUT                       *Image,
+     OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
+     OUT INTN                                  *OffsetX,
+     OUT INTN                                  *OffsetY
+  )
+{
+  UINT32 Current;
+
+  if (Instance == NULL || Image == NULL ||
+      Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Current = *Instance;
+  if (Current >= ARRAY_SIZE (mLogos)) {
+    return EFI_NOT_FOUND;
+  }
+
+  (*Instance)++;
+  *Attribute = mLogos[Current].Attribute;
+  *OffsetX   = mLogos[Current].OffsetX;
+  *OffsetY   = mLogos[Current].OffsetY;
+
+  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
+                        mLogos[Current].ImageId, Image);
+}
+
+STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+  GetImage
+};
+
+/**
+  Entrypoint of this module.
+
+  This function is the entrypoint of this module. It installs the Edkii
+  Platform Logo protocol.
+
+  @param  ImageHandle       The firmware allocated handle for the EFI image.
+  @param  SystemTable       A pointer to the EFI System Table.
+
+  @retval EFI_SUCCESS       The entry point is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeLogo (
+  IN EFI_HANDLE               ImageHandle,
+  IN EFI_SYSTEM_TABLE         *SystemTable
+  )
+{
+  EFI_STATUS                  Status;
+  EFI_HII_PACKAGE_LIST_HEADER *PackageList;
+  EFI_HII_DATABASE_PROTOCOL   *HiiDatabase;
+  EFI_HANDLE                  Handle;
+
+  Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
+                  (VOID **) &HiiDatabase);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
+                  (VOID **) &mHiiImageEx);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Retrieve HII package list from ImageHandle
+  //
+  Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
+                  (VOID **) &PackageList, ImageHandle, NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR,
+      "HII Image Package with logo not found in PE/COFF resource section\n"));
+    return Status;
+  }
+
+  //
+  // Publish HII package list to HII Database.
+  //
+  Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
+                          &mHiiHandle);
+  if (!EFI_ERROR (Status)) {
+    Handle = NULL;
+    Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
+                    &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
+  }
+  return Status;
+}
--- a/edk2-platforms/Platform/OrangePi/Drivers/LogoDxe/Logo.idf
+++ b/edk2-platforms/Platform/OrangePi/Drivers/LogoDxe/Logo.idf
@@ -0,0 +1,10 @@
+// @file
+// Platform Logo image definition file.
+//
+// Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+// Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+
+#image IMG_LOGO Logo.bmp
--- a/edk2-platforms/Platform/OrangePi/Drivers/LogoDxe/LogoDxe.inf
+++ b/edk2-platforms/Platform/OrangePi/Drivers/LogoDxe/LogoDxe.inf
@@ -0,0 +1,48 @@
+## @file
+#  The default logo bitmap picture shown on setup screen.
+#
+#  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+#  Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = LogoDxe
+  FILE_GUID                      = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = InitializeLogo
+#
+#  This flag specifies whether HII resource section is generated into PE image.
+#
+  UEFI_HII_RESOURCE_SECTION      = TRUE
+
+[Sources]
+  Logo.bmp
+  Logo.c
+  Logo.idf
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  DebugLib
+
+[Protocols]
+  gEfiHiiDatabaseProtocolGuid        ## CONSUMES
+  gEfiHiiImageExProtocolGuid         ## CONSUMES
+  gEfiHiiPackageListProtocolGuid     ## PRODUCES CONSUMES
+  gEdkiiPlatformLogoProtocolGuid     ## PRODUCES
+
+[Depex]
+  gEfiHiiDatabaseProtocolGuid AND
+  gEfiHiiImageExProtocolGuid
--- a/edk2-platforms/Platform/OrangePi/OrangePi5/AcpiTables/AcpiTables.inf
+++ b/edk2-platforms/Platform/OrangePi/OrangePi5/AcpiTables/AcpiTables.inf
@@ -0,0 +1,64 @@
+#/** @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2019-2021, ARM Limited. All rights reserved.
+#  Copyright (c) Microsoft Corporation. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+  RK_COMMON_ACPI_DIR             = Silicon/Rockchip/RK3588/AcpiTables
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+
+[Sources]
+  Dsdt.asl
+  $(RK_COMMON_ACPI_DIR)/Madt.aslc
+  $(RK_COMMON_ACPI_DIR)/Fadt.aslc
+  $(RK_COMMON_ACPI_DIR)/Gtdt.aslc
+  $(RK_COMMON_ACPI_DIR)/Spcr.aslc
+  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
+  $(RK_COMMON_ACPI_DIR)/RK3588PcieIort.aslc
+  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Rockchip/RockchipPkg.dec
+  Platform/Rockchip/RK3588/RK3588.dec
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
--- a/edk2-platforms/Platform/OrangePi/OrangePi5/AcpiTables/Dsdt.asl
+++ b/edk2-platforms/Platform/OrangePi/OrangePi5/AcpiTables/Dsdt.asl
@@ -0,0 +1,39 @@
+/** @file
+ *
+ *  Differentiated System Definition Table (DSDT)
+ *
+ *  Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ *  Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
+ *  Copyright (c) Microsoft Corporation. All rights reserved.
+ *  Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include "AcpiTables.h"
+
+DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
+{
+  Scope (\_SB_)
+  {
+    include ("Cpu.asl")
+
+    // include ("Pcie.asl")
+    include ("Sata0.asl")
+    include ("Sata2.asl")
+    // include ("Emmc.asl")
+    include ("Sdhc.asl")
+    // include ("Gmac.asl")
+    // include ("Gpio.asl")
+    // include ("I2c.asl")
+    include ("Uart.asl")
+    // include ("Spi.asl")
+
+    // won't work on Windows, will trigger bugcheck by usbehci
+    // include ("Usb2.asl")
+
+    include ("Usb3Host0.asl")
+    include ("Usb3Host2.asl")
+  }
+}
--- a/edk2-platforms/Platform/OrangePi/OrangePi5/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-platforms/Platform/OrangePi/OrangePi5/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -0,0 +1,287 @@
+/** @file
+*
+*  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include <Base.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/GpioLib.h>
+#include <Library/RK806.h>
+#include <Soc.h>
+
+static struct regulator_init_data rk806_init_data[] = {
+  /* Master PMIC */
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
+  /* This is not configured in the OrangePi5's Linux device tree
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 1100000), */
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
+  /* The OPi is officially configured for the 837500 voltage, but is still marked as avdd_0v75_s0 in the schematic and Linux device tree. rockchip says this voltage is set to improve HDMI stability. */
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 837500),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  /* No dual PMICs on this platform */
+};
+
+VOID
+EFIAPI
+DwEmmcDxeIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux */
+}
+
+VOID
+EFIAPI
+SdhciEmmcDxeIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux */
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+}
+
+#define NS_CRU_BASE         0xFD7C0000
+#define CRU_CLKSEL_CON59    0x03EC
+#define CRU_CLKSEL_CON78    0x0438
+
+VOID
+EFIAPI
+Rk806SpiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
+  PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+}
+
+VOID
+EFIAPI
+Rk806Configure (
+  VOID
+  )
+{
+  UINTN RegCfgIndex;
+
+  RK806Init();
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
+    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+}
+
+VOID
+EFIAPI
+SetCPULittleVoltage (
+  IN UINT32 Microvolts
+  )
+{
+  struct regulator_init_data Rk806CpuLittleSupply =
+        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+
+  RK806RegulatorInit(Rk806CpuLittleSupply);
+}
+
+VOID
+EFIAPI
+NorFspiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
+             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
+#define FSPI_M1
+#if defined(FSPI_M0)
+   /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
+#elif defined(FSPI_M1)
+  /*FSPI M1*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
+#else
+  /*FSPI M2*/
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
+#endif
+}
+
+VOID
+EFIAPI
+GmacIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    /* gmac0 iomux */
+    BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+    BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+    BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+    BUS_IOC->GPIO2C_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+    BUS_IOC->GPIO4C_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0100;
+    BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011;
+    break;
+  case 1:
+    /* gmac1 iomux */
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+NorFspiEnableClock (
+  UINT32 *CruBase
+  )
+{
+  UINTN BaseAddr = (UINTN) CruBase;
+
+  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+}
+
+VOID
+EFIAPI
+I2cIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    /* io mux M2 */
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
+    break;
+  case 1:
+    /* io mux */
+    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
+    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
+    break;
+  case 2:
+    /* io mux */
+    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
+    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
+    PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
+    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    break;
+  case 3:
+    break;
+  case 4:
+    break;
+  case 5:
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+UsbPortPowerEnable (
+  VOID
+  )
+{
+  DEBUG((EFI_D_WARN, "UsbPortPowerEnable called\n"));
+  /* Set GPIO3 PC0 (TYPEC_EN) output high to power Type-C/USB2.0 ports */
+  GpioPinWrite (3, GPIO_PIN_PC0, TRUE);
+  GpioPinSetDirection (3, GPIO_PIN_PC0, GPIO_PIN_OUTPUT);
+
+  // DEBUG((EFI_D_WARN, "Trying to enable green led\n"));
+  // GpioPinWrite (1, GPIO_PIN_PA2, TRUE);
+  // GpioPinSetDirection (1, GPIO_PIN_PA2, GPIO_PIN_OUTPUT);
+}
+
+VOID
+EFIAPI
+Usb2PhyResume (
+  VOID
+  )
+{
+  MmioWrite32(0xfd5d0008, 0x20000000);
+  MmioWrite32(0xfd5d4008, 0x20000000);
+  MmioWrite32(0xfd5d8008, 0x20000000);
+  MmioWrite32(0xfd5dc008, 0x20000000);
+  MmioWrite32(0xfd7f0a10, 0x07000700);
+  MmioWrite32(0xfd7f0a10, 0x07000000);
+}
+
+VOID
+EFIAPI
+UsbDpPhyEnable (
+  VOID
+  )
+{
+  /* enable rx_lfps_en & usbdp_low_pwrn */
+  MmioWrite32(0xfd5c8004, 0x60006000);
+  MmioWrite32(0xfd5cc004, 0x60006000);
+  
+  /* remove rx-termination, we don't support SS yet */
+  MmioWrite32 (0xfd5c800c, 0x00030001);
+  MmioWrite32 (0xfd5cc00c, 0x00030001);
+}
+
+/* Orange Pi5 does not have PCIe3.0, wait for PCIe2 support and re-add it.
+VOID
+EFIAPI
+Pcie30IoInit(VOID)
+{
+  // Set reset and power IO to gpio output mode
+  GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
+  GpioPinSetDirection (1, GPIO_PIN_PA4, GPIO_PIN_OUTPUT);
+}
+
+VOID
+EFIAPI
+Pcie30PowerEn(VOID)
+{
+  // output high to enable power
+  GpioPinWrite (1, GPIO_PIN_PA4, TRUE);
+}
+
+VOID
+EFIAPI
+Pcie30PeReset(BOOLEAN enable)
+{
+  if(enable)
+    GpioPinWrite (4, GPIO_PIN_PB6, FALSE); // output low
+  else
+    GpioPinWrite (4, GPIO_PIN_PB6, TRUE); // output high
+}
+*/
+
+VOID
+EFIAPI
+PlatformEarlyInit (
+  VOID
+  )
+{
+  // Configure various things specific to this platform
+}
--- a/edk2-platforms/Platform/OrangePi/OrangePi5/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+++ b/edk2-platforms/Platform/OrangePi/OrangePi5/Library/RockchipPlatformLib/RockchipPlatformLib.inf
@@ -0,0 +1,43 @@
+#
+#  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = RockchipPlatformLib
+  FILE_GUID                      = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RockchipPlatformLib
+  RKPLATLIB_COMMON_DIR           = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Platform/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  SerialPortLib
+  CruLib
+  GpioLib
+
+[Sources.common]
+  RockchipPlatformLib.c
+  $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c
+  $(RKPLATLIB_COMMON_DIR)/RockchipSdhci.c
+
+[Sources.AARCH64]
+
+[Pcd]
+  gRockchipTokenSpaceGuid.PcdSdhciDxeBaseAddress
+  gRockchipTokenSpaceGuid.PcdI2cBusCount
+
--- a/edk2-platforms/Platform/OrangePi/OrangePi5/OrangePi5.dsc
+++ b/edk2-platforms/Platform/OrangePi/OrangePi5/OrangePi5.dsc
@@ -0,0 +1,633 @@
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2021-2022, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = OrangePi5
+  PLATFORM_GUID                  = d080df36-45e7-11ec-9726-f42a7dcb925d
+  PLATFORM_VERSION               = 0.2
+  DSC_SPECIFICATION              = 0x00010019
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = Platform/OrangePi/OrangePi5/OrangePi5.fdf
+
+  DEFINE CONFIG_NO_DEBUGLIB      = TRUE
+
+  #
+  # Must match defines in Silicon/Rockchip/RK3588/Include/VarStoreData.h
+  #
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT  = 0
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_MIN          = 1
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_MAX          = 2
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_CUSTOM       = 3
+
+  DEFINE COMBO_PHY_MODE_UNCONNECTED   = 0
+  DEFINE COMBO_PHY_MODE_PCIE          = 1
+  DEFINE COMBO_PHY_MODE_SATA          = 2
+  DEFINE COMBO_PHY_MODE_USB3          = 3
+
+  #
+  # Network definition
+  #
+  DEFINE NETWORK_SNP_ENABLE             = FALSE
+  DEFINE NETWORK_IP6_ENABLE             = FALSE
+  DEFINE NETWORK_TLS_ENABLE             = FALSE
+  DEFINE NETWORK_HTTP_BOOT_ENABLE       = FALSE
+  DEFINE NETWORK_ISCSI_ENABLE           = FALSE
+  DEFINE NETWORK_VLAN_ENABLE            = FALSE
+!include Silicon/Rockchip/Rockchip.dsc.inc
+!include MdePkg/MdeLibs.dsc.inc
+
+[LibraryClasses.common]
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmPlatformLib|Silicon/Rockchip/RK3588/Library/PlatformLib/PlatformLib.inf
+  AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf
+  CruLib|Silicon/Rockchip/Library/CruLib/CruLib.inf
+
+  DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
+
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+  # UiApp dependencies
+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+
+  #RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+  TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
+
+  # USB Requirements
+  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+
+  # PCIe
+  PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+  #PciHostBridgeLib|Silicon/Rockchip/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+  #PciExpressLib|Silicon/Rockchip/Library/PciExpressLib/PciExpressLib.inf
+  PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+
+
+  # VariableRuntimeDxe Requirements
+  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+  AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+  TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+  VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+
+  AndroidBootImgLib|edk2/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.inf
+
+  RockchipDisplayLib|Silicon/Rockchip/Library/DisplayLib/RockchipDisplayLib.inf
+
+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+  LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf
+
+  # OTP Library
+  OtpLib|Silicon/Rockchip/RK3588/Library/OtpLib/OtpLib.inf
+
+  #
+  # Custom libraries
+  #
+  RockchipPlatformLib|Platform/OrangePi/OrangePi5/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+  ResetSystemLib|Silicon/Rockchip/Library/ResetSystemLib/ResetSystemLib.inf
+  PlatformBootManagerLib|Silicon/Rockchip/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+  SerialPortLib|Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf
+  GpioLib|Silicon/Rockchip/RK3588/Library/GpioLib/GpioLib.inf
+  # SCMI Mailbox Transport Layer
+  ArmMtlLib|Silicon/Rockchip/Library/RkMtlLib/RkMtlLib.inf
+
+[LibraryClasses.common.SEC]
+  PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+  ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+  HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
+  MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+  MemoryInitPeiLib|Silicon/Rockchip/RK3588/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
+  PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+  PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+  RockchipPlatformLib|Platform/OrangePi/OrangePi5/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+
+[BuildOptions]
+  GCC:*_*_*_PLATFORM_FLAGS = -I$(WORKSPACE)/Silicon/Rockchip/RK3588/Include -I$(WORKSPACE)/Platform/Rockchip/RK3588/Include -I$(WORKSPACE)/Silicon/Rockchip/Include
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+  #  If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+  #  It could be set FALSE to save size.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+
+[PcdsFixedAtBuild.common]
+  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)"
+
+  # System Memory (1GB)
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000
+  gRK3588TokenSpaceGuid.PcdTotalMemorySize|0x200000000
+  
+  # RK3588 CPU profile
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|8
+  gArmPlatformTokenSpaceGuid.PcdClusterCount|1
+
+  # SMBIOS platform config
+  gRockchipTokenSpaceGuid.PcdPlatformName|"Orange Pi 5"
+  gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Orange Pi"
+  gRockchipTokenSpaceGuid.PcdFamilyName|"Orange Pi 5"
+  gRockchipTokenSpaceGuid.PcdProductUrl|"http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-5.html"
+  gRockchipTokenSpaceGuid.PcdMemoryVendorName|"TBD"
+
+  # I2C
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 }
+  gRockchipTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0 }
+  gRockchipTokenSpaceGuid.PcdI2cClockFrequency|198000000
+  gRockchipTokenSpaceGuid.PcdI2cBaudRate|100000
+  gRockchipTokenSpaceGuid.PcdI2cBusCount|1
+  gRockchipTokenSpaceGuid.PcdI2cDemoAddresses|{ 0x51 } #/* RTCYM8563TS 0x51@bus2 */
+  gRockchipTokenSpaceGuid.PcdI2cDemoBuses|{ 0x2 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ 2, 3 } # SCMI_CLK_CPUB01, SCMI_CLK_CPUB23
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorMinVoltages|{ UINT32(550000), UINT32(550000) }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorMaxVoltages|{ UINT32(1050000), UINT32(1050000) }
+
+  ## UART2 - Serial Terminal
+  DEFINE SERIAL_BASE = 0xFEB50000 # UART2
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|$(SERIAL_BASE)
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|1500000
+  gHisiTokenSpaceGuid.PcdSerialPortSendDelay|500000
+  gHisiTokenSpaceGuid.PcdUartClkInHz|24000000
+
+  ## SPI - SPI2 for test
+  gRockchipTokenSpaceGuid.SpiTestBaseAddr|0xFEB20000
+  gRockchipTokenSpaceGuid.SpiRK806BaseAddr|0xFEB20000
+  ## PL031 RealTimeClock
+  #gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0xF8003000
+
+  ## NOR FLASH
+  gRockchipTokenSpaceGuid.FspiBaseAddr|0xFE2B0000
+
+  ## CRU
+  gRockchipTokenSpaceGuid.CruBaseAddr|0xFD7C0000
+
+  #gRockchipTokenSpaceGuid.PcdSpiVariableOffset|0x3C0000
+  #
+  # ARM General Interrupt Controller
+  #
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0xfe600000
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xfe600000
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0xfe680000
+
+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3
+
+  # GUID of the UI app
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+
+  gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
+
+  #
+  # DW SD card controller
+  #
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeBaseAddress|0xfe2c0000
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz|100000000
+  gDesignWareTokenSpaceGuid.PcdDwPermitObsoleteDrivers|TRUE
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeFifoDepth|256
+  #
+  # SDHCI controller
+  #
+  gRockchipTokenSpaceGuid.PcdSdhciDxeBaseAddress|0xfe2e0000
+
+  #
+  # PCIe controller
+  #
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress|0xfe150000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress|0xf5000000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress|0xf0000000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize|0x100000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress|0xf0100000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize|0x10000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress|0xf0200000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize|0xe00000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64|0x901000000 #deduct 0x1000000 ECAM space
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64|0x3f000000
+
+  #
+  # Fastboot
+  #
+  gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbVendorId|0x2207
+  gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbProductId|0x0001
+
+  #
+  # USB2 EHCI + OHCI companion controllers
+  #
+  gRockchipTokenSpaceGuid.PcdEhciBaseAddress|0xfc800000
+  gRockchipTokenSpaceGuid.PcdNumEhciController|2
+  gRockchipTokenSpaceGuid.PcdEhciSize|0x40000
+  gRockchipTokenSpaceGuid.PcdOhciSize|0x40000
+
+  #
+  # DWC3 controller
+  #
+  gRockchipTokenSpaceGuid.PcdDwc3BaseAddresses|{ UINT32(0xfc000000), UINT32(0xfc400000), UINT32(0xfcd00000) }
+  gRockchipTokenSpaceGuid.PcdDwc3Size|0x400000
+
+  #
+  # Android Loader
+  #
+  gRK3588TokenSpaceGuid.PcdAndroidBootDevicePath|L"\\EFI\\BOOT\\GRUBAA64.EFI"
+  gRK3588TokenSpaceGuid.PcdSdBootDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00E023F70000000000)/SD(0x0)"
+  gRK3588TokenSpaceGuid.PcdKernelBootArg|L"earlycon=uart8250,mmio32,0xfeb50000 root=PARTUUID=614e0000-0000 rw rootwait"
+  gEmbeddedTokenSpaceGuid.PcdAndroidBootDevicePath|L"VenHw(100C2CFA-B586-4198-9B4C-1683D195B1DA)/HD(3,GPT,7A3F0000-0000-446A-8000-702F00006273,0x8000,0x20000)"
+
+  # ACPI Enable
+  gRK3588TokenSpaceGuid.AcpiEnable|TRUE
+
+  #
+  # Display
+  #
+  gRockchipTokenSpaceGuid.PcdLcdPixelFormat|0x00000001
+  gRockchipTokenSpaceGuid.PcdEdpId|0x00000000 #edp0
+  #gRockchipTokenSpaceGuid.PcdEdpId|0x00000001 #edp1
+  gRockchipTokenSpaceGuid.PcdHdmiId|0x00000000 #hdmi0
+  #gRockchipTokenSpaceGuid.PcdHdmiId|0x00000001 #hdmi1
+
+  #
+  # CPU Performance default values
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|FALSE
+  gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE)
+  gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_UNCONNECTED)
+  gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3)
+
+  #  BIT0  - Initialization message.<BR>
+  #  BIT1  - Warning message.<BR>
+  #  BIT2  - Load Event message.<BR>
+  #  BIT3  - File System message.<BR>
+  #  BIT4  - Allocate or Free Pool message.<BR>
+  #  BIT5  - Allocate or Free Page message.<BR>
+  #  BIT6  - Information message.<BR>
+  #  BIT7  - Dispatcher message.<BR>
+  #  BIT8  - Variable message.<BR>
+  #  BIT10 - Boot Manager message.<BR>
+  #  BIT12 - BlockIo Driver message.<BR>
+  #  BIT14 - Network Driver message.<BR>
+  #  BIT16 - UNDI Driver message.<BR>
+  #  BIT17 - LoadFile message.<BR>
+  #  BIT19 - Event message.<BR>
+  #  BIT20 - Global Coherency Database changes message.<BR>
+  #  BIT21 - Memory range cachability changes message.<BR>
+  #  BIT22 - Detailed debug message.<BR>
+  #  BIT31 - Error message.<BR>
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0e
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000000
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0f
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x800B0507
+!endif
+# 0x800B05C7
+# Use 0x807B55FF to enable all debug messages
+
+[PcdsDynamicDefault.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x007C0000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x007CF000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x007D0000
+
+  #
+  # Display
+  #
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x780
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x438
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0
+
+[PcdsDynamicHii.common.DEFAULT]
+  #
+  # CPU Performance
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPreset|L"CpuPerf_CPULClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockCustom|L"CpuPerf_CPULClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|1800
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPreset|L"CpuPerf_CPUB01ClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockCustom|L"CpuPerf_CPUB01ClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|2400
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPreset|L"CpuPerf_CPUB23ClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockCustom|L"CpuPerf_CPUB23ClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|2400
+  gRK3588TokenSpaceGuid.PcdCPULClusterVoltageMode|L"CpuPerf_CPULClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0
+  gRK3588TokenSpaceGuid.PcdCPULClusterVoltageCustom|L"CpuPerf_CPULClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|950000
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterVoltageMode|L"CpuPerf_CPUB01ClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterVoltageCustom|L"CpuPerf_CPUB01ClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|1000000
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterVoltageMode|L"CpuPerf_CPUB23ClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterVoltageCustom|L"CpuPerf_CPUB23ClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|1000000
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY
+  #
+  gRK3588TokenSpaceGuid.PcdComboPhy0Mode|L"ComboPhy0Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault
+  gRK3588TokenSpaceGuid.PcdComboPhy1Mode|L"ComboPhy1Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault
+  gRK3588TokenSpaceGuid.PcdComboPhy2Mode|L"ComboPhy2Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault
+  
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+  #
+  # PEI Phase modules
+  #
+  ArmPlatformPkg/PrePi/PeiUniCore.inf
+  MdeModulePkg/Core/Pei/PeiMain.inf
+  MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+
+  #
+  # DXE
+  #
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+  }
+
+  #
+  # Architectural Protocols
+  #
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+  #EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
+  <LibraryClasses>
+    RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
+  }
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  #PCIe
+  #Silicon/Rockchip/Library/PciExpressLib/PciExpressLib.inf
+  #Silicon/Rockchip/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+  #Silicon/Rockchip/Drivers/PciPlatform/PcieInitDxe.inf
+  ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  #MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+  #MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.inf
+
+  MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+  
+  #
+  # Non-volatile FVB support
+  #
+  Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.inf
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+
+  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf
+  #Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
+  Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf
+  Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
+
+  Platform/OrangePi/Drivers/LogoDxe/LogoDxe.inf
+
+  #
+  # SCMI Driver
+  #
+  ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf
+
+  #
+  # ACPI Support
+  #
+  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+  Platform/OrangePi/OrangePi5/AcpiTables/AcpiTables.inf
+
+  #
+  # Device tree
+  #
+  EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf {
+  <LibraryClasses>
+    DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefault/DxeDtPlatformDtbLoaderLibDefault.inf
+  }
+
+  #
+  # GPIO
+  #
+  Platform/Rockchip/RK3588/RK3588GpioDxe/RK3588GpioDxe.inf
+
+  #
+  # Virtual Keyboard
+  #
+  EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
+
+  # I2C drivers
+  Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.inf
+  MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
+  Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.inf
+  Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.inf
+  Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.inf
+
+  #
+  # MMC/SD
+  #
+  #EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
+  #Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  Silicon/Rockchip/Drivers/MmcDxe/MmcDxe.inf
+  # sdcard is dwemmc, sdhci is for eMMC.
+  Silicon/Rockchip/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  Silicon/Rockchip/Drivers/SdhciHostDxe/SdhciHostDxe.inf
+
+  #
+  # NOR FLASH
+  #
+  Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.inf
+  Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+
+  #
+  # AHCI Support
+  #
+  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+  #
+  # SPI TEST
+  #
+  # Silicon/Rockchip/Library/SpiLib/SpiTest.inf
+
+  #
+  # SMBIOS Support
+  #
+  Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  
+  #
+  # USB Ohci Controller
+  #
+  Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf
+
+  #
+  # USB Ehci Controller
+  #
+  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+
+  #
+  # USB Dwc3 Controller
+  #
+  Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
+  #
+  # USB Xhci Controller
+  #
+  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+
+  #
+  # USB Host Support
+  #
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+  #
+  # USB Mass Storage Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # USB Kb Support
+  #
+  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+  #
+  # USB Mouse Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+
+  #
+  # USB MouseAbsolutePointer Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointerDxe.inf
+
+  #
+  # USB Peripheral Support
+  #
+  EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
+
+  #
+  # Fastboot
+  #
+  EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
+
+  #
+  # Android Boot applications
+  #
+  EmbeddedPkg/Application/AndroidBoot/AndroidBootApp.inf
+
+  #
+  # UEFI Network Stack
+  #
+!include NetworkPkg/Network.dsc.inc
+  #
+  # AX88772 Ethernet Driver
+  #
+  Drivers/ASIX/Bus/Usb/UsbNetworking/Ax88772c/Ax88772c.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+  FatPkg/EnhancedFatDxe/Fat.inf
+
+  #
+  # Bds
+  #
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  MdeModulePkg/Application/UiApp/UiApp.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  ShellPkg/Application/Shell/Shell.inf {
+    <LibraryClasses>
+      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+      NULL|Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.inf
+      NULL|Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf
+      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+      OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
+      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+      gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+  }
+!ifdef $(INCLUDE_TFTP_COMMAND)
+  ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+!endif #$(INCLUDE_TFTP_COMMAND)
+
+  #
+  # Custom Applications and drivers
+  #
+  Silicon/Rockchip/Applications/MaskromReset/maskrom.inf
+
+  # Platform drivers
+  Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf
+
--- a/edk2-platforms/Platform/OrangePi/OrangePi5/OrangePi5.fdf
+++ b/edk2-platforms/Platform/OrangePi/OrangePi5/OrangePi5.fdf
@@ -0,0 +1,375 @@
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2021-2022, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.NOR_FLASH_IMAGE]
+BaseAddress   = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
+Size          = 0x00800000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize     = 0x00001000
+NumBlocks     = 0x800
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+0x00200000|0x00500000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = BL33_AP_UEFI
+
+# NV_VARIABLE_STORE
+0x007C0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+
+# NV_FTW_WORKING header
+0x007D0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+# NV_FTW_WORKING data
+0x007E0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+BlockSize          = 0x40
+NumBlocks          = 0         # This FV gets compressed so make it just big enough
+FvAlignment        = 8         # FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  APRIORI DXE {
+    INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+  }
+
+  INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+  #
+  # PI DXE Drivers producing Architectural Protocols (EFI Services)
+  #
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  #
+  # Multiple Console IO support
+  #
+  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+
+  INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+
+  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  #
+  # ACPI Support
+  #
+  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+  INF RuleOverride = ACPITABLE Platform/OrangePi/OrangePi5/AcpiTables/AcpiTables.inf
+
+  #
+  # Device tree
+  #
+  INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf
+  # FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 {
+  #   SECTION RAW = Platform/Rockchip/DeviceTree/rk3588.dtb
+  # }
+
+  #
+  # GPIO
+  #
+  INF Platform/Rockchip/RK3588/RK3588GpioDxe/RK3588GpioDxe.inf
+  #INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf
+
+  #
+  # I2C
+  #
+  INF Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.inf
+  INF MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
+  # INF Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.inf
+  INF Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.inf
+
+  #
+  # Virtual Keyboard
+  #
+  INF EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
+
+  #
+  # Display Support
+  #
+  
+  INF Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf
+  #INF Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
+  INF Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf
+  INF Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
+  INF Platform/OrangePi/Drivers/LogoDxe/LogoDxe.inf
+
+  INF Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf
+
+  #
+  # SMBIOS Support
+  #
+  INF Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+  INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+
+  #
+  # USB Ehci Controller
+  #
+  INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+
+  #
+  # USB Ohci Controller
+  #
+  INF Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf
+
+  #
+  # USB Dwc3 Controller
+  #
+  INF Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
+  #
+  # USB Xhci Controller
+  #
+  INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+
+  #
+  # USB Host Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+  #
+  # USB Mass Storage Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # USB Kb Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+  #
+  # USB Mouse Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+
+  #
+  # USB MouseAbsolutePointer Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointerDxe.inf
+
+  #
+  # USB Peripheral Support
+  #
+  INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
+
+  #
+  # Fastboot
+  #
+  INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
+
+
+  #PCIe
+  #INF Silicon/Rockchip/Drivers/PciPlatform/PcieInitDxe.inf
+
+  # Required by PCI
+  INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
+  # PCI Support
+  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  #INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+  #INF MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.inf
+
+  #INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+  INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+  #
+  # Android Boot applications
+  #
+  INF EmbeddedPkg/Application/AndroidBoot/AndroidBootApp.inf
+
+  #
+  # UEFI Network Stack
+  #
+!include NetworkPkg/Network.fdf.inc
+
+  #
+  # AX88772 Ethernet Driver for Apple Ethernet Adapter
+  #
+  INF Drivers/ASIX/Bus/Usb/UsbNetworking/Ax88772c/Ax88772c.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF FatPkg/EnhancedFatDxe/Fat.inf
+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  #
+  # Multimedia Card Interface
+  #
+  # INF Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  INF Silicon/Rockchip/Drivers/MmcDxe/MmcDxe.inf
+  # sdcard is dwemmc, sdhci is for eMMC.
+  INF Silicon/Rockchip/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  
+  # Needs to be disabled if booting from eMMC
+  # INF Silicon/Rockchip/Drivers/SdhciHostDxe/SdhciHostDxe.inf
+
+  #
+  # AHCI Support
+  #
+  INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+  #
+  # SPI NOR FLASH
+  #
+  INF Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.inf
+
+  #
+  # Non-volatile FVB support
+  #
+  INF Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.inf
+  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+
+  # Human interface
+  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  # Custom
+  INF Silicon/Rockchip/Applications/MaskromReset/maskrom.inf
+  
+  # SCMI Driver
+  INF ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf
+
+  #
+  # UEFI applications
+  #
+  INF ShellPkg/Application/Shell/Shell.inf
+!ifdef $(INCLUDE_TFTP_COMMAND)
+  INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+!endif #$(INCLUDE_TFTP_COMMAND)
+  #INF Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+
+  #
+  # Bds
+  #
+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+[FV.BL33_AP_UEFI]
+FvAlignment        = 8
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+
+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FVMAIN
+    }
+  }
+
+!include Silicon/Rockchip/Rockchip.fdf.inc
+
+!ifdef $(ROCKCHIP_ACPIEN)
+[Rule.Common.DXE_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX	 DXE_DEPEX		Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32	 PE32			$(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI		 STRING="$(MODULE_NAME)" Optional
+    RAW 	 ACPI  Optional 	      |.acpi
+    RAW 	 ASL   Optional 	      |.aml
+  }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW ACPI		   |.acpi
+    RAW ASL		   |.aml
+  }
+!endif
--- a/edk2-platforms/Platform/Radxa/Drivers/LogoDxe/Logo.bmp
+++ b/edk2-platforms/Platform/Radxa/Drivers/LogoDxe/Logo.bmp
--- a/edk2-platforms/Platform/Radxa/Drivers/LogoDxe/Logo.c
+++ b/edk2-platforms/Platform/Radxa/Drivers/LogoDxe/Logo.c
@@ -0,0 +1,144 @@
+/** @file
+  Logo DXE Driver, install Edkii Platform Logo protocol.
+
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+  Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Protocol/HiiDatabase.h>
+#include <Protocol/GraphicsOutput.h>
+#include <Protocol/HiiImageEx.h>
+#include <Protocol/PlatformLogo.h>
+#include <Protocol/HiiPackageList.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+
+typedef struct {
+  EFI_IMAGE_ID                          ImageId;
+  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
+  INTN                                  OffsetX;
+  INTN                                  OffsetY;
+} LOGO_ENTRY;
+
+STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
+STATIC EFI_HII_HANDLE            mHiiHandle;
+STATIC LOGO_ENTRY                mLogos[] = {
+  {
+    IMAGE_TOKEN (IMG_LOGO),
+    EdkiiPlatformLogoDisplayAttributeCenter,
+    0,
+    0
+  }
+};
+
+/**
+  Load a platform logo image and return its data and attributes.
+
+  @param This              The pointer to this protocol instance.
+  @param Instance          The visible image instance is found.
+  @param Image             Points to the image.
+  @param Attribute         The display attributes of the image returned.
+  @param OffsetX           The X offset of the image regarding the Attribute.
+  @param OffsetY           The Y offset of the image regarding the Attribute.
+
+  @retval EFI_SUCCESS      The image was fetched successfully.
+  @retval EFI_NOT_FOUND    The specified image could not be found.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GetImage (
+  IN     EDKII_PLATFORM_LOGO_PROTOCOL          *This,
+  IN OUT UINT32                                *Instance,
+     OUT EFI_IMAGE_INPUT                       *Image,
+     OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
+     OUT INTN                                  *OffsetX,
+     OUT INTN                                  *OffsetY
+  )
+{
+  UINT32 Current;
+
+  if (Instance == NULL || Image == NULL ||
+      Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Current = *Instance;
+  if (Current >= ARRAY_SIZE (mLogos)) {
+    return EFI_NOT_FOUND;
+  }
+
+  (*Instance)++;
+  *Attribute = mLogos[Current].Attribute;
+  *OffsetX   = mLogos[Current].OffsetX;
+  *OffsetY   = mLogos[Current].OffsetY;
+
+  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
+                        mLogos[Current].ImageId, Image);
+}
+
+STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+  GetImage
+};
+
+/**
+  Entrypoint of this module.
+
+  This function is the entrypoint of this module. It installs the Edkii
+  Platform Logo protocol.
+
+  @param  ImageHandle       The firmware allocated handle for the EFI image.
+  @param  SystemTable       A pointer to the EFI System Table.
+
+  @retval EFI_SUCCESS       The entry point is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeLogo (
+  IN EFI_HANDLE               ImageHandle,
+  IN EFI_SYSTEM_TABLE         *SystemTable
+  )
+{
+  EFI_STATUS                  Status;
+  EFI_HII_PACKAGE_LIST_HEADER *PackageList;
+  EFI_HII_DATABASE_PROTOCOL   *HiiDatabase;
+  EFI_HANDLE                  Handle;
+
+  Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
+                  (VOID **) &HiiDatabase);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
+                  (VOID **) &mHiiImageEx);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Retrieve HII package list from ImageHandle
+  //
+  Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
+                  (VOID **) &PackageList, ImageHandle, NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR,
+      "HII Image Package with logo not found in PE/COFF resource section\n"));
+    return Status;
+  }
+
+  //
+  // Publish HII package list to HII Database.
+  //
+  Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
+                          &mHiiHandle);
+  if (!EFI_ERROR (Status)) {
+    Handle = NULL;
+    Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
+                    &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
+  }
+  return Status;
+}
--- a/edk2-platforms/Platform/Radxa/Drivers/LogoDxe/Logo.idf
+++ b/edk2-platforms/Platform/Radxa/Drivers/LogoDxe/Logo.idf
@@ -0,0 +1,10 @@
+// @file
+// Platform Logo image definition file.
+//
+// Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+// Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+
+#image IMG_LOGO Logo.bmp
--- a/edk2-platforms/Platform/Radxa/Drivers/LogoDxe/LogoDxe.inf
+++ b/edk2-platforms/Platform/Radxa/Drivers/LogoDxe/LogoDxe.inf
@@ -0,0 +1,48 @@
+## @file
+#  The default logo bitmap picture shown on setup screen.
+#
+#  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+#  Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = LogoDxe
+  FILE_GUID                      = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = InitializeLogo
+#
+#  This flag specifies whether HII resource section is generated into PE image.
+#
+  UEFI_HII_RESOURCE_SECTION      = TRUE
+
+[Sources]
+  Logo.bmp
+  Logo.c
+  Logo.idf
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  DebugLib
+
+[Protocols]
+  gEfiHiiDatabaseProtocolGuid        ## CONSUMES
+  gEfiHiiImageExProtocolGuid         ## CONSUMES
+  gEfiHiiPackageListProtocolGuid     ## PRODUCES CONSUMES
+  gEdkiiPlatformLogoProtocolGuid     ## PRODUCES
+
+[Depex]
+  gEfiHiiDatabaseProtocolGuid AND
+  gEfiHiiImageExProtocolGuid
--- a/edk2-platforms/Platform/Radxa/ROCK5A/AcpiTables/AcpiTables.inf
+++ b/edk2-platforms/Platform/Radxa/ROCK5A/AcpiTables/AcpiTables.inf
@@ -0,0 +1,64 @@
+#/** @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2019-2021, ARM Limited. All rights reserved.
+#  Copyright (c) Microsoft Corporation. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+  RK_COMMON_ACPI_DIR             = Silicon/Rockchip/RK3588/AcpiTables
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+
+[Sources]
+  Dsdt.asl
+  $(RK_COMMON_ACPI_DIR)/Madt.aslc
+  $(RK_COMMON_ACPI_DIR)/Fadt.aslc
+  $(RK_COMMON_ACPI_DIR)/Gtdt.aslc
+  $(RK_COMMON_ACPI_DIR)/Spcr.aslc
+  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
+  $(RK_COMMON_ACPI_DIR)/RK3588PcieIort.aslc
+  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Rockchip/RockchipPkg.dec
+  Platform/Rockchip/RK3588/RK3588.dec
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
--- a/edk2-platforms/Platform/Radxa/ROCK5A/AcpiTables/Dsdt.asl
+++ b/edk2-platforms/Platform/Radxa/ROCK5A/AcpiTables/Dsdt.asl
@@ -0,0 +1,38 @@
+/** @file
+ *
+ *  Differentiated System Definition Table (DSDT)
+ *
+ *  Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ *  Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
+ *  Copyright (c) Microsoft Corporation. All rights reserved.
+ *  Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include "AcpiTables.h"
+
+DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
+{
+  Scope (\_SB_)
+  {
+    include ("Cpu.asl")
+
+    // include ("Pcie.asl")
+    include ("Sata0.asl")
+    // include ("Emmc.asl")
+    include ("Sdhc.asl")
+    // include ("Gmac.asl")
+    // include ("Gpio.asl")
+    // include ("I2c.asl")
+    include ("Uart.asl")
+    // include ("Spi.asl")
+
+    // won't work on Windows, will trigger bugcheck by usbehci
+    // include ("Usb2.asl")
+
+    include ("Usb3Host0.asl")
+    include ("Usb3Host2.asl")
+  }
+}
--- a/edk2-platforms/Platform/Radxa/ROCK5A/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-platforms/Platform/Radxa/ROCK5A/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -0,0 +1,267 @@
+/** @file
+*
+*  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include <Base.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/GpioLib.h>
+#include <Library/RK806.h>
+#include <Soc.h>
+
+static struct regulator_init_data rk806_init_data[] = {
+  /* Master PMIC */
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
+  //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  /* No dual PMICs on this platform */
+};
+
+VOID
+EFIAPI
+DwEmmcDxeIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux (microSD socket) */
+  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+}
+
+VOID
+EFIAPI
+SdhciEmmcDxeIoMux (
+  VOID
+  )
+{
+  /* sdhci0 iomux (eMMC socket) */
+  /* Do not override, set by earlier boot stages. */
+}
+
+#define NS_CRU_BASE         0xFD7C0000
+#define CRU_CLKSEL_CON59    0x03EC
+#define CRU_CLKSEL_CON78    0x0438
+
+VOID
+EFIAPI
+Rk806SpiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
+  PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+}
+
+VOID
+EFIAPI
+Rk806Configure (
+  VOID
+  )
+{
+  UINTN RegCfgIndex;
+
+  RK806Init();
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
+    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+}
+
+VOID
+EFIAPI
+SetCPULittleVoltage (
+  IN UINT32 Microvolts
+  )
+{
+  struct regulator_init_data Rk806CpuLittleSupply =
+        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+
+  RK806RegulatorInit(Rk806CpuLittleSupply);
+}
+
+VOID
+EFIAPI
+NorFspiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  /* Do not override, set by earlier boot stages. */
+}
+
+VOID
+EFIAPI
+GmacIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    /* gmac0 iomux */
+    BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+    BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+    BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+    BUS_IOC->GPIO2C_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+    BUS_IOC->GPIO4C_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0100;
+    BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011;
+    break;
+  case 1:
+    /* gmac1 iomux */
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+NorFspiEnableClock (
+  UINT32 *CruBase
+  )
+{
+  UINTN BaseAddr = (UINTN) CruBase;
+
+  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+}
+
+VOID
+EFIAPI
+I2cIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    /* io mux M2 */
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
+    break;
+  case 1:
+    /* io mux */
+    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
+    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
+    break;
+  case 2:
+    /* io mux */
+    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
+    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
+    PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
+    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    break;
+  case 3:
+    break;
+  case 4:
+    break;
+  case 5:
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+UsbPortPowerEnable (
+  VOID
+  )
+{
+  DEBUG((EFI_D_WARN, "UsbPortPowerEnable called\n"));
+  
+  GpioPinSetDirection (4, GPIO_PIN_PB5, GPIO_PIN_OUTPUT);
+  GpioPinWrite (4, GPIO_PIN_PB5, TRUE);
+
+  GpioPinSetDirection (0, GPIO_PIN_PD4, GPIO_PIN_OUTPUT);
+  GpioPinWrite (0, GPIO_PIN_PD4, TRUE);
+}
+
+VOID
+EFIAPI
+Usb2PhyResume (
+  VOID
+  )
+{
+  MmioWrite32(0xfd5d0008, 0x20000000);
+  MmioWrite32(0xfd5d4008, 0x20000000);
+  MmioWrite32(0xfd5d8008, 0x20000000);
+  MmioWrite32(0xfd5dc008, 0x20000000);
+  MmioWrite32(0xfd7f0a10, 0x07000700);
+  MmioWrite32(0xfd7f0a10, 0x07000000);
+}
+
+VOID
+EFIAPI
+UsbDpPhyEnable (
+  VOID
+  )
+{
+  /* enable rx_lfps_en & usbdp_low_pwrn */
+  MmioWrite32(0xfd5c8004, 0x60006000);
+  MmioWrite32(0xfd5cc004, 0x60006000);
+  
+  /* remove rx-termination, we don't support SS yet */
+  MmioWrite32 (0xfd5c800c, 0x00030001);
+  MmioWrite32 (0xfd5cc00c, 0x00030001);
+}
+
+/* ROCK5A does not have PCIe3.0, wait for PCIe2 support and re-add it.
+VOID
+EFIAPI
+Pcie30IoInit(VOID)
+{
+  // Set reset and power IO to gpio output mode
+  GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
+  GpioPinSetDirection (1, GPIO_PIN_PA4, GPIO_PIN_OUTPUT);
+}
+
+VOID
+EFIAPI
+Pcie30PowerEn(VOID)
+{
+  // output high to enable power
+  GpioPinWrite (1, GPIO_PIN_PA4, TRUE);
+}
+
+VOID
+EFIAPI
+Pcie30PeReset(BOOLEAN enable)
+{
+  if(enable)
+    GpioPinWrite (4, GPIO_PIN_PB6, FALSE); // output low
+  else
+    GpioPinWrite (4, GPIO_PIN_PB6, TRUE); // output high
+}
+*/
+
+VOID
+EFIAPI
+PlatformEarlyInit (
+  VOID
+  )
+{
+  // Configure various things specific to this platform
+}
--- a/edk2-platforms/Platform/Radxa/ROCK5A/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+++ b/edk2-platforms/Platform/Radxa/ROCK5A/Library/RockchipPlatformLib/RockchipPlatformLib.inf
@@ -0,0 +1,43 @@
+#
+#  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = RockchipPlatformLib
+  FILE_GUID                      = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RockchipPlatformLib
+  RKPLATLIB_COMMON_DIR           = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Platform/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  SerialPortLib
+  CruLib
+  GpioLib
+
+[Sources.common]
+  RockchipPlatformLib.c
+  $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c
+  $(RKPLATLIB_COMMON_DIR)/RockchipSdhci.c
+
+[Sources.AARCH64]
+
+[Pcd]
+  gRockchipTokenSpaceGuid.PcdSdhciDxeBaseAddress
+  gRockchipTokenSpaceGuid.PcdI2cBusCount
+
--- a/edk2-platforms/Platform/Radxa/ROCK5A/ROCK5A.dsc
+++ b/edk2-platforms/Platform/Radxa/ROCK5A/ROCK5A.dsc
@@ -0,0 +1,633 @@
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2021-2022, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = ROCK5A
+  PLATFORM_GUID                  = d080df36-45e7-11ec-9726-f42a7dcb925d
+  PLATFORM_VERSION               = 0.2
+  DSC_SPECIFICATION              = 0x00010019
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = Platform/Radxa/ROCK5A/ROCK5A.fdf
+
+  DEFINE CONFIG_NO_DEBUGLIB      = TRUE
+
+  #
+  # Must match defines in Silicon/Rockchip/RK3588/Include/VarStoreData.h
+  #
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT  = 0
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_MIN          = 1
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_MAX          = 2
+  DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_CUSTOM       = 3
+
+  DEFINE COMBO_PHY_MODE_UNCONNECTED   = 0
+  DEFINE COMBO_PHY_MODE_PCIE          = 1
+  DEFINE COMBO_PHY_MODE_SATA          = 2
+  DEFINE COMBO_PHY_MODE_USB3          = 3
+
+  #
+  # Network definition
+  #
+  DEFINE NETWORK_SNP_ENABLE             = FALSE
+  DEFINE NETWORK_IP6_ENABLE             = FALSE
+  DEFINE NETWORK_TLS_ENABLE             = FALSE
+  DEFINE NETWORK_HTTP_BOOT_ENABLE       = FALSE
+  DEFINE NETWORK_ISCSI_ENABLE           = FALSE
+  DEFINE NETWORK_VLAN_ENABLE            = FALSE
+!include Silicon/Rockchip/Rockchip.dsc.inc
+!include MdePkg/MdeLibs.dsc.inc
+
+[LibraryClasses.common]
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmPlatformLib|Silicon/Rockchip/RK3588/Library/PlatformLib/PlatformLib.inf
+  AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf
+  CruLib|Silicon/Rockchip/Library/CruLib/CruLib.inf
+
+  DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
+
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+  # UiApp dependencies
+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+
+  #RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+  TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
+
+  # USB Requirements
+  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+
+  # PCIe
+  PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+  #PciHostBridgeLib|Silicon/Rockchip/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+  #PciExpressLib|Silicon/Rockchip/Library/PciExpressLib/PciExpressLib.inf
+  PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+
+
+  # VariableRuntimeDxe Requirements
+  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+  AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+  TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+  VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+
+  AndroidBootImgLib|edk2/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.inf
+
+  RockchipDisplayLib|Silicon/Rockchip/Library/DisplayLib/RockchipDisplayLib.inf
+
+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+  LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf
+
+  # OTP Library
+  OtpLib|Silicon/Rockchip/RK3588/Library/OtpLib/OtpLib.inf
+
+  #
+  # Custom libraries
+  #
+  RockchipPlatformLib|Platform/Radxa/ROCK5A/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+  ResetSystemLib|Silicon/Rockchip/Library/ResetSystemLib/ResetSystemLib.inf
+  PlatformBootManagerLib|Silicon/Rockchip/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+  SerialPortLib|Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf
+  GpioLib|Silicon/Rockchip/RK3588/Library/GpioLib/GpioLib.inf
+  # SCMI Mailbox Transport Layer
+  ArmMtlLib|Silicon/Rockchip/Library/RkMtlLib/RkMtlLib.inf
+
+[LibraryClasses.common.SEC]
+  PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+  ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+  HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
+  MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+  MemoryInitPeiLib|Silicon/Rockchip/RK3588/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
+  PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+  PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+  RockchipPlatformLib|Platform/Radxa/ROCK5A/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+
+[BuildOptions]
+  GCC:*_*_*_PLATFORM_FLAGS = -I$(WORKSPACE)/Silicon/Rockchip/RK3588/Include -I$(WORKSPACE)/Platform/Rockchip/RK3588/Include -I$(WORKSPACE)/Silicon/Rockchip/Include
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+  #  If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+  #  It could be set FALSE to save size.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+
+[PcdsFixedAtBuild.common]
+  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)"
+
+  # System Memory (1GB)
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000
+  gRK3588TokenSpaceGuid.PcdTotalMemorySize|0x200000000
+  
+  # RK3588 CPU profile
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|8
+  gArmPlatformTokenSpaceGuid.PcdClusterCount|1
+
+  # SMBIOS platform config
+  gRockchipTokenSpaceGuid.PcdPlatformName|"ROCK 5 Model A"
+  gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Radxa"
+  gRockchipTokenSpaceGuid.PcdFamilyName|"ROCK 5"
+  gRockchipTokenSpaceGuid.PcdProductUrl|"https://wiki.radxa.com/Rock5/hardware/5a"
+  gRockchipTokenSpaceGuid.PcdMemoryVendorName|"TBD"
+
+  # I2C
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 }
+  gRockchipTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0 }
+  gRockchipTokenSpaceGuid.PcdI2cClockFrequency|198000000
+  gRockchipTokenSpaceGuid.PcdI2cBaudRate|100000
+  gRockchipTokenSpaceGuid.PcdI2cBusCount|1
+  gRockchipTokenSpaceGuid.PcdI2cDemoAddresses|{ 0x51 } #/* RTCYM8563TS 0x51@bus2 */
+  gRockchipTokenSpaceGuid.PcdI2cDemoBuses|{ 0x2 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ 2, 3 } # SCMI_CLK_CPUB01, SCMI_CLK_CPUB23
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorMinVoltages|{ UINT32(550000), UINT32(550000) }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorMaxVoltages|{ UINT32(1050000), UINT32(1050000) }
+
+  ## UART2 - Serial Terminal
+  DEFINE SERIAL_BASE = 0xFEB50000 # UART2
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|$(SERIAL_BASE)
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|1500000
+  gHisiTokenSpaceGuid.PcdSerialPortSendDelay|500000
+  gHisiTokenSpaceGuid.PcdUartClkInHz|24000000
+
+  ## SPI - SPI2 for test
+  gRockchipTokenSpaceGuid.SpiTestBaseAddr|0xFEB20000
+  gRockchipTokenSpaceGuid.SpiRK806BaseAddr|0xFEB20000
+  ## PL031 RealTimeClock
+  #gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0xF8003000
+
+  ## NOR FLASH
+  gRockchipTokenSpaceGuid.FspiBaseAddr|0xFE2B0000
+
+  ## CRU
+  gRockchipTokenSpaceGuid.CruBaseAddr|0xFD7C0000
+
+  #gRockchipTokenSpaceGuid.PcdSpiVariableOffset|0x3C0000
+  #
+  # ARM General Interrupt Controller
+  #
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0xfe600000
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xfe600000
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0xfe680000
+
+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3
+
+  # GUID of the UI app
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+
+  gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
+
+  #
+  # DW SD card controller
+  #
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeBaseAddress|0xfe2c0000
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz|100000000
+  gDesignWareTokenSpaceGuid.PcdDwPermitObsoleteDrivers|TRUE
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeFifoDepth|256
+  #
+  # SDHCI controller
+  #
+  gRockchipTokenSpaceGuid.PcdSdhciDxeBaseAddress|0xfe2e0000
+
+  #
+  # PCIe controller
+  #
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress|0xfe150000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress|0xf5000000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress|0xf0000000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize|0x100000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress|0xf0100000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize|0x10000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress|0xf0200000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize|0xe00000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64|0x901000000 #deduct 0x1000000 ECAM space
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64|0x3f000000
+
+  #
+  # Fastboot
+  #
+  gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbVendorId|0x2207
+  gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbProductId|0x0001
+
+  #
+  # USB2 EHCI + OHCI companion controllers
+  #
+  gRockchipTokenSpaceGuid.PcdEhciBaseAddress|0xfc800000
+  gRockchipTokenSpaceGuid.PcdNumEhciController|2
+  gRockchipTokenSpaceGuid.PcdEhciSize|0x40000
+  gRockchipTokenSpaceGuid.PcdOhciSize|0x40000
+
+  #
+  # DWC3 controller
+  #
+  gRockchipTokenSpaceGuid.PcdDwc3BaseAddresses|{ UINT32(0xfc000000), UINT32(0xfc400000), UINT32(0xfcd00000) }
+  gRockchipTokenSpaceGuid.PcdDwc3Size|0x400000
+
+  #
+  # Android Loader
+  #
+  gRK3588TokenSpaceGuid.PcdAndroidBootDevicePath|L"\\EFI\\BOOT\\GRUBAA64.EFI"
+  gRK3588TokenSpaceGuid.PcdSdBootDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00E023F70000000000)/SD(0x0)"
+  gRK3588TokenSpaceGuid.PcdKernelBootArg|L"earlycon=uart8250,mmio32,0xfeb50000 root=PARTUUID=614e0000-0000 rw rootwait"
+  gEmbeddedTokenSpaceGuid.PcdAndroidBootDevicePath|L"VenHw(100C2CFA-B586-4198-9B4C-1683D195B1DA)/HD(3,GPT,7A3F0000-0000-446A-8000-702F00006273,0x8000,0x20000)"
+
+  # ACPI Enable
+  gRK3588TokenSpaceGuid.AcpiEnable|TRUE
+
+  #
+  # Display
+  #
+  gRockchipTokenSpaceGuid.PcdLcdPixelFormat|0x00000001
+  gRockchipTokenSpaceGuid.PcdEdpId|0x00000000 #edp0
+  #gRockchipTokenSpaceGuid.PcdEdpId|0x00000001 #edp1
+  gRockchipTokenSpaceGuid.PcdHdmiId|0x00000000 #hdmi0
+  #gRockchipTokenSpaceGuid.PcdHdmiId|0x00000001 #hdmi1
+
+  #
+  # CPU Performance default values
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|FALSE
+  gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE)
+  gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_UNCONNECTED)
+  gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3)
+
+  #  BIT0  - Initialization message.<BR>
+  #  BIT1  - Warning message.<BR>
+  #  BIT2  - Load Event message.<BR>
+  #  BIT3  - File System message.<BR>
+  #  BIT4  - Allocate or Free Pool message.<BR>
+  #  BIT5  - Allocate or Free Page message.<BR>
+  #  BIT6  - Information message.<BR>
+  #  BIT7  - Dispatcher message.<BR>
+  #  BIT8  - Variable message.<BR>
+  #  BIT10 - Boot Manager message.<BR>
+  #  BIT12 - BlockIo Driver message.<BR>
+  #  BIT14 - Network Driver message.<BR>
+  #  BIT16 - UNDI Driver message.<BR>
+  #  BIT17 - LoadFile message.<BR>
+  #  BIT19 - Event message.<BR>
+  #  BIT20 - Global Coherency Database changes message.<BR>
+  #  BIT21 - Memory range cachability changes message.<BR>
+  #  BIT22 - Detailed debug message.<BR>
+  #  BIT31 - Error message.<BR>
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0e
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000000
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0f
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x800B0507
+!endif
+# 0x800B05C7
+# Use 0x807B55FF to enable all debug messages
+
+[PcdsDynamicDefault.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x007C0000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x007CF000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x007D0000
+
+  #
+  # Display
+  #
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x780
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x438
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0
+
+[PcdsDynamicHii.common.DEFAULT]
+  #
+  # CPU Performance
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPreset|L"CpuPerf_CPULClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockCustom|L"CpuPerf_CPULClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|1800
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPreset|L"CpuPerf_CPUB01ClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockCustom|L"CpuPerf_CPUB01ClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|2400
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPreset|L"CpuPerf_CPUB23ClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockCustom|L"CpuPerf_CPUB23ClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|2400
+  gRK3588TokenSpaceGuid.PcdCPULClusterVoltageMode|L"CpuPerf_CPULClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0
+  gRK3588TokenSpaceGuid.PcdCPULClusterVoltageCustom|L"CpuPerf_CPULClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|950000
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterVoltageMode|L"CpuPerf_CPUB01ClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterVoltageCustom|L"CpuPerf_CPUB01ClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|1000000
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterVoltageMode|L"CpuPerf_CPUB23ClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterVoltageCustom|L"CpuPerf_CPUB23ClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|1000000
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY
+  #
+  gRK3588TokenSpaceGuid.PcdComboPhy0Mode|L"ComboPhy0Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault
+  gRK3588TokenSpaceGuid.PcdComboPhy1Mode|L"ComboPhy1Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault
+  gRK3588TokenSpaceGuid.PcdComboPhy2Mode|L"ComboPhy2Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault
+  
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+  #
+  # PEI Phase modules
+  #
+  ArmPlatformPkg/PrePi/PeiUniCore.inf
+  MdeModulePkg/Core/Pei/PeiMain.inf
+  MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+
+  #
+  # DXE
+  #
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+  }
+
+  #
+  # Architectural Protocols
+  #
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+  #EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
+  <LibraryClasses>
+    RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
+  }
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  #PCIe
+  #Silicon/Rockchip/Library/PciExpressLib/PciExpressLib.inf
+  #Silicon/Rockchip/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+  #Silicon/Rockchip/Drivers/PciPlatform/PcieInitDxe.inf
+  ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  #MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+  #MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.inf
+
+  MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+  
+  #
+  # Non-volatile FVB support
+  #
+  Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.inf
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+
+  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf
+  #Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
+  Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf
+  Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
+
+  Platform/Radxa/Drivers/LogoDxe/LogoDxe.inf
+
+  #
+  # SCMI Driver
+  #
+  ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf
+
+  #
+  # ACPI Support
+  #
+  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+  Platform/Radxa/ROCK5A/AcpiTables/AcpiTables.inf
+
+  #
+  # Device tree
+  #
+  EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf {
+  <LibraryClasses>
+    DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefault/DxeDtPlatformDtbLoaderLibDefault.inf
+  }
+
+  #
+  # GPIO
+  #
+  Platform/Rockchip/RK3588/RK3588GpioDxe/RK3588GpioDxe.inf
+
+  #
+  # Virtual Keyboard
+  #
+  EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
+
+  # I2C drivers
+  Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.inf
+  MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
+  Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.inf
+  Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.inf
+  Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.inf
+
+  #
+  # MMC/SD
+  #
+  #EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
+  #Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  Silicon/Rockchip/Drivers/MmcDxe/MmcDxe.inf
+  # sdcard is dwemmc, sdhci is for eMMC.
+  Silicon/Rockchip/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  Silicon/Rockchip/Drivers/SdhciHostDxe/SdhciHostDxe.inf
+
+  #
+  # NOR FLASH
+  #
+  Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.inf
+  Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+
+  #
+  # AHCI Support
+  #
+  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+  #
+  # SPI TEST
+  #
+  # Silicon/Rockchip/Library/SpiLib/SpiTest.inf
+
+  #
+  # SMBIOS Support
+  #
+  Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  
+  #
+  # USB Ohci Controller
+  #
+  Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf
+
+  #
+  # USB Ehci Controller
+  #
+  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+
+  #
+  # USB Dwc3 Controller
+  #
+  Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
+  #
+  # USB Xhci Controller
+  #
+  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+
+  #
+  # USB Host Support
+  #
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+  #
+  # USB Mass Storage Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # USB Kb Support
+  #
+  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+  #
+  # USB Mouse Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+
+  #
+  # USB MouseAbsolutePointer Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointerDxe.inf
+
+  #
+  # USB Peripheral Support
+  #
+  EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
+
+  #
+  # Fastboot
+  #
+  EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
+
+  #
+  # Android Boot applications
+  #
+  EmbeddedPkg/Application/AndroidBoot/AndroidBootApp.inf
+
+  #
+  # UEFI Network Stack
+  #
+!include NetworkPkg/Network.dsc.inc
+  #
+  # AX88772 Ethernet Driver
+  #
+  Drivers/ASIX/Bus/Usb/UsbNetworking/Ax88772c/Ax88772c.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+  FatPkg/EnhancedFatDxe/Fat.inf
+
+  #
+  # Bds
+  #
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  MdeModulePkg/Application/UiApp/UiApp.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  ShellPkg/Application/Shell/Shell.inf {
+    <LibraryClasses>
+      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+      NULL|Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.inf
+      NULL|Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf
+      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+      OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
+      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+      gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+  }
+!ifdef $(INCLUDE_TFTP_COMMAND)
+  ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+!endif #$(INCLUDE_TFTP_COMMAND)
+
+  #
+  # Custom Applications and drivers
+  #
+  Silicon/Rockchip/Applications/MaskromReset/maskrom.inf
+
+  # Platform drivers
+  Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf
+
--- a/edk2-platforms/Platform/Radxa/ROCK5A/ROCK5A.fdf
+++ b/edk2-platforms/Platform/Radxa/ROCK5A/ROCK5A.fdf
@@ -0,0 +1,377 @@
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2021-2022, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.NOR_FLASH_IMAGE]
+BaseAddress   = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
+Size          = 0x00800000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize     = 0x00001000
+NumBlocks     = 0x800
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+0x00200000|0x00500000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = BL33_AP_UEFI
+
+# NV_VARIABLE_STORE
+0x007C0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+
+# NV_FTW_WORKING header
+0x007D0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+# NV_FTW_WORKING data
+0x007E0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+BlockSize          = 0x40
+NumBlocks          = 0         # This FV gets compressed so make it just big enough
+FvAlignment        = 8         # FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  APRIORI DXE {
+    INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+  }
+
+  INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+  #
+  # PI DXE Drivers producing Architectural Protocols (EFI Services)
+  #
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  #
+  # Multiple Console IO support
+  #
+  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+
+  INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+
+  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  #
+  # ACPI Support
+  #
+  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+  INF RuleOverride = ACPITABLE Platform/Radxa/ROCK5A/AcpiTables/AcpiTables.inf
+
+  #
+  # Device tree
+  #
+  INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf
+  # FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 {
+  #   SECTION RAW = Platform/Rockchip/DeviceTree/rk3588.dtb
+  # }
+
+  #
+  # GPIO
+  #
+  INF Platform/Rockchip/RK3588/RK3588GpioDxe/RK3588GpioDxe.inf
+  #INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf
+
+  #
+  # I2C
+  #
+  INF Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.inf
+  INF MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
+  # INF Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.inf
+  INF Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.inf
+
+  #
+  # Virtual Keyboard
+  #
+  INF EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
+
+  #
+  # Display Support
+  #
+  
+  INF Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf
+  #INF Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
+  INF Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf
+  INF Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
+  INF Platform/Radxa/Drivers/LogoDxe/LogoDxe.inf
+
+  INF Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf
+
+  #
+  # SMBIOS Support
+  #
+  INF Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+  INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+
+  #
+  # USB Ehci Controller
+  #
+  INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+
+  #
+  # USB Ohci Controller
+  #
+  INF Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf
+
+  #
+  # USB Dwc3 Controller
+  #
+  INF Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
+  #
+  # USB Xhci Controller
+  #
+  INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+
+  #
+  # USB Host Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+  #
+  # USB Mass Storage Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # USB Kb Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+  #
+  # USB Mouse Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+
+  #
+  # USB MouseAbsolutePointer Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointerDxe.inf
+
+  #
+  # USB Peripheral Support
+  #
+  INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
+
+  #
+  # Fastboot
+  #
+  INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
+
+
+  #PCIe
+  #INF Silicon/Rockchip/Drivers/PciPlatform/PcieInitDxe.inf
+
+  # Required by PCI
+  INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
+  # PCI Support
+  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  #INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+  #INF MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.inf
+
+  #INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+  INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+  #
+  # Android Boot applications
+  #
+  INF EmbeddedPkg/Application/AndroidBoot/AndroidBootApp.inf
+
+  #
+  # UEFI Network Stack
+  #
+!include NetworkPkg/Network.fdf.inc
+
+  #
+  # AX88772 Ethernet Driver for Apple Ethernet Adapter
+  #
+  INF Drivers/ASIX/Bus/Usb/UsbNetworking/Ax88772c/Ax88772c.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF FatPkg/EnhancedFatDxe/Fat.inf
+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  #
+  # Multimedia Card Interface
+  #
+  # INF Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  INF Silicon/Rockchip/Drivers/MmcDxe/MmcDxe.inf
+  # sdcard is dwemmc, sdhci is for eMMC.
+  INF Silicon/Rockchip/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  
+  #
+  # DWC SDHCI (for eMMC slot)
+  #
+  INF Silicon/Rockchip/Drivers/SdhciHostDxe/SdhciHostDxe.inf
+
+  #
+  # AHCI Support
+  #
+  INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+  #
+  # SPI NOR FLASH
+  #
+  INF Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.inf
+
+  #
+  # Non-volatile FVB support
+  #
+  INF Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.inf
+  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+
+  # Human interface
+  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  # Custom
+  INF Silicon/Rockchip/Applications/MaskromReset/maskrom.inf
+  
+  # SCMI Driver
+  INF ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf
+
+  #
+  # UEFI applications
+  #
+  INF ShellPkg/Application/Shell/Shell.inf
+!ifdef $(INCLUDE_TFTP_COMMAND)
+  INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+!endif #$(INCLUDE_TFTP_COMMAND)
+  #INF Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+
+  #
+  # Bds
+  #
+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+[FV.BL33_AP_UEFI]
+FvAlignment        = 8
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+
+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FVMAIN
+    }
+  }
+
+!include Silicon/Rockchip/Rockchip.fdf.inc
+
+!ifdef $(ROCKCHIP_ACPIEN)
+[Rule.Common.DXE_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX	 DXE_DEPEX		Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32	 PE32			$(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI		 STRING="$(MODULE_NAME)" Optional
+    RAW 	 ACPI  Optional 	      |.acpi
+    RAW 	 ASL   Optional 	      |.aml
+  }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW ACPI		   |.acpi
+    RAW ASL		   |.aml
+  }
+!endif
--- a/edk2-platforms/Platform/Radxa/ROCK5B/AcpiTables/AcpiTables.inf
+++ b/edk2-platforms/Platform/Radxa/ROCK5B/AcpiTables/AcpiTables.inf
@@ -15,6 +15,7 @@
  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
  MODULE_TYPE                    = USER_DEFINED
  VERSION_STRING                 = 1.0
+  RK_COMMON_ACPI_DIR             = Silicon/Rockchip/RK3588/AcpiTables

 #
 # The following information is for reference only and not required by the build tools.
@@ -23,15 +24,14 @@
 #

 [Sources]
-  AcpiTables.h
-  Madt.aslc
-  Fadt.aslc
-  Gtdt.aslc
  Dsdt.asl
-  Spcr.aslc
-  Mcfg.aslc
-  RK3588PcieIort.aslc
-  Dbg2.aslc
+  $(RK_COMMON_ACPI_DIR)/Madt.aslc
+  $(RK_COMMON_ACPI_DIR)/Fadt.aslc
+  $(RK_COMMON_ACPI_DIR)/Gtdt.aslc
+  $(RK_COMMON_ACPI_DIR)/Spcr.aslc
+  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
+  $(RK_COMMON_ACPI_DIR)/RK3588PcieIort.aslc
+  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc

 [Packages]
  ArmPkg/ArmPkg.dec
--- a/edk2-platforms/Platform/Radxa/ROCK5B/AcpiTables/Dsdt.asl
+++ b/edk2-platforms/Platform/Radxa/ROCK5B/AcpiTables/Dsdt.asl
@@ -17,88 +17,13 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
 {
  Scope (\_SB_)
  {
-    Device (CPU0)
-    {
-      Name (_HID, "ACPI0007")
-      Name (_UID, 0x0)
-      Method (_STA)
-      {
-        Return (0xf)
-      }
-    }
-    Device (CPU1)
-    {
-      Name (_HID, "ACPI0007")
-      Name (_UID, 0x1)
-      Method (_STA)
-      {
-        Return (0xf)
-      }
-    }
-
-    Device (CPU2)
-    {
-      Name (_HID, "ACPI0007")
-      Name (_UID, 0x2)
-      Method (_STA)
-      {
-        Return (0xf)
-      }
-    }
-
-    Device (CPU3)
-    {
-      Name (_HID, "ACPI0007")
-      Name (_UID, 0x3)
-      Method (_STA)
-      {
-        Return (0xf)
-      }
-    }
-
-    Device (CPU4)
-    {
-      Name (_HID, "ACPI0007")
-      Name (_UID, 0x4)
-      Method (_STA)
-      {
-        Return (0xf)
-      }
-    }
-
-    Device (CPU5)
-    {
-      Name (_HID, "ACPI0007")
-      Name (_UID, 0x5)
-      Method (_STA)
-      {
-        Return (0xf)
-      }
-    }
-
-    Device (CPU6)
-    {
-      Name (_HID, "ACPI0007")
-      Name (_UID, 0x6)
-      Method (_STA)
-      {
-        Return (0xf)
-      }
-    }
-
-    Device (CPU7)
-    {
-      Name (_HID, "ACPI0007")
-      Name (_UID, 0x7)
-      Method (_STA)
-      {
-        Return (0xf)
-      }
-    }
+    include ("Cpu.asl")

    include ("Pcie.asl")
-    // include ("Sata.asl")
-    // include ("Emmc.asl")
+    include ("Sata1.asl")
+    include ("Sata2.asl")
+    include ("Emmc.asl")
+    include ("Sdhc.asl")
    // include ("Gmac.asl")
    // include ("Gpio.asl")
    // include ("I2c.asl")
@@ -108,6 +33,8 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
    // won't work on Windows, will trigger bugcheck by usbehci
    // include ("Usb2.asl")

-    include ("Usb3.asl")
+    include ("Usb3Host0.asl")
+    include ("Usb3Host1.asl")
+    include ("Usb3Host2.asl")
  }
 }
--- a/edk2-platforms/Platform/Radxa/ROCK5B/AcpiTables/Emmc.asl
+++ b/edk2-platforms/Platform/Radxa/ROCK5B/AcpiTables/Emmc.asl
@@ -1,76 +0,0 @@
-/** @file
- *
- *  Copyright (c) 2021, ARM Limited. All rights reserved.
- *
- *  SPDX-License-Identifier: BSD-2-Clause-Patent
- *
- **/
-#include "AcpiTables.h"
-
-
-  Device (SDC3) {
-    Name (_HID, "PRP0001")
-    Name (_UID, 3)
-    Name (_CCA, 0)
-
-    Method (_CRS, 0x0, Serialized) {
-      Name (RBUF, ResourceTemplate() {
-        Memory32Fixed (ReadWrite, 0xfe2e0000, 0x1000)
-        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 237 }
-      })
-      Return (RBUF)
-    }
-    Name (_DSD, Package () {
-      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-      Package () {
-        Package (2) { "compatible", "rockchip,rk3588-dwcmshc" },
-        Package () { "max-frequency", 200000000 },
-        Package () { "bus-width", 8 },
-        Package () { "no-sd", 0x1 },
-        Package () { "no-sdio", 0x1  },
-        Package () { "mmc-hs400-1_8v", 0x1  },
-        Package () { "mmc-hs400-enhanced-strobe", 0x1  },
-        Package () { "non-removable", 0x1  },
-      }
-    })
-
-    OperationRegion(EMMC, SystemMemory, 0xFD7C0434, 0x4)
-      Field(EMMC, DWordAcc, Lock, WriteAsZeros) {
-      PLLE, 32,
-    }
-
-    Method(SCLK, 1, Serialized) {
-      If (Arg0 <= 400000)
-      {
-        Store (0xFF00BF00, PLLE)
-      }
-      ElseIF (Arg0 <= 50000000)
-      {
-        Store (0xFF008000, PLLE)
-      }
-      Else
-      {
-        Store (0xFF000600, PLLE)
-      }
-    }
-
-    Method(_PS3) {
-
-    }
-
-    Method(_PS2) {
-      Store (0xFF00BF00, PLLE)
-    }
-
-    Method(_PS1) {
-      Store (0xFF008000, PLLE)
-    }
-
-    Method(_PS0) {
-      Store (0xFF000600, PLLE)
-    }
-
-    Method(_PSC) {
-      Return(0x01)
-    }
-  }
--- a/edk2-platforms/Platform/Radxa/ROCK5B/AcpiTables/Sata.asl
+++ b/edk2-platforms/Platform/Radxa/ROCK5B/AcpiTables/Sata.asl
@@ -1,68 +0,0 @@
-/** @file
- *
- *  Copyright (c) 2021, ARM Limited. All rights reserved.
- *
- *  SPDX-License-Identifier: BSD-2-Clause-Patent
- *
- **/
-#include "AcpiTables.h"
-
-Device (ATA0) {
-  Name (_HID, "PRP0001")
-  Name (_UID, 3)
-  Name (_CCA, 0)
-
-  Method (_CRS, 0x0, Serialized) {
-    Name (RBUF, ResourceTemplate() {
-      Memory32Fixed (ReadWrite, 0xfe210000, 0x1000)
-      Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 305 }
-    })
-    Return (RBUF)
-  }
-  Name (_DSD, Package () {
-    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-    Package () {
-      Package (2) { "compatible", "rockchip,rk-ahci" },
-    }
-  })
-}
-
-Device (ATA1) {
-  Name (_HID, "PRP0001")
-  Name (_UID, 3)
-  Name (_CCA, 0)
-
-  Method (_CRS, 0x0, Serialized) {
-    Name (RBUF, ResourceTemplate() {
-      Memory32Fixed (ReadWrite, 0xfe220000, 0x1000)
-      Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 306 }
-    })
-    Return (RBUF)
-  }
-  Name (_DSD, Package () {
-    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-    Package () {
-      Package (2) { "compatible", "rockchip,rk-ahci" },
-    }
-  })
-}
-
-Device (ATA2) {
-  Name (_HID, "PRP0001")
-  Name (_UID, 3)
-  Name (_CCA, 0)
-
-  Method (_CRS, 0x0, Serialized) {
-    Name (RBUF, ResourceTemplate() {
-      Memory32Fixed (ReadWrite, 0xfe230000, 0x1000)
-      Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 307 }
-    })
-    Return (RBUF)
-  }
-  Name (_DSD, Package () {
-    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-    Package () {
-      Package (2) { "compatible", "rockchip,rk-ahci" },
-    }
-  })
-}
--- a/edk2-platforms/Platform/Radxa/ROCK5B/AcpiTables/Usb3.asl
+++ b/edk2-platforms/Platform/Radxa/ROCK5B/AcpiTables/Usb3.asl
@@ -1,54 +0,0 @@
-/** @file
-*  DWC3 XHCI Controllers.
-*
-*  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
-*
-*  SPDX-License-Identifier: BSD-2-Clause-Patent
-**/
-
-#include "AcpiTables.h"
-
-Device (XHC0) {
-    Name (_HID, "PNP0D10")
-    Name (_UID, Zero)
-    Name (_CCA, Zero)
-
-    Method (_CRS, 0x0, Serialized) {
-        Name (RBUF, ResourceTemplate() {
-            Memory32Fixed (ReadWrite, 0xfc000000, 0x400000)
-            Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 252 }
-        })
-        Return (RBUF)
-    }   
-}
-
-Device (XHC1) {
-    Name (_HID, "PNP0D10")
-    Name (_UID, One)
-    Name (_CCA, Zero)
-
-    Method (_CRS, 0x0, Serialized) {
-        Name (RBUF, ResourceTemplate() {
-            Memory32Fixed (ReadWrite, 0xfc400000, 0x400000)
-            Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 253 }
-        })
-        Return (RBUF)
-    }   
-}
-
-// This only supports USB 3.0 devices.
-// USB2 DP / DM are connected to one of the EHCI controllers instead (EHC1 on ROCK 5B).
-
-Device (XHC2) {
-    Name (_HID, "PNP0D10")
-    Name (_UID, 2)
-    Name (_CCA, Zero)
-
-    Method (_CRS, 0x0, Serialized) {
-        Name (RBUF, ResourceTemplate() {
-            Memory32Fixed (ReadWrite, 0xfcd00000, 0x400000)
-            Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 254 }
-        })
-        Return (RBUF)
-    }   
-}
--- a/edk2-platforms/Platform/Radxa/ROCK5B/Drivers/RK3588Dxe_rock5b/RK3588Dxe.c
+++ b/edk2-platforms/Platform/Radxa/ROCK5B/Drivers/RK3588Dxe_rock5b/RK3588Dxe.c
@@ -1,882 +0,0 @@
-/** @file
-*
-*  Copyright (c) 2021, Rockchip Limited. All rights reserved.
-*
-*  SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-#include <Uefi.h>
-#include <Library/ArmLib.h>
-#include <Protocol/Cpu.h>
-#include <Library/CacheMaintenanceLib.h>
-#include <Library/DebugLib.h>
-#include <Library/DevicePathLib.h>
-#include <Library/IoLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/PcdLib.h>
-#include <Library/UefiBootManagerLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiLib.h>
-#include <Library/RK806.h>
-#include <Library/AcpiLib.h>
-#include <Protocol/DevicePath.h>
-#include <Protocol/DevicePathFromText.h>
-#include <Protocol/EmbeddedGpio.h>
-#include <Protocol/LoadedImage.h>
-#include <Protocol/PlatformBootManager.h>
-#include <Protocol/PlatformVirtualKeyboard.h>
-#include <Protocol/AndroidBootImg.h>
-#include <Library/DxeServicesTableLib.h>
-#include <Library/NonDiscoverableDeviceRegistrationLib.h>
-#include <Protocol/NonDiscoverableDevice.h>
-#include <Protocol/ArmScmi.h>
-#include <Protocol/ArmScmiClockProtocol.h>
-
-#include <Soc.h>
-#include <Library/CruLib.h>
-#include <RK3588RegsPeri.h>
-#include "RK3588Dxe.h"
-
-#define SCMI_CLK_CPUL			0
-#define SCMI_CLK_CPUB01			2
-#define SCMI_CLK_CPUB23			3
-
-#define CP_UNCONNECTED    0x0
-#define  CP_PCIE          0x01
-#define  CP_SATA          0x10
-#define  CP_USB3          0x20
-
-STATIC
-EFI_STATUS
-BoardInitSetCpuSpeed (
-  VOID
-  )
-{
-  EFI_STATUS             Status;
-  SCMI_CLOCK_PROTOCOL    *ClockProtocol;
-  EFI_GUID               ClockProtocolGuid = ARM_SCMI_CLOCK_PROTOCOL_GUID;
-  UINT64                 CpuRate;
-  UINT32                 ClockId;
-  UINT32                 ClockProtocolVersion;
-  BOOLEAN                Enabled;
-  CHAR8                  ClockName[SCMI_MAX_STR_LEN];
-  UINT32                 TotalRates = 0;
-  UINT32                 ClockRateSize;
-  SCMI_CLOCK_RATE        *ClockRate;
-  SCMI_CLOCK_RATE_FORMAT ClockRateFormat;
-  UINT32                 ClockIds[3]= {SCMI_CLK_CPUL, SCMI_CLK_CPUB01, SCMI_CLK_CPUB23};
-
-  Status = gBS->LocateProtocol (
-                  &ClockProtocolGuid,
-                  NULL,
-                  (VOID**)&ClockProtocol
-                  );
-  if (EFI_ERROR (Status)) {
-    ASSERT_EFI_ERROR (Status);
-    return Status;
-  }
-
-  Status = ClockProtocol->GetVersion (ClockProtocol, &ClockProtocolVersion);
-  if (EFI_ERROR (Status)) {
-    ASSERT_EFI_ERROR (Status);
-    return Status;
-  }
-  DEBUG ((DEBUG_ERROR, "SCMI clock management protocol version = %x\n",
-    ClockProtocolVersion));
-
-  ClockId = 0;
-
-  for (int i=0 ; i<3; i=i+1 )
-  {
-    ClockId = ClockIds[i];
-    Status = ClockProtocol->GetClockAttributes (
-                              ClockProtocol,
-                              ClockId,
-                              &Enabled,
-                              ClockName
-                              );
-    if (EFI_ERROR (Status)) {
-      ASSERT_EFI_ERROR (Status);
-      return Status;
-    }
-
-    Status = ClockProtocol->RateGet (ClockProtocol, ClockId, &CpuRate);
-    if (EFI_ERROR (Status)) {
-      ASSERT_EFI_ERROR (Status);
-      return Status;
-    }
-
-    DEBUG ((EFI_D_WARN, "SCMI: %a: Current rate is %uHz\n", ClockName, CpuRate));
-
-    TotalRates = 0;
-    ClockRateSize = 0;
-    Status = ClockProtocol->DescribeRates (
-                              ClockProtocol,
-                              ClockId,
-                              &ClockRateFormat,
-                              &TotalRates,
-                              &ClockRateSize,
-                              ClockRate
-                              );
-    if (EFI_ERROR (Status) && Status != EFI_BUFFER_TOO_SMALL) {
-      ASSERT_EFI_ERROR (Status);
-      return Status;
-    }
-    ASSERT (Status == EFI_BUFFER_TOO_SMALL);
-    ASSERT (TotalRates > 0);
-    ASSERT (ClockRateFormat == ScmiClockRateFormatDiscrete);
-    if (Status != EFI_BUFFER_TOO_SMALL ||
-        TotalRates == 0 ||
-        ClockRateFormat != ScmiClockRateFormatDiscrete) {
-      return EFI_DEVICE_ERROR;
-    }
-    
-    ClockRateSize = sizeof (*ClockRate) * TotalRates;
-    ClockRate = AllocatePool (ClockRateSize);
-    ASSERT (ClockRate != NULL);
-    if (ClockRate == NULL) {
-      return EFI_OUT_OF_RESOURCES;
-    }
-    Status = ClockProtocol->DescribeRates (
-                              ClockProtocol,
-                              ClockId,
-                              &ClockRateFormat,
-                              &TotalRates,
-                              &ClockRateSize,
-                              ClockRate
-                              );
-    if (EFI_ERROR (Status)) {
-      ASSERT_EFI_ERROR (Status);
-      FreePool (ClockRate);
-      return Status;
-    }
-
-    CpuRate = ClockRate[TotalRates - 1].DiscreteRate.Rate;
-    FreePool (ClockRate);
-
-    DEBUG ((EFI_D_WARN, "SCMI: %a: New rate is %uHz\n", ClockName, CpuRate));
-
-    Status = ClockProtocol->RateSet (
-                              ClockProtocol,
-                              ClockId,
-                              CpuRate
-                              );
-    if (EFI_ERROR (Status)) {
-      ASSERT_EFI_ERROR (Status);
-      return Status;
-    }
-
-    Status = ClockProtocol->RateGet (ClockProtocol, ClockId, &CpuRate);
-    if (EFI_ERROR (Status)) {
-      ASSERT_EFI_ERROR (Status);
-      return Status;
-    }
-
-    DEBUG ((EFI_D_WARN, "SCMI: %a: Current rate is %uHz\n", ClockName, CpuRate));
-  }
-
-  return EFI_SUCCESS;
-}
-
-STATIC
-VOID
-UartInit (
-  IN VOID
-  )
-{
-  //UINT32     Val;
-
-  DEBUG((EFI_D_WARN, "RK3588InitPeripherals: UartInit()\n"));
-  /* make UART1 out of reset */
-  //MmioWrite32 (CRU_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART1);
-  //MmioWrite32 (CRU_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART1);
-  /* make UART2 out of reset */
-  //MmioWrite32 (CRU_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART2);
-  //MmioWrite32 (CRU_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART2);
-  /* make UART3 out of reset */
-  //MmioWrite32 (CRU_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART3);
-  //MmioWrite32 (CRU_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART3);
-  /* make UART4 out of reset */
-  //MmioWrite32 (CRU_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART4);
-  //MmioWrite32 (CRU_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART4);
-
-  /* make DW_MMC2 out of reset */
-  //MmioWrite32 (CRU_BASE + SC_PERIPH_RSTDIS0, PERIPH_RST0_MMC2);
-
-  /* enable clock for BT/WIFI */
-  //Val = MmioRead32 (PMUSSI_ONOFF8_REG) | PMUSSI_ONOFF8_EN_32KB;
-  //MmioWrite32 (PMUSSI_ONOFF8_REG, Val);
-}
-
-STATIC EMBEDDED_GPIO        *mGpio;
-
-STATIC
-VOID
-MtcmosInit (
-  IN VOID
-  )
-{
-  //UINT32     Data;
-
-  DEBUG((EFI_D_WARN, "RK3588InitPeripherals: MtcmosInit()\n"));
-  /* enable MTCMOS for GPU */
-  //MmioWrite32 (AO_CTRL_BASE + SC_PW_MTCMOS_EN0, PW_EN0_G3D);
-  //do {
-  //  Data = MmioRead32 (AO_CTRL_BASE + SC_PW_MTCMOS_ACK_STAT0);
-  //} while ((Data & PW_EN0_G3D) == 0);
-}
-
-STATIC
-VOID
-GmacIomuxInit (
-  IN VOID
-  )
-{
-  DEBUG((EFI_D_WARN, "RK3588InitPeripherals: GmacIomuxInit()\n"));
-  GmacIomux(0);
-}
-
-static struct regulator_init_data rk806_master[] = {
-	RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
-	RK8XX_VOLTAGE_INIT(MASTER_BUCK2, 750000),
-	RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
-	RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
-	RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 750000),
-	RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
-	RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
-	RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 750000),
-	RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1100000),
-
-	RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
-	RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 900000),
-	RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
-	RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 750000),
-	RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 850000),
-
-	RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
-	RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
-	RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1800000),
-	RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
-	RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 1800000),
-	RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
-};
-
-static struct regulator_init_data rk806_slaver[] = {
-	RK8XX_VOLTAGE_INIT(SLAVER_BUCK1, 750000),
-	RK8XX_VOLTAGE_INIT(SLAVER_BUCK2, 750000),
-	RK8XX_VOLTAGE_INIT(SLAVER_BUCK3, 750000),
-	RK8XX_VOLTAGE_INIT(SLAVER_BUCK4, 3300000),
-	RK8XX_VOLTAGE_INIT(SLAVER_BUCK5, 750000),
-	RK8XX_VOLTAGE_INIT(SLAVER_BUCK6, 750000),
-	RK8XX_VOLTAGE_INIT(SLAVER_BUCK7, 1800000),
-	RK8XX_VOLTAGE_INIT(SLAVER_BUCK8, 750000),
-	RK8XX_VOLTAGE_INIT(SLAVER_BUCK10, 850000),
-
-	RK8XX_VOLTAGE_INIT(SLAVER_NLDO1, 750000),
-	RK8XX_VOLTAGE_INIT(SLAVER_NLDO2, 850000),
-	RK8XX_VOLTAGE_INIT(SLAVER_NLDO3, 850000),
-	RK8XX_VOLTAGE_INIT(SLAVER_NLDO4, 1200000),
-	RK8XX_VOLTAGE_INIT(SLAVER_NLDO5, 1200000),
-
-	RK8XX_VOLTAGE_INIT(SLAVER_PLDO1, 1800000),
-	RK8XX_VOLTAGE_INIT(SLAVER_PLDO2, 1800000),
-	RK8XX_VOLTAGE_INIT(SLAVER_PLDO3, 1800000),
-	RK8XX_VOLTAGE_INIT(SLAVER_PLDO4, 3300000),
-	RK8XX_VOLTAGE_INIT(SLAVER_PLDO5, 2800000),
-	RK8XX_VOLTAGE_INIT(SLAVER_PLDO6, 1800000),
-};
-
-static UINTN ComPhyReg[3][2] = {
-  {0xFEE00000, 0xFD5BC000},
-  {0xFEE10000, 0xFD5C0000},
-  {0xFEE20000, 0xFD5C4000},
-};
-
-static UINTN AhciReg[3] = {
-  0xFE210000,
-  0xFE220000,
-  0xFE230000,
-};
-
-UINTN
-EFIAPI
-InitComPhyConfig(
-  UINTN PhyBaseAddr,
-  UINTN PhpBaseAddr,
-  UINT8 PhyMode
-)
-{
-  UINT32 val;
-  DEBUG ((DEBUG_ERROR, "%a reg=%x %x mode = %d\n", __func__, PhyBaseAddr, PhpBaseAddr, PhyMode));
-
-  switch (PhyMode) {
-  case CP_PCIE:
-    MmioWrite32(PhpBaseAddr + 0x0, 0xFFFF1000);
-    MmioWrite32(PhpBaseAddr + 0x4, 0xFFFF4000);
-    MmioWrite32(PhpBaseAddr + 0x8, 0xFFFF0101);
-    MmioWrite32(PhpBaseAddr + 0xc, 0xFFFF0200);
-
-    /* gate_tx_pck_sel length select work for L1SS */
-    MmioWrite32(PhyBaseAddr + 0x74, 0xc0);
-
-    /* PLL KVCO tuning fine */
-    val = MmioRead32(PhyBaseAddr + (0x20 << 2));
-    val &= ~(0x7 << 2);
-    val |= 0x4 << 2;
-    MmioWrite32(PhyBaseAddr + (0x20 << 2), val);
-
-    /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
-    MmioWrite32(PhyBaseAddr + (0x1b << 2), 0x4c);
-
-    /* Set up su_trim: T3 */
-    MmioWrite32(PhyBaseAddr + (0xa << 2), 0xb0);
-    MmioWrite32(PhyBaseAddr + (0xb << 2), 0x47);
-    MmioWrite32(PhyBaseAddr + (0xd << 2), 0x57);
-
-    break;
-
-  case CP_SATA:
-    MmioWrite32(PhyBaseAddr + 0x38, 0x41);
-    MmioWrite32(PhyBaseAddr + 0x18, 0x8F);
-    MmioWrite32(PhyBaseAddr + 0x7C, 0x50);
-    MmioWrite32(PhyBaseAddr + 0x24, 0x07);
-
-    MmioWrite32(PhpBaseAddr + 0x0, 0xFFFF0129);
-    MmioWrite32(PhpBaseAddr + 0x4, 0xFFFF4000);
-    MmioWrite32(PhpBaseAddr + 0x8, 0xFFFF80c1);
-    MmioWrite32(PhpBaseAddr + 0xc, 0xFFFF0407);
-    break;
-
-  case CP_USB3:
-    /* Set SSC downward spread spectrum */
-    val = MmioRead32(PhyBaseAddr + (0x1f << 2));
-    val &= ~(0x3 << 4);
-    val |= 0x01 << 4;
-    MmioWrite32(PhyBaseAddr + 0x7c, val);
-
-    /* Enable adaptive CTLE for USB3.0 Rx */
-    val = MmioRead32(PhyBaseAddr + (0x0e << 2));
-    val &= ~(0x1 << 0);
-    val |= 0x01;
-    MmioWrite32(PhyBaseAddr + (0x0e << 2), val);
-
-    /* Set PLL KVCO fine tuning signals */
-    val = MmioRead32(PhyBaseAddr + (0x20 << 2));
-    val &= ~(0x7 << 2);
-    val |= 0x2 << 2;
-    MmioWrite32(PhyBaseAddr + (0x20 << 2), val);
-
-    /* Set PLL LPF R1 to su_trim[10:7]=1001 */
-    MmioWrite32(PhyBaseAddr + (0xb << 2), 0x4);
-
-    /* Set PLL input clock divider 1/2 */
-    val = MmioRead32(PhyBaseAddr + (0x5 << 2));
-    val &= ~(0x3 << 6);
-    val |= 0x1 << 6;
-    MmioWrite32(PhyBaseAddr + (0x5 << 2), val);
-
-    /* Set PLL loop divider */
-    MmioWrite32(PhyBaseAddr + (0x11 << 2), 0x32);
-
-    /* Set PLL KVCO to min and set PLL charge pump current to max */
-    MmioWrite32(PhyBaseAddr + (0xa << 2), 0xf0);
-
-    /* Set Rx squelch input filler bandwidth */
-    MmioWrite32(PhyBaseAddr + (0x14 << 2), 0x0d);
-
-    /* Set txcomp_sel[15] to 1b'0 */
-    MmioWrite32(PhpBaseAddr + 0x8, 0x80000000);
-    /* Set txelec_sel[12] to 1b'0 */
-    MmioWrite32(PhpBaseAddr + 0x8, 0x10000000);
-    /* Set usb_mode_set[5:0]=6b'000100 */
-    MmioWrite32(PhpBaseAddr + 0x0, 0x003F0004);
-
-    /* phy_clk_sel to 100MHz */
-    MmioWrite32(PhpBaseAddr + 0x4, 0x60004000);
-    break;
-
-  default:
-    break;
-  }
-
-  return RETURN_SUCCESS;
-}
-
-UINTN
-EFIAPI
-ComboPhyInit(void)
-{
-  UINT32 data;
-  UINT8 *ComPhyMode;
-  UINTN ComPhyDeviceTableSize, Index;
-
-  ComPhyMode = PcdGetPtr (PcdComboPhyMode);
-  if (ComPhyMode == NULL)
-    return RETURN_NOT_FOUND;
-
-  ComPhyDeviceTableSize = PcdGetSize (PcdComboPhyMode);
-
-  /* config phy clock to 100Mhz */
-  HAL_CRU_ClkSetFreq(PLL_PPLL, 100 * 1000000);
-  HAL_CRU_ClkSetFreq(CLK_REF_PIPE_PHY0, 100 * 1000000);
-  HAL_CRU_ClkSetFreq(CLK_REF_PIPE_PHY1, 100 * 1000000);
-  HAL_CRU_ClkSetFreq(CLK_REF_PIPE_PHY2, 100 * 1000000);
-
-  /* Initialize echo combo phy */
-  for (Index = 0; Index < ComPhyDeviceTableSize; Index++) {
-    InitComPhyConfig (ComPhyReg[Index][0], ComPhyReg[Index][1], ComPhyMode[Index]);
-    if (ComPhyMode[Index] == CP_SATA) {
-		RegisterNonDiscoverableMmioDevice (
-           NonDiscoverableDeviceTypeAhci,
-           NonDiscoverableDeviceDmaTypeCoherent,
-           NULL,
-           NULL,
-           1,
-           AhciReg[Index], SIZE_4KB);
-    }
-  }
-  /* Initialize SATA */
-  data = MmioRead32(0xfe210000 + 0x118);
-  MmioWrite32(0xfe210000 + 0x118, data | 1 << 22); /* FBSCP */
-  MmioWrite32(0xfe210000 + 0xc, 1); /* HOST_PORTS_IMPL */
-
-  data = MmioRead32(0xfe220000 + 0x118);
-  MmioWrite32(0xfe220000 + 0x118, data | 1 << 22); /* FBSCP */
-  MmioWrite32(0xfe220000 + 0xc, 1); /* HOST_PORTS_IMPL */
-
-  data = MmioRead32(0xfe230000 + 0x118);
-  MmioWrite32(0xfe230000 + 0x118, data | 1 << 22); /* FBSCP */
-  MmioWrite32(0xfe230000 + 0xc, 1); /* HOST_PORTS_IMPL */
-
-  MmioWrite32(0xfd5b0000 + 0x0, 0x07E00440);
-  MmioWrite32(0xfd5b0000 + 0x4, 0x00070002);
-
-  /* reset deassert */
-  MmioWrite32(0xfd7c0000 + 0x0b34, 0x01c00000);
-
-  for (Index = 0; Index < ComPhyDeviceTableSize; Index++)
-    if (ComPhyMode[Index] == CP_USB3)
-      gBS->Stall(2000);
-
-  return RETURN_SUCCESS;
-}
-
-EFI_STATUS
-RK3588InitPeripherals (
-  IN VOID
-  )
-{
-  INT32 i;
-  //UINT32     Data, Bits;
-
-  DEBUG((EFI_D_WARN, "RK3588InitPeripherals: Entry\n"));
-
-  /* make I2C0/I2C1/I2C2/SPI0 out of reset */
-  //Bits = PERIPH_RST3_I2C0 | PERIPH_RST3_I2C1 | PERIPH_RST3_I2C2 | PERIPH_RST3_SSP;
-  //MmioWrite32 (CRU_BASE + SC_PERIPH_RSTDIS3, Bits);
-
-  //do {
-  //  Data = MmioRead32 (CRU_BASE + SC_PERIPH_RSTSTAT3);
-  //} while (Data & Bits);
-
-  // UartInit ();
-
-  /* MTCMOS -- Multi-threshold CMOS */
-  // MtcmosInit ();
-
-  /* Set DETECT_J15_FASTBOOT (GPIO24) pin as GPIO function */
-  //MmioWrite32 (IOCG_084_REG, 0);        /* configure GPIO24 as nopull */
-  //MmioWrite32 (IOMG_080_REG, 0);        /* configure GPIO24 as GPIO */
-  // RK806Init();
-
-  // for (i = 0; i < ARRAY_SIZE(rk806_master); i++)
-  //   RK806RegulatorInit(rk806_master[i]);
-  // for (i = 0; i < ARRAY_SIZE(rk806_slaver); i++)
-  //   RK806RegulatorInit(rk806_slaver[i]);
-
-  ComboPhyInit();
-
-  // GmacIomuxInit();
-
-  return EFI_SUCCESS;
-}
-
-STATIC
-EFI_STATUS
-CreatePlatformBootOptionFromPath (
-  IN     CHAR16                          *PathStr,
-  IN     CHAR16                          *Description,
-  IN OUT EFI_BOOT_MANAGER_LOAD_OPTION    *BootOption
-  )
-{
-  EFI_STATUS                   Status;
-  EFI_DEVICE_PATH              *DevicePath;
-
-  DevicePath = (EFI_DEVICE_PATH *)ConvertTextToDevicePath (PathStr);
-  ASSERT (DevicePath != NULL);
-  Status = EfiBootManagerInitializeLoadOption (
-             BootOption,
-             LoadOptionNumberUnassigned,
-             LoadOptionTypeBoot,
-             LOAD_OPTION_ACTIVE,
-             Description,
-             DevicePath,
-             NULL,
-             0
-             );
-  FreePool (DevicePath);
-  return Status;
-}
-
-STATIC
-EFI_STATUS
-CreatePlatformBootOptionFromGuid (
-  IN     EFI_GUID                        *FileGuid,
-  IN     CHAR16                          *Description,
-  IN OUT EFI_BOOT_MANAGER_LOAD_OPTION    *BootOption
-  )
-{
-  EFI_STATUS                             Status;
-  EFI_DEVICE_PATH                        *DevicePath;
-  EFI_DEVICE_PATH                        *TempDevicePath;
-  EFI_LOADED_IMAGE_PROTOCOL              *LoadedImage;
-  MEDIA_FW_VOL_FILEPATH_DEVICE_PATH      FileNode;
-
-  Status = gBS->HandleProtocol (
-                  gImageHandle,
-                  &gEfiLoadedImageProtocolGuid,
-                  (VOID **) &LoadedImage
-                  );
-  ASSERT_EFI_ERROR (Status);
-  EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid);
-  TempDevicePath = DevicePathFromHandle (LoadedImage->DeviceHandle);
-  ASSERT (TempDevicePath != NULL);
-  DevicePath = AppendDevicePathNode (
-                 TempDevicePath,
-                 (EFI_DEVICE_PATH_PROTOCOL *) &FileNode
-                 );
-  ASSERT (DevicePath != NULL);
-  Status = EfiBootManagerInitializeLoadOption (
-             BootOption,
-             LoadOptionNumberUnassigned,
-             LoadOptionTypeBoot,
-             LOAD_OPTION_ACTIVE,
-             Description,
-             DevicePath,
-             NULL,
-             0
-             );
-  FreePool (DevicePath);
-  return Status;
-}
-
-STATIC
-EFI_STATUS
-GetPlatformBootOptionsAndKeys (
-  OUT UINTN                              *BootCount,
-  OUT EFI_BOOT_MANAGER_LOAD_OPTION       **BootOptions,
-  OUT EFI_INPUT_KEY                      **BootKeys
-  )
-{
-  EFI_GUID                               *FileGuid;
-  CHAR16                                 *PathStr;
-  EFI_STATUS                             Status;
-  UINTN                                  Size;
-
-  Size = sizeof (EFI_BOOT_MANAGER_LOAD_OPTION) * HIKEY_BOOT_OPTION_NUM;
-  *BootOptions = (EFI_BOOT_MANAGER_LOAD_OPTION *)AllocateZeroPool (Size);
-  if (*BootOptions == NULL) {
-    DEBUG ((DEBUG_ERROR, "Failed to allocate memory for BootOptions\n"));
-    return EFI_OUT_OF_RESOURCES;
-  }
-  Size = sizeof (EFI_INPUT_KEY) * HIKEY_BOOT_OPTION_NUM;
-  *BootKeys = (EFI_INPUT_KEY *)AllocateZeroPool (Size);
-  if (*BootKeys == NULL) {
-    DEBUG ((DEBUG_ERROR, "Failed to allocate memory for BootKeys\n"));
-    Status = EFI_OUT_OF_RESOURCES;
-    goto Error;
-  }
-
-  PathStr = (CHAR16 *)PcdGetPtr (PcdSdBootDevicePath);
-  ASSERT (PathStr != NULL);
-  Status = CreatePlatformBootOptionFromPath (
-             PathStr,
-             L"Boot from SD",
-             &(*BootOptions)[0]
-             );
-  ASSERT_EFI_ERROR (Status);
-
-  PathStr = (CHAR16 *)PcdGetPtr (PcdAndroidBootDevicePath);
-  ASSERT (PathStr != NULL);
-  Status = CreatePlatformBootOptionFromPath (
-             PathStr,
-             L"Grub",
-             &(*BootOptions)[1]
-             );
-  ASSERT_EFI_ERROR (Status);
-
-  FileGuid = PcdGetPtr (PcdAndroidBootFile);
-  ASSERT (FileGuid != NULL);
-  Status = CreatePlatformBootOptionFromGuid (
-             FileGuid,
-             L"Android Boot",
-             &(*BootOptions)[2]
-             );
-  ASSERT_EFI_ERROR (Status);
-
-  FileGuid = PcdGetPtr (PcdAndroidFastbootFile);
-  ASSERT (FileGuid != NULL);
-  Status = CreatePlatformBootOptionFromGuid (
-             FileGuid,
-             L"Android Fastboot",
-             &(*BootOptions)[3]
-             );
-  ASSERT_EFI_ERROR (Status);
-  (*BootKeys)[3].ScanCode = SCAN_NULL;
-  (*BootKeys)[3].UnicodeChar = 'f';
-
-  *BootCount = 4;
-
-  return EFI_SUCCESS;
-Error:
-  FreePool (*BootOptions);
-  return Status;
-}
-
-PLATFORM_BOOT_MANAGER_PROTOCOL mPlatformBootManager = {
-  GetPlatformBootOptionsAndKeys
-};
-
-EFI_STATUS
-EFIAPI
-VirtualKeyboardRegister (
-  IN VOID
-  )
-{
-  EFI_STATUS           Status;
-
-  Status = gBS->LocateProtocol (
-                  &gEmbeddedGpioProtocolGuid,
-                  NULL,
-                  (VOID **) &mGpio
-                  );
-  if (EFI_ERROR (Status)) {
-    return Status;
-  }
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EFIAPI
-VirtualKeyboardReset (
-  IN VOID
-  )
-{
-  EFI_STATUS           Status;
-
-  if (mGpio == NULL) {
-    return EFI_INVALID_PARAMETER;
-  }
-  Status = mGpio->Set (mGpio, DETECT_J15_FASTBOOT, GPIO_MODE_INPUT);
-  return Status;
-}
-
-BOOLEAN
-EFIAPI
-VirtualKeyboardQuery (
-  IN VIRTUAL_KBD_KEY             *VirtualKey
-  )
-{
-  EFI_STATUS           Status;
-  UINTN                Value = 0;
-
-  if ((VirtualKey == NULL) || (mGpio == NULL)) {
-    return FALSE;
-  }
-  if (MmioRead32 (ADB_REBOOT_ADDRESS) == ADB_REBOOT_BOOTLOADER) {
-    goto Done;
-  } else {
-    Status = mGpio->Get (mGpio, DETECT_J15_FASTBOOT, &Value);
-    if (EFI_ERROR (Status) || (Value != 0)) {
-      return FALSE;
-    }
-  }
-Done:
-  VirtualKey->Signature = VIRTUAL_KEYBOARD_KEY_SIGNATURE;
-  VirtualKey->Key.ScanCode = SCAN_NULL;
-  VirtualKey->Key.UnicodeChar = L'f';
-  return TRUE;
-}
-
-EFI_STATUS
-EFIAPI
-VirtualKeyboardClear (
-  IN VIRTUAL_KBD_KEY            *VirtualKey
-  )
-{
-  if (VirtualKey == NULL) {
-    return EFI_INVALID_PARAMETER;
-  }
-  if (MmioRead32 (ADB_REBOOT_ADDRESS) == ADB_REBOOT_BOOTLOADER) {
-    MmioWrite32 (ADB_REBOOT_ADDRESS, ADB_REBOOT_NONE);
-    WriteBackInvalidateDataCacheRange ((VOID *)ADB_REBOOT_ADDRESS, 4);
-  }
-  return EFI_SUCCESS;
-}
-
-PLATFORM_VIRTUAL_KBD_PROTOCOL mVirtualKeyboard = {
-  VirtualKeyboardRegister,
-  VirtualKeyboardReset,
-  VirtualKeyboardQuery,
-  VirtualKeyboardClear
-};
-
-STATIC  EFI_STATUS EFIAPI AppendArgs (
-  IN CHAR16            *Args,
-  IN UINTN              Size
-  )
-{
-	CHAR16 *newArgs =   (CHAR16 *)PcdGetPtr (PcdKernelBootArg);
-    UINTN srcSize, i, bootArgSize;
-
-    for (srcSize = 0; srcSize < Size / 2; srcSize++) {
-        if (!Args[srcSize])
-			break;
-    }
-
-    for (bootArgSize = 0; bootArgSize < Size / 2; bootArgSize++) {
-        if (!newArgs[bootArgSize])
-			break;
-    }
-
-	if (bootArgSize * 2 + srcSize * 2 < Size)
-	    for (i = 0; i < bootArgSize; i++)
-            Args[i] = newArgs[i];
-
-    return 0;
-}
-
-ANDROID_BOOTIMG_PROTOCOL mAndroidBootImageManager = {
-	  AppendArgs,
-	  NULL
-};
-
-STATIC CONST EFI_GUID mAcpiTableFile = {
-  0x7E374E25, 0x8E01, 0x4FEE, { 0x87, 0xf2, 0x39, 0x0C, 0x23, 0xC6, 0x06, 0xCD }
-};
-
-STATIC VOID SetFlashAttributeToUncache(VOID)
-{
-  EFI_STATUS Status;
-  EFI_GCD_MEMORY_SPACE_DESCRIPTOR desp = {0};
-
-  Status = gDS->AddMemorySpace (
-                     EfiGcdMemoryTypeMemoryMappedIo,
-                     PcdGet64(FspiBaseAddr),
-                     SIZE_64KB,
-                     EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
-                     );
-  if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR, "RTC: Failed to add memory space Status = %r\n", Status));
-    return;
-  }
-
-  Status = gDS->GetMemorySpaceDescriptor(PcdGet64(FspiBaseAddr),&desp);
-  DEBUG ((DEBUG_ERROR, "%a: GetMemorySpaceDescriptor status = %x\n", __FUNCTION__, Status));
-  if(EFI_ERROR(Status)){
-    return;
-  }
-
-  Status = gDS->SetMemorySpaceAttributes (
-                     PcdGet64(FspiBaseAddr),
-                     SIZE_64KB,
-                     EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
-                     );
-  if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR, "%a: Failed to set memory attributes Status = %x\n",__FUNCTION__, Status));
-  }
-
-  Status = gDS->AddMemorySpace (
-                     EfiGcdMemoryTypeMemoryMappedIo,
-                     PcdGet64(CruBaseAddr),
-                     SIZE_64KB,
-                     EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
-                     );
-  if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR, "RTC: Failed to add memory space Status = %r\n", Status));
-    return;
-  }
-
-  Status = gDS->GetMemorySpaceDescriptor(PcdGet64(CruBaseAddr),&desp);
-    DEBUG ((DEBUG_ERROR, "%a: GetMemorySpaceDescriptor status = %x\n", __FUNCTION__, Status));
-  if(EFI_ERROR(Status)){
-    return;
-  }
-
-  Status = gDS->SetMemorySpaceAttributes (
-                     PcdGet64(CruBaseAddr),
-                     SIZE_64KB,
-                     EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
-                     );
-  if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR, "%a: Failed to set memory attributes Status = %x\n",__FUNCTION__, Status));
-  }
-
-}
-
-EFI_STATUS
-EFIAPI
-RK3588EntryPoint (
-  IN EFI_HANDLE         ImageHandle,
-  IN EFI_SYSTEM_TABLE   *SystemTable
-  )
-{
-  EFI_STATUS            Status;
-
-  /* Update CPU speed */
-  // looks like the BL31 firmware in rk3588 isn't able to change frequency anymore
-  // You can get current CPU freq with it, and even set a new freq without error
-  // but it won't take effect.
-  // BoardInitSetCpuSpeed();
-  
-  Status = RK3588InitPeripherals ();
-  if (EFI_ERROR (Status)) {
-    return Status;
-  }
-
-  SetFlashAttributeToUncache();
-
-  if(PcdGetBool (AcpiEnable)) {
-    LocateAndInstallAcpiFromFvConditional (&mAcpiTableFile, NULL);
-  }
-
-  Status = gBS->InstallProtocolInterface (
-                  &ImageHandle,
-                  &gPlatformVirtualKeyboardProtocolGuid,
-                  EFI_NATIVE_INTERFACE,
-                  &mVirtualKeyboard
-                  );
-  if (EFI_ERROR (Status)) {
-    return Status;
-  }
-
-  Status = gBS->InstallProtocolInterface (
-                  &ImageHandle,
-                  &gPlatformBootManagerProtocolGuid,
-                  EFI_NATIVE_INTERFACE,
-                  &mPlatformBootManager
-                  );
-
-  if (EFI_ERROR (Status)) {
-    return Status;
-  }
-
-  Status = gBS->InstallProtocolInterface (
-                  &ImageHandle,
-                  &gAndroidBootImgProtocolGuid,
-                  EFI_NATIVE_INTERFACE,
-                  &mAndroidBootImageManager
-                  );
-
-  return Status;
-}
--- a/edk2-platforms/Platform/Radxa/ROCK5B/Drivers/RK3588Dxe_rock5b/RK3588Dxe.inf
+++ b/edk2-platforms/Platform/Radxa/ROCK5B/Drivers/RK3588Dxe_rock5b/RK3588Dxe.inf
@@ -1,67 +0,0 @@
-#
-#  Copyright (c) 2013 - 2014, ARM Ltd. All rights reserved.
-#  Copyright (c) 2018, Linaro Ltd. All rights reserved.
-#
-#  SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-
-[Defines]
-  INF_VERSION                    = 0x0001001a
-  BASE_NAME                      = RK3588Dxe
-  FILE_GUID                      = f6c64348-45ec-11ec-9726-f42a7dcb925d
-  MODULE_TYPE                    = DXE_DRIVER
-  VERSION_STRING                 = 1.0
-  ENTRY_POINT                    = RK3588EntryPoint
-
-[Sources.common]
-  RK3588Dxe.c
-
-[Packages]
-  ArmPkg/ArmPkg.dec
-  EmbeddedPkg/EmbeddedPkg.dec
-  MdeModulePkg/MdeModulePkg.dec
-  MdePkg/MdePkg.dec
-  Platform/Rockchip/RK3588/RK3588.dec
-  Silicon/Rockchip/RockchipPkg.dec
-  ArmPlatformPkg/ArmPlatformPkg.dec
-  Platform/Radxa/ROCK5B/ROCK5B.dec
-
-[LibraryClasses]
-  CacheMaintenanceLib
-  DebugLib
-  AcpiLib
-  IoLib
-  UefiBootManagerLib
-  UefiLib
-  UefiDriverEntryPoint
-  SpiLib
-  RK806
-  CruLib
-  ArmLib
-  NonDiscoverableDeviceRegistrationLib
-
-[Protocols]
-  gEfiDevicePathFromTextProtocolGuid
-  gEfiLoadedImageProtocolGuid
-  gEmbeddedGpioProtocolGuid
-  gPlatformBootManagerProtocolGuid
-  gPlatformVirtualKeyboardProtocolGuid
-  gAndroidBootImgProtocolGuid
-  gEfiCpuArchProtocolGuid
-
-[Pcd]
-  gRK3588TokenSpaceGuid.PcdAndroidBootDevicePath
-  gRK3588TokenSpaceGuid.PcdAndroidBootFile
-  gRK3588TokenSpaceGuid.PcdAndroidFastbootFile
-  gRK3588TokenSpaceGuid.PcdSdBootDevicePath
-  gRK3588TokenSpaceGuid.AcpiEnable
-  gRockchipTokenSpaceGuid.CruBaseAddr
-  gRockchipTokenSpaceGuid.FspiBaseAddr
-  gRK3588TokenSpaceGuid.PcdKernelBootArg
-  gRockchipTokenSpaceGuid.PcdComboPhyMode
-
-[Guids]
-  gEfiEndOfDxeEventGroupGuid
-
-[Depex]
-  TRUE
--- a/edk2-platforms/Platform/Radxa/ROCK5B/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.c
+++ b/edk2-platforms/Platform/Radxa/ROCK5B/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.c
@@ -1,296 +0,0 @@
-/** @file
-  UART Serial Port library functions
-
-  Copyright (c) 2006 - 2009, Intel Corporation
-  Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved.
-  Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved.
-  SPDX-License-Identifier: BSD-2-Clause-Patent
-
-  Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/
-**/
-#include <Uefi.h>
-#include <Library/PcdLib.h>
-#include <Library/SerialPortLib.h>
-#include <Library/IoLib.h>
-#include <Protocol/SerialIo.h>
-
-#include "Dw8250SerialPortLib.h"
-
-
-/**
-  Initialize the serial device hardware.
-
-  If no initialization is required, then return RETURN_SUCCESS.
-  If the serial device was successfuly initialized, then return RETURN_SUCCESS.
-  If the serial device could not be initialized, then return RETURN_DEVICE_ERROR.
-
-  @retval RETURN_SUCCESS        The serial device was initialized.
-  @retval RETURN_DEVICE_ERROR   The serail device could not be initialized.
-
-**/
-RETURN_STATUS
-EFIAPI
-SerialPortInitialize (
-  VOID
-  )
-{
-    UINT32 ulUartClkFreq;
-
-    MmioWrite8 (UART_LCR_REG, UART_LCR_DLS8);
-    MmioWrite8 (UART_FCR_REG, UART_FCR_EN | UART_FCR_RXCLR | UART_FCR_TXCLR);
-    MmioWrite8 (UART_LCR_REG, UART_LCR_DLAB | UART_LCR_DLS8);
-
-    ulUartClkFreq = PcdGet32(PcdUartClkInHz);
-
-    MmioWrite8 (UART_DLL_REG, (ulUartClkFreq / (16 * (UINT32)BAUDRATE) ) & 0xff);
-    MmioWrite8 (UART_DLH_REG, ((ulUartClkFreq/ (16 * (UINT32)BAUDRATE) ) >> 8 ) & 0xff);
-    MmioWrite8 (UART_LCR_REG, UART_LCR_DLS8);
-    MmioWrite8 (UART_IEL_REG, 0x00);
-
-    return RETURN_SUCCESS;
-}
-
-
-/**
-  Write data from buffer to serial device.
-
-  Writes NumberOfBytes data bytes from Buffer to the serial device.
-  The number of bytes actually written to the serial device is returned.
-  If the return value is less than NumberOfBytes, then the write operation failed.
-
-  If Buffer is NULL, then ASSERT().
-
-  If NumberOfBytes is zero, then return 0.
-
-  @param  Buffer           Pointer to the data buffer to be written.
-  @param  NumberOfBytes    Number of bytes to written to the serial device.
-
-  @retval 0                NumberOfBytes is 0.
-  @retval >0               The number of bytes written to the serial device.
-                           If this value is less than NumberOfBytes, then the read operation failed.
-
-**/
-UINTN
-EFIAPI
-SerialPortWrite (
-  IN UINT8     *Buffer,
-  IN UINTN     NumberOfBytes
-)
-{
-  UINTN  Result;
-
-  if (NULL == Buffer) {
-    return 0;
-  }
-
-  Result = NumberOfBytes;
-
-  while (NumberOfBytes--) {
-
-    SerialPortWriteChar(*Buffer);
-    Buffer++;
-  }
-
-  return Result;
-}
-
-
-/**
-  Reads data from a serial device into a buffer.
-
-  @param  Buffer           Pointer to the data buffer to store the data read from the serial device.
-  @param  NumberOfBytes    Number of bytes to read from the serial device.
-
-  @retval 0                NumberOfBytes is 0.
-  @retval >0               The number of bytes read from the serial device.
-                           If this value is less than NumberOfBytes, then the read operation failed.
-
-**/
-UINTN
-EFIAPI
-SerialPortRead (
-  OUT UINT8     *Buffer,
-  IN  UINTN     NumberOfBytes
-)
-{
-  UINTN  Result;
-
-  if (NULL == Buffer) {
-    return 0;
-  }
-
-  Result = 0;
-
-  while (NumberOfBytes--) {
-    //
-    // Wait for the serail port to be ready.
-    //
-    *Buffer=SerialPortReadChar();
-    Buffer++ ;
-    Result++;
-  }
-
-  return Result;
-}
-
-/**
-  Polls a serial device to see if there is any data waiting to be read.
-
-  Polls aserial device to see if there is any data waiting to be read.
-  If there is data waiting to be read from the serial device, then TRUE is returned.
-  If there is no data waiting to be read from the serial device, then FALSE is returned.
-
-  @retval TRUE             Data is waiting to be read from the serial device.
-  @retval FALSE            There is no data waiting to be read from the serial device.
-
-**/
-BOOLEAN
-EFIAPI
-SerialPortPoll (
-  VOID
-  )
-{
-
-  return (BOOLEAN) ((MmioRead8 (UART_LSR_REG) & UART_LSR_DR) == UART_LSR_DR);
-
-}
-
-
-VOID SerialPortWriteChar(UINT8 scShowChar)
-{
-    UINT32 ulLoop = 0;
-
-    while(ulLoop < (UINT32)UART_SEND_DELAY)
-    {
-
-        if ((MmioRead8 (UART_USR_REG) & 0x02) == 0x02)
-        {
-            break;
-        }
-
-        ulLoop++;
-    }
-    MmioWrite8 (UART_THR_REG, (UINT8)scShowChar);
-
-    ulLoop = 0;
-    while(ulLoop < (UINT32)UART_SEND_DELAY)
-    {
-        if ((MmioRead8 (UART_USR_REG) & 0x04) == 0x04)
-        {
-            break;
-        }
-        ulLoop++;
-    }
-
-    return;
-}
-
-
-UINT8 SerialPortReadChar(VOID)
-{
-    UINT8 recvchar = 0;
-
-    while(1)
-    {
-        if ((MmioRead8 (UART_LSR_REG) & UART_LSR_DR) == UART_LSR_DR)
-        {
-            break;
-        }
-    }
-
-    recvchar = MmioRead8 (UART_RBR_REG);
-
-    return recvchar;
-}
-
-/**
-  Sets the baud rate, receive FIFO depth, transmit/receice time out, parity,
-  data bits, and stop bits on a serial device.
-
-  @param BaudRate           The requested baud rate. A BaudRate value of 0 will use the
-                            device's default interface speed.
-                            On output, the value actually set.
-  @param ReveiveFifoDepth   The requested depth of the FIFO on the receive side of the
-                            serial interface. A ReceiveFifoDepth value of 0 will use
-                            the device's default FIFO depth.
-                            On output, the value actually set.
-  @param Timeout            The requested time out for a single character in microseconds.
-                            This timeout applies to both the transmit and receive side of the
-                            interface. A Timeout value of 0 will use the device's default time
-                            out value.
-                            On output, the value actually set.
-  @param Parity             The type of parity to use on this serial device. A Parity value of
-                            DefaultParity will use the device's default parity value.
-                            On output, the value actually set.
-  @param DataBits           The number of data bits to use on the serial device. A DataBits
-                            vaule of 0 will use the device's default data bit setting.
-                            On output, the value actually set.
-  @param StopBits           The number of stop bits to use on this serial device. A StopBits
-                            value of DefaultStopBits will use the device's default number of
-                            stop bits.
-                            On output, the value actually set.
-
-  @retval RETURN_SUCCESS            The new attributes were set on the serial device.
-  @retval RETURN_UNSUPPORTED        The serial device does not support this operation.
-  @retval RETURN_INVALID_PARAMETER  One or more of the attributes has an unsupported value.
-  @retval RETURN_DEVICE_ERROR       The serial device is not functioning correctly.
-
-**/
-RETURN_STATUS
-EFIAPI
-SerialPortSetAttributes (
-  IN OUT UINT64             *BaudRate,
-  IN OUT UINT32             *ReceiveFifoDepth,
-  IN OUT UINT32             *Timeout,
-  IN OUT EFI_PARITY_TYPE    *Parity,
-  IN OUT UINT8              *DataBits,
-  IN OUT EFI_STOP_BITS_TYPE *StopBits
-  )
-{
-  return RETURN_UNSUPPORTED;
-}
-
-/**
-  Set the serial device control bits.
-
-  @param  Control                 Control bits which are to be set on the serial device.
-
-  @retval EFI_SUCCESS             The new control bits were set on the serial device.
-  @retval EFI_UNSUPPORTED         The serial device does not support this operation.
-  @retval EFI_DEVICE_ERROR        The serial device is not functioning correctly.
-
-**/
-RETURN_STATUS
-EFIAPI
-SerialPortSetControl (
-  IN UINT32                  Control
-  )
-{
-  return EFI_UNSUPPORTED;
-}
-
-/**
-  Get the serial device control bits.
-
-  @param  Control                 Control signals read from the serial device.
-
-  @retval EFI_SUCCESS             The control bits were read from the serial device.
-  @retval EFI_DEVICE_ERROR        The serial device is not functioning correctly.
-
-**/
-RETURN_STATUS
-EFIAPI
-SerialPortGetControl (
-  OUT UINT32                  *Control
-  )
-{
-
-    if (SerialPortPoll ()) {
-        // If a character is pending don't set EFI_SERIAL_INPUT_BUFFER_EMPTY
-        *Control = EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
-    } else {
-        *Control = EFI_SERIAL_INPUT_BUFFER_EMPTY | EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
-    }
-    return EFI_SUCCESS;
-}
-
--- a/edk2-platforms/Platform/Radxa/ROCK5B/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.h
+++ b/edk2-platforms/Platform/Radxa/ROCK5B/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.h
@@ -1,110 +0,0 @@
-/** @file
-*
-*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
-*  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
-*  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
-*
-*  SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-*  Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/
-**/
-
-#ifndef __DW8250_SERIALPORTLIB_H__
-#define __DW8250_SERIALPORTLIB_H__
-
-
-#define SERIAL_0_BASE_ADR     (PcdGet64(PcdSerialRegisterBase))
-
-
-#define UART_SEND_DELAY      (PcdGet32(PcdSerialPortSendDelay))
-#define BAUDRATE             (PcdGet64(PcdUartDefaultBaudRate))
-
-
-#define UART_THR_REG         (SERIAL_0_BASE_ADR + UART_THR)
-#define UART_RBR_REG         (SERIAL_0_BASE_ADR + UART_RBR)
-#define UART_DLL_REG         (SERIAL_0_BASE_ADR + UART_DLL)
-#define UART_DLH_REG         (SERIAL_0_BASE_ADR + UART_DLH)
-#define UART_IEL_REG         (SERIAL_0_BASE_ADR + UART_IEL)
-#define UART_IIR_REG         (SERIAL_0_BASE_ADR + UART_IIR)
-#define UART_FCR_REG         (SERIAL_0_BASE_ADR + UART_FCR)
-#define UART_LCR_REG         (SERIAL_0_BASE_ADR + UART_LCR)
-#define UART_LSR_REG         (SERIAL_0_BASE_ADR + UART_LSR)
-#define UART_USR_REG         (SERIAL_0_BASE_ADR + UART_USR)
-
-
-#define UART_RBR     0x00
-#define UART_THR     0x00
-#define UART_DLL     0x00
-#define UART_DLH     0x04
-#define UART_IEL     0x04
-#define UART_IIR     0x08
-#define UART_FCR     0x08
-#define UART_LCR     0x0C
-#define UART_MCR     0x10
-#define UART_LSR     0x14
-#define UART_USR     0x7C
-
-/* register definitions */
-
-#define UART_FCR_EN          0x01
-#define UART_FCR_RXCLR       0x02
-#define UART_FCR_TXCLR       0x04
-#define UART_FCR_CLEARFIFO   0x00
-#define UART_FCR_RXL1        0x00
-#define UART_FCR_RXL4        0x40
-#define UART_FCR_RXL8        0x80
-#define UART_FCR_RXL14       0xc0
-#define UART_FCR_TXL0        0x00
-#define UART_FCR_TXL4        0x20
-#define UART_FCR_TXL8        0x30
-#define UART_FCR_TXL14       0x10
-
-/*LCR Name: Line Control Register fields*/
-#define UART_LCR_DLAB   0x80
-#define UART_LCR_EPS    0x10
-#define UART_LCR_PEN    0x08
-#define UART_LCR_STOP   0x04
-#define UART_LCR_DLS8   0x03
-#define UART_LCR_DLS7   0x02
-#define UART_LCR_DLS6   0x01
-#define UART_LCR_DLS5   0x00
-
-
-#define UART_DLH_AND_DLL_WIDTH 0xFF
-
-
-#define UART_IER_PTIME  0x80
-#define UART_IER_ELSI   0x04
-#define UART_IER_ETBEI  0x02
-#define UART_IER_ERBFI  0x01
-
-
-#define UART_IIR_FIFOSE         0xC0
-
-
-#define UART_IIR_InterruptID   0x01
-#define UART_IIR_INTIDTE       0x02
-#define UART_IIR_INTIDRA       0x04
-#define UART_IIR_INTIDRLS      0x06
-#define UART_IIR_INTMASK       0x0f
-#define UART_IIR_RDA           0x04
-#define UART_IIR_TE            0x02
-
-#define UART_LSR_TEMT       0x40
-#define UART_LSR_THRE       0x20
-#define UART_LSR_BI         0x10
-#define UART_LSR_FE         0x08
-#define UART_LSR_PE         0x04
-#define UART_LSR_R          0x02
-#define UART_LSR_DR         0x01
-
-
-#define UART_USR_BUSY  0x01
-
-#define FIFO_MAXSIZE    32
-
-extern UINT8 SerialPortReadChar(VOID);
-extern VOID SerialPortWriteChar(UINT8 scShowChar);
-
-#endif
-
--- a/edk2-platforms/Platform/Radxa/ROCK5B/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf
+++ b/edk2-platforms/Platform/Radxa/ROCK5B/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf
@@ -1,36 +0,0 @@
-#/** @file
-#
-#  Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
-#  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
-#  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
-#  SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-#  Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = Dw8250SerialPortLib
-  FILE_GUID                      = 78337705-D2A8-4EA7-9C18-27FC4A8A2C6E
-  MODULE_TYPE                    = BASE
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = SerialPortLib
-
-[Sources.common]
-  Dw8250SerialPortLib.c
-
-[Packages]
-  MdePkg/MdePkg.dec
-  MdeModulePkg/MdeModulePkg.dec
-  ArmPlatformPkg/ArmPlatformPkg.dec
-  Platform/Radxa/ROCK5B/ROCK5B.dec
-
-[LibraryClasses]
-  BaseLib
-  IoLib
-
-[Pcd]
-  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
-  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
-  gROCK5BTokenSpaceGuid.PcdSerialPortSendDelay
-  gROCK5BTokenSpaceGuid.PcdUartClkInHz
--- a/edk2-platforms/Platform/Radxa/ROCK5B/Library/PlatformBootManagerLib/PlatformBm.c
+++ b/edk2-platforms/Platform/Radxa/ROCK5B/Library/PlatformBootManagerLib/PlatformBm.c
--- a/edk2-platforms/Platform/Radxa/ROCK5B/Library/PlatformBootManagerLib/PlatformBm.h
+++ b/edk2-platforms/Platform/Radxa/ROCK5B/Library/PlatformBootManagerLib/PlatformBm.h
@@ -1,53 +0,0 @@
-/** @file
-  Head file for BDS Platform specific code
-
-  Copyright (C) 2015-2016, Red Hat, Inc.
-  Copyright (c) 2004 - 2008, Intel Corporation. All rights reserved.<BR>
-  Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
-
-  SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef PLATFORM_BM_H_
-#define PLATFORM_BM_H_
-
-#include <Library/BaseLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/DebugLib.h>
-#include <Library/DevicePathLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiLib.h>
-#include <Library/UefiRuntimeServicesTableLib.h>
-
-/**
-  Use SystemTable Conout to stop video based Simple Text Out consoles from
-  going to the video device. Put up LogoFile on every video device that is a
-  console.
-
-  @param[in]  LogoFile   File name of logo to display on the center of the
-                         screen.
-
-  @retval EFI_SUCCESS     ConsoleControl has been flipped to graphics and logo
-                          displayed.
-  @retval EFI_UNSUPPORTED Logo not found
-**/
-EFI_STATUS
-EnableQuietBoot (
-  IN  EFI_GUID  *LogoFile
-  );
-
-/**
-  Use SystemTable Conout to turn on video based Simple Text Out consoles. The
-  Simple Text Out screens will now be synced up with all non video output
-  devices
-
-  @retval EFI_SUCCESS     UGA devices are back in text mode and synced up.
-**/
-EFI_STATUS
-DisableQuietBoot (
-  VOID
-  );
-
-#endif // PLATFORM_BM_H_
--- a/edk2-platforms/Platform/Radxa/ROCK5B/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+++ b/edk2-platforms/Platform/Radxa/ROCK5B/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -1,97 +0,0 @@
-## @file
-#  Implementation for PlatformBootManagerLib library class interfaces.
-#
-#  Copyright (C) 2015-2016, Red Hat, Inc.
-#  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
-#  Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
-#  Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
-#
-#  SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-##
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = PlatformBootManagerLib
-  FILE_GUID                      = 92FD2DE3-B9CB-4B35-8141-42AD34D73C9F
-  MODULE_TYPE                    = DXE_DRIVER
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = PlatformBootManagerLib|DXE_DRIVER
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-#  VALID_ARCHITECTURES           = ARM AARCH64
-#
-
-[Sources]
-  PlatformBm.c
-  PlatformBm.h
-
-[Packages]
-  EmbeddedPkg/EmbeddedPkg.dec
-  MdeModulePkg/MdeModulePkg.dec
-  MdePkg/MdePkg.dec
-  ShellPkg/ShellPkg.dec
-  Platform/Radxa/ROCK5B/ROCK5B.dec
-  SimpleInit.dec
-
-[LibraryClasses]
-  BaseLib
-  BaseMemoryLib
-  BootLogoLib
-  CapsuleLib
-  DebugLib
-  DevicePathLib
-  DxeServicesLib
-  HobLib
-  MemoryAllocationLib
-  PcdLib
-  PrintLib
-  UefiBootManagerLib
-  UefiBootServicesTableLib
-  UefiLib
-  UefiRuntimeServicesTableLib
-
-[FeaturePcd]
-  gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport
-
-[FixedPcd]
-  gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
-  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
-  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
-  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
-  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
-  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType
-
-[Pcd]
-  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
-  gEfiMdeModulePkgTokenSpaceGuid.PcdBootDiscoveryPolicy
-
-[Guids]
-  gBootDiscoveryPolicyMgrFormsetGuid
-  gEdkiiNonDiscoverableEhciDeviceGuid
-  gEdkiiNonDiscoverableUhciDeviceGuid
-  gEdkiiNonDiscoverableXhciDeviceGuid
-  gEfiBootManagerPolicyNetworkGuid
-  gEfiBootManagerPolicyConnectAllGuid
-  gEfiFileInfoGuid
-  gEfiFileSystemInfoGuid
-  gEfiFileSystemVolumeLabelInfoIdGuid
-  gEfiEndOfDxeEventGroupGuid
-  gEfiTtyTermGuid
-  gUefiShellFileGuid
-  gSimpleInitFileGuid
-  gMaskromFileGuid
-
-[Protocols]
-  gEdkiiNonDiscoverableDeviceProtocolGuid
-  gEfiBootManagerPolicyProtocolGuid
-  gEfiDevicePathProtocolGuid
-  gEfiGraphicsOutputProtocolGuid
-  gEfiLoadedImageProtocolGuid
-  gEfiPciRootBridgeIoProtocolGuid
-  gEfiSimpleFileSystemProtocolGuid
-  gEsrtManagementProtocolGuid
-  gPlatformBootManagerProtocolGuid
--- a/edk2-platforms/Platform/Radxa/ROCK5B/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-platforms/Platform/Radxa/ROCK5B/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -9,49 +9,55 @@
 #include <Library/DebugLib.h>
 #include <Library/IoLib.h>
 #include <Library/GpioLib.h>
+#include <Library/RK806.h>
 #include <Soc.h>

-void DebugPrintHex(void *buf, UINT32 width, UINT32 len)
+static struct regulator_init_data rk806_init_data[] = {
+  /* Master PMIC */
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
+  //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+
+  /* No dual PMICs on this platform */
+};
+
+VOID
+EFIAPI
+DwEmmcDxeIoMux (
+  VOID
+  )
 {
-  UINT32 i,j;
-  UINT8 *p8 = (UINT8 *) buf;
-  UINT16 *p16 = (UINT16 *) buf;
-  UINT32 *p32 =(UINT32 *) buf;
-
-  j = 0;
-  for (i = 0; i < len; i++) {
-    if (j == 0) {
-      DebugPrint(DEBUG_ERROR, "%p + 0x%x:",buf, i * width);
-    }
-
-    if (width == 4) {
-      DebugPrint(DEBUG_ERROR, "0x%08x,", p32[i]);
-    } else if (width == 2) {
-      DebugPrint(DEBUG_ERROR, "0x%04x,", p16[i]);
-    } else {
-      DebugPrint(DEBUG_ERROR, "0x%02x,", p8[i]);
-    }
-
-    if (++j >= (16/width)) {
-      j = 0;
-      DebugPrint(DEBUG_ERROR, "\n","");
-    }
-  }
-  DebugPrint(DEBUG_ERROR, "\n","");
+  /* sdmmc0 iomux (microSD socket) */
+  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
 }

-void
+VOID
 EFIAPI
-DwEmmcDxeIoMux(void)
+SdhciEmmcDxeIoMux (
+  VOID
+  )
 {
-  /* sdmmc0 iomux */
-}
-
-void
-EFIAPI
-SdhciEmmcDxeIoMux(void)
-{
-  /* sdmmc0 iomux */
+  /* sdhci0 iomux (eMMC socket) */
  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
@@ -61,9 +67,11 @@ SdhciEmmcDxeIoMux(void)
 #define CRU_CLKSEL_CON59    0x03EC
 #define CRU_CLKSEL_CON78    0x0438

-void
+VOID
 EFIAPI
-Rk806SpiIomux(void)
+Rk806SpiIomux (
+  VOID
+  )
 {
  /* io mux */
  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
@@ -73,9 +81,37 @@ Rk806SpiIomux(void)
  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
 }

-void
+VOID
 EFIAPI
-NorFspiIomux(void)
+Rk806Configure (
+  VOID
+  )
+{
+  UINTN RegCfgIndex;
+
+  RK806Init();
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
+    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+}
+
+VOID
+EFIAPI
+SetCPULittleVoltage (
+  IN UINT32 Microvolts
+  )
+{
+  struct regulator_init_data Rk806CpuLittleSupply =
+        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+
+  RK806RegulatorInit(Rk806CpuLittleSupply);
+}
+
+VOID
+EFIAPI
+NorFspiIomux (
+  VOID
+  )
 {
  /* io mux */
  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
@@ -99,11 +135,11 @@ NorFspiIomux(void)
 #endif
 }

-void
+VOID
 EFIAPI
 GmacIomux (
   UINT32 id
-)
+  )
 {
  switch (id) {
  case 0:
@@ -123,37 +159,35 @@ GmacIomux (
  }
 }

-void
+VOID
 EFIAPI
 NorFspiEnableClock (
  UINT32 *CruBase
-)
+  )
 {
  UINTN BaseAddr = (UINTN) CruBase;

  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
 }

-UINT32
+VOID
 EFIAPI
-I2cGetBase (
+I2cIomux (
   UINT32 id
-)
+  )
 {
-  UINT32 Base = 0;
-
  switch (id) {
  case 0:
-    Base = 0xFD880000;
+    /* io mux M2 */
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
    break;
  case 1:
-    Base = 0xFEA90000;
    /* io mux */
    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
    break;
  case 2:
-    Base = 0xFEAA0000;
    /* io mux */
    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
@@ -161,30 +195,21 @@ I2cGetBase (
    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
    break;
  case 3:
-    Base = 0xFEAB0000;
    break;
  case 4:
-    Base = 0xFEAC0000;
    break;
  case 5:
-    Base = 0xFEAD0000;
    break;
  default:
    break;
  }
-
-  return Base;
 }

-#define GPIO4_BASE         0xFEC50000
-#define GPIO_SWPORT_DR_L   0x0000
-#define GPIO_SWPORT_DR_H   0x0004
-#define GPIO_SWPORT_DDR_L  0x0008
-#define GPIO_SWPORT_DDR_H  0x000C
-
-void
+VOID
 EFIAPI
-UsbPortPowerEnable (void)
+UsbPortPowerEnable (
+  VOID
+  )
 {
  DEBUG((EFI_D_WARN, "UsbPortPowerEnable called\n"));
  /* Set GPIO4 PB0 (USB_HOST_PWREN) output high to power USB ports */
@@ -196,18 +221,11 @@ UsbPortPowerEnable (void)
  // GpioPinSetDirection (0, GPIO_PIN_PB7, GPIO_PIN_OUTPUT);
 }

-void
+VOID
 EFIAPI
-Usb2PhySuspend (void)
-{
-  MmioWrite32(0xfd5d4008, 0x20000000);
-  MmioWrite32(0xfd5d8008, 0x20000000);
-  MmioWrite32(0xfd5dc008, 0x20000000);
-}
-
-void
-EFIAPI
-Usb2PhyResume (void)
+Usb2PhyResume (
+  VOID
+  )
 {
  MmioWrite32(0xfd5d0008, 0x20000000);
  MmioWrite32(0xfd5d4008, 0x20000000);
@@ -217,9 +235,11 @@ Usb2PhyResume (void)
  MmioWrite32(0xfd7f0a10, 0x07000000);
 }

-void
+VOID
 EFIAPI
-UsbDpPhyEnable (void)
+UsbDpPhyEnable (
+  VOID
+  )
 {
  /* enable rx_lfps_en & usbdp_low_pwrn */
  MmioWrite32(0xfd5c8004, 0x60006000);
@@ -230,43 +250,32 @@ UsbDpPhyEnable (void)
  MmioWrite32 (0xfd5cc00c, 0x00030001);
 }

-void
+VOID
 EFIAPI
-Dwc3Force20ClkFor30Clk (UINT32 Address, BOOLEAN enable)
-{
-  UINT32 Reg;
-
-  if (enable) {
-    Reg = MmioRead32(Address);
-    Reg |= (1 << 26);
-    MmioWrite32((Address), Reg);
-  } else {
-    Reg = MmioRead32(Address);
-    Reg &= ~(1 << 26);
-    MmioWrite32(Address, Reg);
-  }
-}
-
-void
-EFIAPI
-Pcie30IoInit(void)
+Pcie30IoInit (
+  VOID
+  )
 {
  /* Set reset and power IO to gpio output mode */
  GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
  GpioPinSetDirection (1, GPIO_PIN_PA4, GPIO_PIN_OUTPUT);
 }

-void
+VOID
 EFIAPI
-Pcie30PowerEn(void)
+Pcie30PowerEn (
+  VOID
+  )
 {
  /* output high to enable power */
  GpioPinWrite (1, GPIO_PIN_PA4, TRUE);
 }

-void
+VOID
 EFIAPI
-Pcie30PeReset(BOOLEAN enable)
+Pcie30PeReset (
+  BOOLEAN enable
+  )
 {
  if(enable)
    GpioPinWrite (4, GPIO_PIN_PB6, FALSE); /* output low */
@@ -274,3 +283,11 @@ Pcie30PeReset(BOOLEAN enable)
    GpioPinWrite (4, GPIO_PIN_PB6, TRUE); /* output high */
 }

+VOID
+EFIAPI
+PlatformEarlyInit (
+  VOID
+  )
+{
+  // Configure various things specific to this platform
+}
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Mario Bălănică	8d3b89755d	Update README.md	2023-06-01 03:52:28 +03:00
Mario Bălănică	b9e6b9baec	Platforms: Make UEFI FV size consistent Increase size to 0x00500000 for remaining platforms.	2023-06-01 03:40:02 +03:00
Mario Bălănică	1bb2861929	Do not append NV var store to the final flash image This allows the variables to persist across firmware updates. If the store is corrupted or missing (which was also the case with NV_DATA.img being actually empty), the FVB driver should rewrite a clean FV header.	2023-06-01 03:36:20 +03:00
Mario Bălănică	017844d902	Platform/ROCK5A: Rename "ROCK 5A" to "ROCK 5 Model A" To be consistent with Model B and naming on the website.	2023-06-01 02:54:54 +03:00
Mario Bălănică	5fc7f34ea5	Platform/ROCK5B: Don't allow switching Combo PHY #0 It is hardwired to the onboard Realtek PCIe NIC.	2023-06-01 02:43:40 +03:00
Mario Bălănică	f6c1346772	Silicon/Rockchip: Disable SATA staggered spin-up With it enabled, NetBSD doesn't pick up any drive (be it HDD or SSD) most of the time (is this a driver or controller bug?).	2023-06-01 02:42:05 +03:00
Mario Bălănică	fc5ee180d8	Platforms: Expose SATA devices in ACPI Enable only controllers that have the PHY routable to some kind of connector on the platform. It would be better to have them into their own SSDT that gets installed at runtime depending on the Combo PHY configuration.	2023-06-01 02:39:39 +03:00
Mario Bălănică	57a86578c2	Platforms: Set default CPU clock presets The SoC heats up quite a lot with CPU clocks and voltages always set to max. Therefore, leave clocks at their boot default value on platforms without active cooling that's turned on by default. The presets can be overridden by the user in the Configuration menu, assuming proper cooling is installed.	2023-06-01 01:06:48 +03:00
Mario Bălănică	39118afb47	Silicon/Rockchip: Add default cluster clock preset PCDs	2023-06-01 00:46:43 +03:00
Mario Bălănică	40be23e7d5	Platforms: Configure default Combo PHY modes - Combo PHY #1 is not exposed on RK3588S. - For platforms that have an USB 3 port directly wired to the PHY (that is, no hub in between), allow switching modes as it's fairly possible to hack together an USB 3 to PCIe or SATA cable.	2023-06-01 00:00:03 +03:00
Mario Bălănică	7595444430	Silicon/Rockchip: Make the Naneng Combo PHY user-configurable	2023-05-31 23:23:37 +03:00
Mario Bălănică	16d3555631	Silicon/Rockchip: Fix SATA support The upstream driver works fine if we correct the HBA capabilities. Also fix and split the ACPI devices into their own file, since RK3588S lacks SATA #1.	2023-05-30 18:57:35 +03:00
Mario Bălănică	dbde496288	Platforms: Switch to AHCI drivers from MdeModulePkg	2023-05-30 18:38:36 +03:00
Mario Bălănică	4f261d1115	Platform/ROCK5A: Enable eMMC and update pin muxing comments Same as the previous change for Indiedroid Nova.	2023-05-30 04:15:21 +03:00
Mario Bălănică	e1f1f50ef5	Platform/IndiedroidNova: Do not override eMMC and FSPI pin muxing The eMMC slot is shared with FSPI, making it possible to connect either an eMMC or SPI NOR module. Pin muxing is already configured by earlier boot stages depending on what's detected in the slot, thus no need to perform the detection ourselves.	2023-05-30 04:13:27 +03:00
Mario Bălănică	df1f46add9	Platforms: Enable RkFvbDxe	2023-05-30 03:24:44 +03:00
Mario Bălănică	c1de6b10ff	Silicon/Rockchip: Support persistent variable store on SD/eMMC On SD/eMMC this feature is more limited, since these devices are meant to be used by the OS and we can't take ownership of them. As such, changes to the var store will only be saved at boot time when certain events happen (platform reset, ready to boot, image load). Full runtime support is available when booted from SPI NOR flash. Also introduce the gRockchipTokenSpaceGuid.PcdNvStoragePreferSpiFlash flag which forces the var store to be on SPI flash, if available, no matter the boot device. This can be useful during development as NOR flash is quite slow to write compared to SD.	2023-05-30 03:08:04 +03:00
Mario Bălănică	4db804855f	Silicon/Rockchip: Make SD controllers identifiable by base address	2023-05-30 02:06:12 +03:00
Mario Bălănică	1184da0f5d	Silicon/Rockchip: Signal an event on system reset	2023-05-30 02:00:33 +03:00
Mario Bălănică	d496851043	U-Boot FIT: Map UEFI NV region into memory Load it at the same address as seen in flash so we don't have to deal with reading it from the boot device in UEFI anymore.	2023-05-30 01:54:27 +03:00
Mario Bălănică	1d435eeafb	Silicon/Rockchip: Add ATAGS reading library	2023-05-26 17:48:50 +03:00
Molly Sophia	0c765f022b	Workflow: Fix CI Signed-off-by: Molly Sophia <mollysophia379@gmail.com>	2023-05-21 16:11:43 +08:00
Molly Sophia	3461e121e6	Rockchip: Reduce code duplication in DwEmmcDxe Signed-off-by: Molly Sophia <mollysophia379@gmail.com>	2023-05-21 16:08:16 +08:00
Molly Sophia	8eb1541a00	RK3588: Remove duplicated (and unused) RK3588Dxe Signed-off-by: Molly Sophia <mollysophia379@gmail.com>	2023-05-21 16:05:27 +08:00
Molly Sophia	3dd1abd91d	Update build.sh This includes several tiny fixes: - Fixed `build.sh --clean` command - Partially fixed `build.sh -d all` command - Don't check for SimpleInit folder when BUILD_GUI is false - Added a define CONFIG_SOC for reducing code duplication Signed-off-by: Molly Sophia <mollysophia379@gmail.com>	2023-05-21 15:54:03 +08:00
Molly Sophia	cfdb896be5	Platforms: Add initial support for Radxa rock-5a What's working: - USB3 Ports - HDMI0 Output Note: On rock-5a the FSPI for SPI NOR is multiplexed with the eMMC module, so both are not configured yet. May try to add some autodetecting code later. Signed-off-by: Molly Sophia <mollysophia379@gmail.com>	2023-05-20 11:59:54 +08:00
Molly Sophia	694dfc8b25	Workflow: Add NanoPC T6 Signed-off-by: Molly Sophia <mollysophia379@gmail.com>	2023-05-14 14:18:23 +08:00
Sophon	f5e87e2230	Merge pull request #22 from MollySophia/molly/nanopc-t6 Platforms: Add initial support for NanoPC T6	2023-05-14 14:13:59 +08:00
Molly Sophia	b3abf83da7	Platforms: Add initial support for NanoPC T6 What's working: - Type-C and USB - HDMI0 Output - eMMC and SDHCI What's broken or untested: - Everything else Signed-off-by: Molly Sophia <mollysophia379@gmail.com>	2023-05-14 14:06:27 +08:00
Mario Bălănică	3676af4b37	Add Khadas Edge2 platform	2023-05-11 19:07:20 +03:00
Mario Bălănică	5570bf1348	Silicon/Rockchip: Delete Usb2PhySuspend() in RockchipPlatformLib Unused and actually enables the PHYs.	2023-05-02 04:07:38 +03:00
Mario Bălănică	4999bfad7d	Add Mekotronics R58 Mini platform The device is a trimmed down R58X. No PCIe / M.2 slots and SD expansion is completely missing.	2023-05-02 03:32:00 +03:00
Mario Bălănică	05f8cc20fc	Add Mekotronics R58X platform Everything currently supported works except for the micro SD card slot - no idea what it's connected to, no signs of life on either MSHC controller even in Maskrom mode.	2023-05-02 02:54:32 +03:00
Mario Bălănică	b88a32dd93	Fix and expose eMMC device in ACPI In preparation for Windows support.	2023-04-28 18:54:25 +03:00
Mario Bălănică	08c90b9eb2	Silicon/Rockchip: Improve eMMC detection	2023-04-28 18:49:29 +03:00
Mario Bălănică	6e88083971	Enable EMMC boot for platforms that support it	2023-04-21 22:17:17 +03:00
Mario Bălănică	f5895f0295	Silicon/Rockchip: Add card detection in SdhciHostDxe Adapted from ArasanMmcHostDxe. Fixes #17	2023-04-21 22:16:08 +03:00
Mario Bălănică	e62c694e7b	Add config options for CPU clock rates and voltages By default, clock rates are set to maximum and voltages are set depending on the clock. This behavior can be changed in the CPU Performance form (for platforms that have persistent NV support as of now). Clocks are set as soon as we get write access to the var store, however voltages will be set later on first notification of the ReadyToBoot event. This allows the user to dial settings back in case the values are too high and the system hangs or boot loops when loading the OS.	2023-04-20 12:14:15 +03:00
Mario Bălănică	fc1afc0b1e	Add identification tags to RK860X regulators	2023-04-20 09:55:08 +03:00
Mario Bălănică	b9857a812a	Minor refactoring for RockchipPlatformLib and I2cDxe	2023-04-17 05:16:35 +03:00
Mario Bălănică	bf4468e1b6	Add Firefly ROC-RK3588S-PC and Station M3 platforms Station M3 is basically a complete package (case, cooling, accessories) built around the ROC-RK3588S-PC board. We have a separate platform for it as it's sold under a different brand with its own logo and product name.	2023-04-17 03:15:55 +03:00
Mario Bălănică	c2b5ffd259	Silicon/Rockchip: Add SMBIOS PCDs for motherboard vendor and name	2023-04-17 03:15:54 +03:00
Mario Bălănică	1dd3e75ad5	Add miscellaneous init function for platforms	2023-04-17 03:15:33 +03:00
Mario Bălănică	a4bf6ae99f	Platform/IndiedroidNova: Enable & configure voltage regulators	2023-04-15 02:10:18 +03:00
Mario Bălănică	bf712b17d5	Silicon/Rockchip: More fixes for the regulator event handler	2023-04-14 23:13:57 +03:00
Mario Bălănică	15d6b7a31b	Silicon/Rockchip: Remove dependency on gRk860xRegulatorProtocolGuid In case some platforms don't have it configured yet.	2023-04-14 22:36:19 +03:00
Mario Bălănică	45c5c04c27	Platform/ROCK5B: Update RK806 voltages Little CPU cluster is set to maximum voltage for roughly 1.8 GHz.	2023-04-13 05:06:29 +03:00
Mario Bălănică	e2696f8a03	Platform/ROCK5B: Enable RK860X regulators for the big cores	2023-04-13 04:41:30 +03:00
Mario Bălănică	c6e85e2b93	Platform/OrangePi5: Enable RK860X regulators for the big cores	2023-04-13 04:36:55 +03:00
Mario Bălănică	eda397ef22	Silicon/Rockchip: Configure RK860X in RK3588Dxe	2023-04-13 04:20:19 +03:00
Mario Bălănică	d922f80d9a	Silicon/Rockchip: Add RK860X voltage regulator driver	2023-04-13 04:06:30 +03:00
Mario Bălănică	aa2637795f	Silicon/Rockchip: Move USB PHY setup back to UsbHcdInitDxe	2023-04-13 02:37:22 +03:00
Mario Bălănică	920a324046	Fix USB controller sizes and delete unused PCDs	2023-04-13 02:33:16 +03:00
Mario Bălănică	aaa4412ed6	Silicon/Rockchip: Create a protocol for OhciDxe We can initialize these controllers only after USB PHY setup, which happens in a driver that may load later. This also fixes the boot delay caused by storage devices being initially enumerated on OHCI (due to it loading earlier) and a second time on EHCI or XHCI.	2023-04-13 02:25:10 +03:00
WillzenZou	b808ae5d79	Platform/OrangePi5: Adjust the voltage to allow the CPU frequency to be normal and remove the PCIe3 initialisation until PCIe2 is supported. Note: Voltage reference from Orange Pi5's Linux device tree and schematic	2023-04-09 03:34:37 +03:00
Mario Bălănică	5468c3911b	workflows/build: Add indiedroid-nova	2023-04-08 16:22:34 +03:00
Mario Bălănică	d3fd20e064	Platform/IndiedroidNova: Add initial support Almost everything currently supported works, with the exception of SDMMC and possibly other things that require GPIO mux. We have no schematics for this board yet. Also known as 9Tripod Pico Pi V2.0.	2023-04-08 16:19:47 +03:00
Mario Bălănică	f3a02af3d3	Platform/ROCK5B: Remove vendor from platform name Fix "Radxa Radxa"	2023-04-06 21:54:03 +03:00
Mario Bălănică	b2a49eb86c	Silicon/Rockchip: Set ARM clocks to maximum	2023-04-06 21:22:21 +03:00
Mario Bălănică	1571a69925	Move RK806 init to RockchipPlatformLib	2023-04-06 20:27:35 +03:00
Mario Bălănică	519474e4ec	Move RK3588Dxe to Silicon/Rockchip/RK3588 All board-specific code should be moved to RockchipPlatformLib instead.	2023-04-06 20:23:25 +03:00
Mario Bălănică	f688ecb5c1	Move common ACPI tables to Silicon/Rockchip/RK3588	2023-04-05 20:34:26 +03:00
Mario Bălănică	d8fb4f170b	Update SMBIOS and share it between boards The serial number and SoC model are now read from OTP memory. CPU clock is read from SCMI but it may need some tweaking.	2023-04-05 02:19:47 +03:00
Mario Bălănică	9172e8a588	Silicon/Rockchip: Add RK3588 OTP library	2023-04-05 01:35:10 +03:00
Mario Bălănică	47ff4eb0fe	Platform/ROCK5B: Don't include SimpleInit.inc if it's disabled	2023-04-02 20:41:49 +03:00
Mario Bălănică	c56ba68db8	Delete ROCK5B and OrangePi5 package declarations We don't need them anymore.	2023-04-02 20:12:43 +03:00
Mario Bălănică	3a940530c8	Delete our Dw8250SerialPortLib fork and use Hisilicon's instead	2023-04-02 20:10:15 +03:00
Mario Bălănică	ca9f78d422	Move ROCK5B's GpioLib to Silicon/Rockchip/RK3588	2023-04-02 19:51:38 +03:00
Mario Bălănică	42fd558d61	Move ROCK5B's RkMtlLib to Silicon/Rockchip	2023-04-02 19:29:07 +03:00
Mario Bălănică	4fdc21d1f5	Move ROCK5B's maskrom app to Silicon/Rockchip	2023-04-02 19:21:05 +03:00
Mario Bălănică	ec0751ff07	Move ROCK5B's MemoryInitPeiLib to Silicon/Rockchip/RK3588	2023-04-02 19:09:04 +03:00
Mario Bălănică	9b28318d67	Move ROCK5B's ResetSystemLib to Silicon/Rockchip	2023-04-02 18:32:35 +03:00
Mario Bălănică	b6b21196b1	Move ROCK5B's DwEmmcDxe to Silicon/Rockchip/RK3588	2023-04-02 18:23:25 +03:00
Mario Bălănică	8b86613593	Move plat CruLib and Sdhci helper to Silicon/Rockchip/RK3588	2023-04-02 17:56:52 +03:00
Mario Bălănică	70067ff9ba	Silicon/Rockchip: Remove stale boot options in PlatformBootManagerLib Fixes #16	2023-04-02 01:02:22 +03:00
Mario Bălănică	14296a2d03	Silicon/Rockchip: Delete unused BmcConfigBootLib	2023-04-02 00:32:38 +03:00
Mario Bălănică	760f28cf7c	Move ROCK5B's PlatformBootManagerLib to Silicon/Rockchip	2023-04-02 00:24:57 +03:00
Xilin Wu	a92e99261c	Make simple-init optional	2023-03-28 09:44:38 +08:00
Xilin Wu	91fcaad18f	rock-5b: Enable FvSimpleFileSystemDxe	2023-03-28 09:23:36 +08:00
WillzenZou	f0bf08d7a2	Platform/OrangePi5: Support SD card boot and expose microSD socket via ACPI. From the efforts of @Googulator.	2023-03-27 23:05:49 +03:00
WillzenZou	6d0fe9b99d	Replace mkimage binary form rockchip's uboot sources to fix "libc.so.6: version `GLIBC_2.34' not found" when build in ubuntu 20.04. It might be better to integrate the source code of mkimage in rockchip's uboot.	2023-03-27 23:05:49 +03:00
WillzenZou	1832e267aa	Platform/OrangePi5: Add OrangePi Logo.	2023-03-27 23:05:49 +03:00
Mario Bălănică	a7c9207fc3	workflows/build: Switch to actions/checkout@v3 Silence warnings.	2023-03-26 04:31:28 +03:00
Mario Bălănică	8bb27dd77e	Update workflows This will build all platforms and configurations on every push or pull request to master. Creating version tags will rebuild and draft a new release.	2023-03-26 02:22:57 +02:00
Mario Bălănică	f386fdb548	Enable USB PHYs a bit earlier and re-enable OhciDxe There's no clear dependency set here. It may be better to register a protocol for this instead.	2023-03-25 00:52:04 +02:00
Mario Bălănică	8249a40916	Platform/OrangePi5: Add memory detection	2023-03-24 19:14:23 +02:00
Mario Bălănică	45e5744a13	Move ROCK5B's ArmPlatformLib to Silicon/Rockchip/RK3588	2023-03-24 18:45:31 +02:00
Sophon	b8f77ee0a4	Merge pull request #12 from amazingfate/github-workflow	2023-03-24 17:48:07 +08:00
amazingfate	d0bff2a5ea	workflow: fix git submodule init	2023-03-24 04:51:51 +00:00
amazingfate	95c272d4f2	workflow: fix dep gcc-aarch64-linux-gnu	2023-03-24 04:46:38 +00:00
amazingfate	478e247519	add missing dep gettext	2023-03-24 04:43:29 +00:00
amazingfate	8255f785af	add test branch to workflow	2023-03-24 04:40:53 +00:00
amazingfate	f361f2e655	add github workflow build	2023-03-24 04:39:37 +00:00
Mario Bălănică	6a38289140	Silicon/Rockchip: Fix Rk3588 case sensitivity issue	2023-03-24 04:20:52 +02:00
Googulator	810662b1b0	Rock 5B: Add bad memory ranges from upstream u-boot On 16GB Rock 5Bs, memory ranges 0x3FC000000-0x3FC500000 and 0x3FFF00000-0x400000000 cause a SError when accessed. Enabling full 16GB support exposed this issue. TODO: Figure out why BSP u-boot is not affected by this (is it already blacklisting these ranges?)	2023-03-23 04:35:42 +01:00
Googulator	32417bc583	Merge pull request #11 from Googulator/master Rock 5B: Autodetect memory size	2023-03-23 04:08:55 +01:00
Googulator	2b04205689	Rock 5B: Autodetect memory size Get rid of the hardcoded 8GB value. SdramLib is intended to be generic, but the base address & bank count are still defined in code. They will need to be converted to PCDs to be truly generic.	2023-03-23 04:06:38 +01:00
Xilin Wu	e206e0606d	ACPI IORT: Set CCA to 0 PCIe is not cache coherent on rk3588	2023-03-22 18:05:48 +08:00
Sophon	ec58d6f883	Merge pull request #10 from Googulator/master	2023-03-22 14:24:51 +08:00
Googulator	26a5d60c67	Expose microSD socket via ACPI Unfortunately this is not SDHCI or even anything similar, so a custom driver will be required.	2023-03-22 05:45:23 +01:00
Googulator	6ca88e897d	Rock 5B: Support SD card boot Currently, this is done using a forked version of DwEmmcDxe, due to clock handling differences between RK3568 and RK3588 (on RK3588, the SD interface clock is managed by SCMI). The driver name is confusing - DwEmmcDxe is for the SD socket, while SdhciHostDxe is for the eMMC socket. Unfortunately eMMC boot cannot be enabled, because SdhciHostDxe softlocks if it cannot detect a plugged-in eMMC, instead of allowing fallback to another boot device.	2023-03-22 04:38:33 +01:00
Googulator	78cd614959	Rock 5B: Stop pretending to be Hikey	2023-03-21 22:52:58 +01:00
Googulator	1760d7fb5b	Rock 5B: Set combo PHY #0 to PCIE On the Rock 5B, Combo PHYs #0 and #1 are used for PCIE, while #2 serves the top USB 3.0 Type A port. SATA is not accessible, except via a special M.2 breakout adapter, which connects to PHY #1. Therefore, setting PHY #0 to SATA makes no sense. (In the future, PHY #1 should be made configurable in the firmware menu, to enable using the M.2 -> SATA adapter.)	2023-03-21 22:22:31 +01:00
Googulator	0839d43c7a	Remove more GMAC code for Rock 5B	2023-03-21 22:07:14 +01:00
Googulator	7253525eb2	Remove GMAC init for Rock 5B The GMAC interface is not used for Ethernet on Rock 5B. Instead, a PCIE-based 2.5GBASE-T Ethernet solution is used.	2023-03-21 22:06:22 +01:00
Googulator	80e8b8ee84	Merge pull request #1 from mariobalanica/master Merge Mario's logo changes	2023-03-21 21:58:56 +01:00
WillzenZou	6761759867	Platform/OrangePi5: Initial support for OPi5 notes: just turned off the pcie3x4 and changed some names.	2023-03-17 21:09:17 +02:00
Mario Bălănică	5eb829c872	Platform/Radxa: Add LogoDxe	2023-03-17 20:22:21 +02:00