Platform/ROCK5B: Remove vendor from platform name

Fix "Radxa Radxa"

.github/workflows/build.yml

@@ -0,0 +1,56 @@
+name: Build
+on:
+  push:
+    branches:
+      - master
+  pull_request:
+    branches:
+      - master
+  workflow_call:
+
+jobs:
+  build:
+    runs-on: ubuntu-latest
+    strategy:
+      matrix:
+        PLATFORM: [rock-5b, orangepi-5] # rk3588-evb is currently failing
+        CONFIGURATION: [Debug, Release]
+    steps:
+      - name: Checkout
+        uses: actions/checkout@v3
+      - name: Submodule init
+        shell: bash
+        run: git submodule update --init --recursive
+        
+      - name: Install dependencies
+        shell: bash
+        run: |
+          sudo apt-get install -y \
+          acpica-tools \
+          binutils-aarch64-linux-gnu \
+          build-essential \
+          device-tree-compiler \
+          gettext \
+          git \
+          gcc-aarch64-linux-gnu \
+          libc6-dev-arm64-cross \
+          python3 \
+          python3-pyelftools
+          
+      - name: Get version tag
+        id: get_version_tag
+        shell: bash
+        run: echo "version=$(git describe --tags --always)" >> $GITHUB_OUTPUT
+        
+      - name: Build platform
+        shell: bash
+        run: |  
+         ./build.sh --device ${{matrix.PLATFORM}} --release ${{matrix.CONFIGURATION}}
+          mv RK3588_NOR_FLASH.img ${{matrix.PLATFORM}}_UEFI_${{matrix.CONFIGURATION}}_${{steps.get_version_tag.outputs.version}}.img
+        
+      - name: Upload artifact
+        uses: actions/upload-artifact@v3
+        with:
+          name: ${{matrix.PLATFORM}} UEFI ${{matrix.CONFIGURATION}} image
+          path: ./*.img
+          if-no-files-found: error

.github/workflows/release.yml

@@ -0,0 +1,34 @@
+name: Release
+on:  
+  push:
+    tags:
+      - '*'
+      
+jobs:
+  build_for_release:
+    uses: ./.github/workflows/build.yml
+  
+  release:
+    runs-on: ubuntu-latest
+    needs: build_for_release
+    permissions:
+      contents: write
+    steps:
+      - name: Download all workflow run artifacts
+        uses: actions/download-artifact@v3
+          
+      - name: Create release
+        uses: softprops/action-gh-release@v1
+        with:
+          draft: true
+          prerelease: false
+          files: "*/*Release*.img"
+          fail_on_unmatched_files: true
+          generate_release_notes: true
+          append_body: true
+          body: |
+            ## Usage
+            Flash the board-specific image to SPINOR with rkdevtool / rkdeveloptool or to an EMMC / SD card.
+            If your board is not yet supported, using a similar image may work but beware of potential issues.
+
+            Debug builds can be found in the artifacts of the workflow run for this release.

build.sh

@@ -8,6 +8,7 @@ function _help(){
 	echo "Options: "
 	echo "	--device DEV, -d DEV:    build for DEV."
 	echo "	--all, -a:               build all devices."
+	echo "	--gui:                   Enable simple-init GUI."
 	echo "	--release MODE, -r MODE: Release mode for building, default is 'DEBUG', 'RELEASE' alternatively."
 	echo "	--toolchain TOOLCHAIN:   Set toolchain, default is 'GCC5'."
 	echo " 	--skip-rootfs-gen:       skip generating SimpleInit rootfs to speed up building."
@@ -109,6 +110,7 @@ function _build(){
 		-p "${ROOTDIR}/${DSC_FILE}" \
 		-b "${_MODE}" \
 		-D FIRMWARE_VER="${GITCOMMIT}" \
+		-D ENABLE_SIMPLE_INIT="${BUILD_GUI}" \
 		||return "$?"
 
 	_pack
@@ -133,7 +135,8 @@ DISTCLEAN=false
 TOOLCHAIN=GCC5
 export ROOTDIR OUTDIR
 export GEN_ROOTFS=true
-OPTS="$(getopt -o t:d:haCDO:r -l toolchain:,device:,help,all,skip-rootfs-gen,clean,distclean,outputdir:,release: -n 'build.sh' -- "$@")"||exit 1
+export BUILD_GUI=false
+OPTS="$(getopt -o t:d:haCDO:r -l toolchain:,device:,help,all,skip-rootfs-gen,gui,clean,distclean,outputdir:,release: -n 'build.sh' -- "$@")"||exit 1
 eval set -- "${OPTS}"
 while true
 do	case "${1}" in
@@ -143,6 +146,7 @@ do	case "${1}" in
 		-D|--distclean) DISTCLEAN=true;shift;;
 		-O|--outputdir) OUTDIR="${2}";shift 2;;
 		--skip-rootfs-gen) GEN_ROOTFS=false;shift;;
+		--gui) BUILD_GUI=true;shift;;
 		-r|--release) MODE="${2}";shift 2;;
 		-t|--toolchain) TOOLCHAIN="${2}";shift 2;;
 		-h|--help) _help 0;shift;;

configs/orangepi-5.conf

@@ -0,0 +1,3 @@
+DSC_FILE=edk2-platforms/Platform/OrangePi/OrangePi5/OrangePi5.dsc
+PLATFORM_NAME=OrangePi5
+SOC=RK3588

edk2-platforms/Platform/OrangePi/Drivers/LogoDxe/Logo.c

@@ -0,0 +1,144 @@
+/** @file
+  Logo DXE Driver, install Edkii Platform Logo protocol.
+
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+  Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Protocol/HiiDatabase.h>
+#include <Protocol/GraphicsOutput.h>
+#include <Protocol/HiiImageEx.h>
+#include <Protocol/PlatformLogo.h>
+#include <Protocol/HiiPackageList.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+
+typedef struct {
+  EFI_IMAGE_ID                          ImageId;
+  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
+  INTN                                  OffsetX;
+  INTN                                  OffsetY;
+} LOGO_ENTRY;
+
+STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
+STATIC EFI_HII_HANDLE            mHiiHandle;
+STATIC LOGO_ENTRY                mLogos[] = {
+  {
+    IMAGE_TOKEN (IMG_LOGO),
+    EdkiiPlatformLogoDisplayAttributeCenter,
+    0,
+    0
+  }
+};
+
+/**
+  Load a platform logo image and return its data and attributes.
+
+  @param This              The pointer to this protocol instance.
+  @param Instance          The visible image instance is found.
+  @param Image             Points to the image.
+  @param Attribute         The display attributes of the image returned.
+  @param OffsetX           The X offset of the image regarding the Attribute.
+  @param OffsetY           The Y offset of the image regarding the Attribute.
+
+  @retval EFI_SUCCESS      The image was fetched successfully.
+  @retval EFI_NOT_FOUND    The specified image could not be found.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GetImage (
+  IN     EDKII_PLATFORM_LOGO_PROTOCOL          *This,
+  IN OUT UINT32                                *Instance,
+     OUT EFI_IMAGE_INPUT                       *Image,
+     OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
+     OUT INTN                                  *OffsetX,
+     OUT INTN                                  *OffsetY
+  )
+{
+  UINT32 Current;
+
+  if (Instance == NULL || Image == NULL ||
+      Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Current = *Instance;
+  if (Current >= ARRAY_SIZE (mLogos)) {
+    return EFI_NOT_FOUND;
+  }
+
+  (*Instance)++;
+  *Attribute = mLogos[Current].Attribute;
+  *OffsetX   = mLogos[Current].OffsetX;
+  *OffsetY   = mLogos[Current].OffsetY;
+
+  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
+                        mLogos[Current].ImageId, Image);
+}
+
+STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+  GetImage
+};
+
+/**
+  Entrypoint of this module.
+
+  This function is the entrypoint of this module. It installs the Edkii
+  Platform Logo protocol.
+
+  @param  ImageHandle       The firmware allocated handle for the EFI image.
+  @param  SystemTable       A pointer to the EFI System Table.
+
+  @retval EFI_SUCCESS       The entry point is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeLogo (
+  IN EFI_HANDLE               ImageHandle,
+  IN EFI_SYSTEM_TABLE         *SystemTable
+  )
+{
+  EFI_STATUS                  Status;
+  EFI_HII_PACKAGE_LIST_HEADER *PackageList;
+  EFI_HII_DATABASE_PROTOCOL   *HiiDatabase;
+  EFI_HANDLE                  Handle;
+
+  Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
+                  (VOID **) &HiiDatabase);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
+                  (VOID **) &mHiiImageEx);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Retrieve HII package list from ImageHandle
+  //
+  Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
+                  (VOID **) &PackageList, ImageHandle, NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR,
+      "HII Image Package with logo not found in PE/COFF resource section\n"));
+    return Status;
+  }
+
+  //
+  // Publish HII package list to HII Database.
+  //
+  Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
+                          &mHiiHandle);
+  if (!EFI_ERROR (Status)) {
+    Handle = NULL;
+    Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
+                    &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
+  }
+  return Status;
+}

edk2-platforms/Platform/OrangePi/Drivers/LogoDxe/Logo.idf

@@ -0,0 +1,10 @@
+// @file
+// Platform Logo image definition file.
+//
+// Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+// Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+
+#image IMG_LOGO Logo.bmp

edk2-platforms/Platform/OrangePi/Drivers/LogoDxe/LogoDxe.inf

@@ -0,0 +1,48 @@
+## @file
+#  The default logo bitmap picture shown on setup screen.
+#
+#  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+#  Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = LogoDxe
+  FILE_GUID                      = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = InitializeLogo
+#
+#  This flag specifies whether HII resource section is generated into PE image.
+#
+  UEFI_HII_RESOURCE_SECTION      = TRUE
+
+[Sources]
+  Logo.bmp
+  Logo.c
+  Logo.idf
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  DebugLib
+
+[Protocols]
+  gEfiHiiDatabaseProtocolGuid        ## CONSUMES
+  gEfiHiiImageExProtocolGuid         ## CONSUMES
+  gEfiHiiPackageListProtocolGuid     ## PRODUCES CONSUMES
+  gEdkiiPlatformLogoProtocolGuid     ## PRODUCES
+
+[Depex]
+  gEfiHiiDatabaseProtocolGuid AND
+  gEfiHiiImageExProtocolGuid

edk2-platforms/Platform/OrangePi/OrangePi5/AcpiTables/AcpiTables.inf

@@ -0,0 +1,64 @@
+#/** @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2019-2021, ARM Limited. All rights reserved.
+#  Copyright (c) Microsoft Corporation. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+  RK_COMMON_ACPI_DIR             = Silicon/Rockchip/RK3588/AcpiTables
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+
+[Sources]
+  Dsdt.asl
+  $(RK_COMMON_ACPI_DIR)/Madt.aslc
+  $(RK_COMMON_ACPI_DIR)/Fadt.aslc
+  $(RK_COMMON_ACPI_DIR)/Gtdt.aslc
+  $(RK_COMMON_ACPI_DIR)/Spcr.aslc
+  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
+  $(RK_COMMON_ACPI_DIR)/RK3588PcieIort.aslc
+  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Rockchip/RockchipPkg.dec
+  Platform/Rockchip/RK3588/RK3588.dec
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase

edk2-platforms/Platform/OrangePi/OrangePi5/AcpiTables/Dsdt.asl

@@ -0,0 +1,38 @@
+/** @file
+ *
+ *  Differentiated System Definition Table (DSDT)
+ *
+ *  Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ *  Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
+ *  Copyright (c) Microsoft Corporation. All rights reserved.
+ *  Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include "AcpiTables.h"
+
+DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
+{
+  Scope (\_SB_)
+  {
+    include ("Cpu.asl")
+
+    // include ("Pcie.asl")
+    // include ("Sata.asl")
+    // include ("Emmc.asl")
+    include ("Sdhc.asl")
+    // include ("Gmac.asl")
+    // include ("Gpio.asl")
+    // include ("I2c.asl")
+    include ("Uart.asl")
+    // include ("Spi.asl")
+
+    // won't work on Windows, will trigger bugcheck by usbehci
+    // include ("Usb2.asl")
+
+    include ("Usb3Host0.asl")
+    include ("Usb3Host2.asl")
+  }
+}

edk2-platforms/Platform/OrangePi/OrangePi5/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -0,0 +1,323 @@
+/** @file
+*
+*  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include <Base.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/GpioLib.h>
+#include <Library/RK806.h>
+#include <Soc.h>
+
+static struct regulator_init_data rk806_init_data[] = {
+  /* Master PMIC */
+
+  /* TODO: Figure out the correct voltages
+
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK2, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1100000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 900000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 850000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  */
+
+  /* No dual PMICs on this platform */
+};
+
+void DebugPrintHex(void *buf, UINT32 width, UINT32 len)
+{
+  UINT32 i,j;
+  UINT8 *p8 = (UINT8 *) buf;
+  UINT16 *p16 = (UINT16 *) buf;
+  UINT32 *p32 =(UINT32 *) buf;
+
+  j = 0;
+  for (i = 0; i < len; i++) {
+    if (j == 0) {
+      DebugPrint(DEBUG_ERROR, "%p + 0x%x:",buf, i * width);
+    }
+
+    if (width == 4) {
+      DebugPrint(DEBUG_ERROR, "0x%08x,", p32[i]);
+    } else if (width == 2) {
+      DebugPrint(DEBUG_ERROR, "0x%04x,", p16[i]);
+    } else {
+      DebugPrint(DEBUG_ERROR, "0x%02x,", p8[i]);
+    }
+
+    if (++j >= (16/width)) {
+      j = 0;
+      DebugPrint(DEBUG_ERROR, "\n","");
+    }
+  }
+  DebugPrint(DEBUG_ERROR, "\n","");
+}
+
+void
+EFIAPI
+DwEmmcDxeIoMux(void)
+{
+  /* sdmmc0 iomux */
+}
+
+void
+EFIAPI
+SdhciEmmcDxeIoMux(void)
+{
+  /* sdmmc0 iomux */
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+}
+
+#define NS_CRU_BASE         0xFD7C0000
+#define CRU_CLKSEL_CON59    0x03EC
+#define CRU_CLKSEL_CON78    0x0438
+
+void
+EFIAPI
+Rk806SpiIomux(void)
+{
+  /* io mux */
+  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
+  PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+}
+
+VOID
+EFIAPI
+Rk806Configure(
+  VOID
+)
+{
+  UINTN RegCfgIndex;
+
+  RK806Init();
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
+    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+}
+
+void
+EFIAPI
+NorFspiIomux(void)
+{
+  /* io mux */
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
+             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
+#define FSPI_M1
+#if defined(FSPI_M0)
+   /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
+#elif defined(FSPI_M1)
+  /*FSPI M1*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
+#else
+  /*FSPI M2*/
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
+#endif
+}
+
+void
+EFIAPI
+GmacIomux (
+   UINT32 id
+)
+{
+  switch (id) {
+  case 0:
+    /* gmac0 iomux */
+    BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+    BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+    BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+    BUS_IOC->GPIO2C_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+    BUS_IOC->GPIO4C_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0100;
+    BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011;
+    break;
+  case 1:
+    /* gmac1 iomux */
+    break;
+  default:
+    break;
+  }
+}
+
+void
+EFIAPI
+NorFspiEnableClock (
+  UINT32 *CruBase
+)
+{
+  UINTN BaseAddr = (UINTN) CruBase;
+
+  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+}
+
+UINT32
+EFIAPI
+I2cGetBase (
+   UINT32 id
+)
+{
+  UINT32 Base = 0;
+
+  switch (id) {
+  case 0:
+    Base = 0xFD880000;
+    break;
+  case 1:
+    Base = 0xFEA90000;
+    /* io mux */
+    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
+    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
+    break;
+  case 2:
+    Base = 0xFEAA0000;
+    /* io mux */
+    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
+    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
+    PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
+    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    break;
+  case 3:
+    Base = 0xFEAB0000;
+    break;
+  case 4:
+    Base = 0xFEAC0000;
+    break;
+  case 5:
+    Base = 0xFEAD0000;
+    break;
+  default:
+    break;
+  }
+
+  return Base;
+}
+
+#define GPIO4_BASE         0xFEC50000
+#define GPIO_SWPORT_DR_L   0x0000
+#define GPIO_SWPORT_DR_H   0x0004
+#define GPIO_SWPORT_DDR_L  0x0008
+#define GPIO_SWPORT_DDR_H  0x000C
+
+void
+EFIAPI
+UsbPortPowerEnable (void)
+{
+  DEBUG((EFI_D_WARN, "UsbPortPowerEnable called\n"));
+  /* Set GPIO3 PC0 (TYPEC_EN) output high to power Type-C/USB2.0 ports */
+  GpioPinWrite (3, GPIO_PIN_PC0, TRUE);
+  GpioPinSetDirection (3, GPIO_PIN_PC0, GPIO_PIN_OUTPUT);
+
+  // DEBUG((EFI_D_WARN, "Trying to enable green led\n"));
+  // GpioPinWrite (1, GPIO_PIN_PA2, TRUE);
+  // GpioPinSetDirection (1, GPIO_PIN_PA2, GPIO_PIN_OUTPUT);
+}
+
+void
+EFIAPI
+Usb2PhySuspend (void)
+{
+  MmioWrite32(0xfd5d4008, 0x20000000);
+  MmioWrite32(0xfd5d8008, 0x20000000);
+  MmioWrite32(0xfd5dc008, 0x20000000);
+}
+
+void
+EFIAPI
+Usb2PhyResume (void)
+{
+  MmioWrite32(0xfd5d0008, 0x20000000);
+  MmioWrite32(0xfd5d4008, 0x20000000);
+  MmioWrite32(0xfd5d8008, 0x20000000);
+  MmioWrite32(0xfd5dc008, 0x20000000);
+  MmioWrite32(0xfd7f0a10, 0x07000700);
+  MmioWrite32(0xfd7f0a10, 0x07000000);
+}
+
+void
+EFIAPI
+UsbDpPhyEnable (void)
+{
+  /* enable rx_lfps_en & usbdp_low_pwrn */
+  MmioWrite32(0xfd5c8004, 0x60006000);
+  MmioWrite32(0xfd5cc004, 0x60006000);
+  
+  /* remove rx-termination, we don't support SS yet */
+  MmioWrite32 (0xfd5c800c, 0x00030001);
+  MmioWrite32 (0xfd5cc00c, 0x00030001);
+}
+
+void
+EFIAPI
+Dwc3Force20ClkFor30Clk (UINT32 Address, BOOLEAN enable)
+{
+  UINT32 Reg;
+
+  if (enable) {
+    Reg = MmioRead32(Address);
+    Reg |= (1 << 26);
+    MmioWrite32((Address), Reg);
+  } else {
+    Reg = MmioRead32(Address);
+    Reg &= ~(1 << 26);
+    MmioWrite32(Address, Reg);
+  }
+}
+
+void
+EFIAPI
+Pcie30IoInit(void)
+{
+  /* Set reset and power IO to gpio output mode */
+  GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
+  GpioPinSetDirection (1, GPIO_PIN_PA4, GPIO_PIN_OUTPUT);
+}
+
+void
+EFIAPI
+Pcie30PowerEn(void)
+{
+  /* output high to enable power */
+  GpioPinWrite (1, GPIO_PIN_PA4, TRUE);
+}
+
+void
+EFIAPI
+Pcie30PeReset(BOOLEAN enable)
+{
+  if(enable)
+    GpioPinWrite (4, GPIO_PIN_PB6, FALSE); /* output low */
+  else
+    GpioPinWrite (4, GPIO_PIN_PB6, TRUE); /* output high */
+}
+

edk2-platforms/Platform/OrangePi/OrangePi5/Library/RockchipPlatformLib/RockchipPlatformLib.inf

@@ -0,0 +1,43 @@
+#
+#  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = RockchipPlatformLib
+  FILE_GUID                      = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RockchipPlatformLib
+  RKPLATLIB_COMMON_DIR           = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Platform/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  SerialPortLib
+  CruLib
+  GpioLib
+
+[Sources.common]
+  RockchipPlatformLib.c
+  $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c
+  $(RKPLATLIB_COMMON_DIR)/RockchipSdhci.c
+
+[Sources.AARCH64]
+
+[Pcd]
+  gRockchipTokenSpaceGuid.PcdSdhciDxeBaseAddress
+  gRockchipTokenSpaceGuid.PcdI2cBusCount
+

edk2-platforms/Platform/OrangePi/OrangePi5/OrangePi5.dsc

@@ -0,0 +1,593 @@
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2021-2022, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = OrangePi5
+  PLATFORM_GUID                  = d080df36-45e7-11ec-9726-f42a7dcb925d
+  PLATFORM_VERSION               = 0.2
+  DSC_SPECIFICATION              = 0x00010019
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = Platform/OrangePi/OrangePi5/OrangePi5.fdf
+
+  DEFINE CONFIG_NO_DEBUGLIB      = TRUE
+
+  DEFINE CP_UNCONNECTED    = 0x0
+  DEFINE CP_PCIE           = 0x01
+  DEFINE CP_SATA           = 0x10
+  DEFINE CP_USB3           = 0x20
+
+  #
+  # Network definition
+  #
+  DEFINE NETWORK_SNP_ENABLE             = FALSE
+  DEFINE NETWORK_IP6_ENABLE             = FALSE
+  DEFINE NETWORK_TLS_ENABLE             = FALSE
+  DEFINE NETWORK_HTTP_BOOT_ENABLE       = FALSE
+  DEFINE NETWORK_ISCSI_ENABLE           = FALSE
+  DEFINE NETWORK_VLAN_ENABLE            = FALSE
+!include Silicon/Rockchip/Rockchip.dsc.inc
+!include MdePkg/MdeLibs.dsc.inc
+
+[LibraryClasses.common]
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmPlatformLib|Silicon/Rockchip/RK3588/Library/PlatformLib/PlatformLib.inf
+  AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf
+  CruLib|Silicon/Rockchip/Library/CruLib/CruLib.inf
+
+  DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
+
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+  # UiApp dependencies
+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+
+  #RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+  TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
+
+  # USB Requirements
+  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+
+  # PCIe
+  PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+  #PciHostBridgeLib|Silicon/Rockchip/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+  #PciExpressLib|Silicon/Rockchip/Library/PciExpressLib/PciExpressLib.inf
+  PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+
+
+  # VariableRuntimeDxe Requirements
+  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+  AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+  TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+  VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+
+  AndroidBootImgLib|edk2/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.inf
+
+  RockchipDisplayLib|Silicon/Rockchip/Library/DisplayLib/RockchipDisplayLib.inf
+
+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+  LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf
+
+  # OTP Library
+  OtpLib|Silicon/Rockchip/RK3588/Library/OtpLib/OtpLib.inf
+
+  #
+  # Custom libraries
+  #
+  RockchipPlatformLib|Platform/OrangePi/OrangePi5/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+  ResetSystemLib|Silicon/Rockchip/Library/ResetSystemLib/ResetSystemLib.inf
+  PlatformBootManagerLib|Silicon/Rockchip/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+  SerialPortLib|Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf
+  GpioLib|Silicon/Rockchip/RK3588/Library/GpioLib/GpioLib.inf
+  # SCMI Mailbox Transport Layer
+  ArmMtlLib|Silicon/Rockchip/Library/RkMtlLib/RkMtlLib.inf
+
+[LibraryClasses.common.SEC]
+  PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+  ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+  HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
+  MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+  MemoryInitPeiLib|Silicon/Rockchip/RK3588/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
+  PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+  PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+  RockchipPlatformLib|Platform/OrangePi/OrangePi5/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+
+[BuildOptions]
+  GCC:*_*_*_PLATFORM_FLAGS = -I$(WORKSPACE)/Silicon/Rockchip/RK3588/Include -I$(WORKSPACE)/Platform/Rockchip/RK3588/Include -I$(WORKSPACE)/Silicon/Rockchip/Include
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+  #  If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+  #  It could be set FALSE to save size.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+
+[PcdsFixedAtBuild.common]
+  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)"
+
+  # System Memory (1GB)
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000
+  gRK3588TokenSpaceGuid.PcdTotalMemorySize|0x200000000
+  
+  # RK3588 CPU profile
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|8
+  gArmPlatformTokenSpaceGuid.PcdClusterCount|1
+
+  # SMBIOS platform config
+  gRockchipTokenSpaceGuid.PcdPlatformName|"Orange Pi 5"
+  gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Orange Pi"
+  gRockchipTokenSpaceGuid.PcdFamilyName|"Orange Pi 5"
+  gRockchipTokenSpaceGuid.PcdProductUrl|"http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-5.html"
+  gRockchipTokenSpaceGuid.PcdMemoryVendorName|"TBD"
+
+  # I2C
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x51 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x2 }
+  gRockchipTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x2 }
+  gRockchipTokenSpaceGuid.PcdI2cClockFrequency|198000000
+  gRockchipTokenSpaceGuid.PcdI2cBaudRate|100000
+  gRockchipTokenSpaceGuid.PcdI2cBusCount|1
+  gRockchipTokenSpaceGuid.PcdI2cDemoAddresses|{ 0x51 } #/* RTCYM8563TS 0x51@bus2 */
+  gRockchipTokenSpaceGuid.PcdI2cDemoBuses|{ 0x2 }
+
+  ## UART2 - Serial Terminal
+  DEFINE SERIAL_BASE = 0xFEB50000 # UART2
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|$(SERIAL_BASE)
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|1500000
+  gHisiTokenSpaceGuid.PcdSerialPortSendDelay|500000
+  gHisiTokenSpaceGuid.PcdUartClkInHz|24000000
+
+  ## SPI - SPI2 for test
+  gRockchipTokenSpaceGuid.SpiTestBaseAddr|0xFEB20000
+  gRockchipTokenSpaceGuid.SpiRK806BaseAddr|0xFEB20000
+  ## PL031 RealTimeClock
+  #gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0xF8003000
+
+  ## NOR FLASH
+  gRockchipTokenSpaceGuid.FspiBaseAddr|0xFE2B0000
+
+  ## CRU
+  gRockchipTokenSpaceGuid.CruBaseAddr|0xFD7C0000
+
+  #gRockchipTokenSpaceGuid.PcdSpiVariableOffset|0x3C0000
+  #
+  # ARM General Interrupt Controller
+  #
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0xfe600000
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xfe600000
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0xfe680000
+
+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3
+
+  # GUID of the UI app
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+
+  gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
+
+  #
+  # DW SD card controller
+  #
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeBaseAddress|0xfe2c0000
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz|100000000
+  gDesignWareTokenSpaceGuid.PcdDwPermitObsoleteDrivers|TRUE
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeFifoDepth|256
+  #
+  # SDHCI controller
+  #
+  gRockchipTokenSpaceGuid.PcdSdhciDxeBaseAddress|0xfe2e0000
+
+  #
+  # PCIe controller
+  #
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress|0xfe150000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress|0xf5000000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress|0xf0000000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize|0x100000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress|0xf0100000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize|0x10000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress|0xf0200000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize|0xe00000
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64|0x901000000 #deduct 0x1000000 ECAM space
+  gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64|0x3f000000
+
+  #
+  # Fastboot
+  #
+  gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbVendorId|0x2207
+  gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbProductId|0x0001
+
+  #
+  # USB OHCI controller
+  #
+  gRockchipTokenSpaceGuid.PcdOhciBaseAddress|0xfc840000
+  gRockchipTokenSpaceGuid.PcdNumOhciController|2
+  gRockchipTokenSpaceGuid.PcdOhciSize|0x80000
+
+  #
+  # USB2 EHCI controller
+  #
+  gRockchipTokenSpaceGuid.PcdEhciBaseAddress|0xfc800000
+  gRockchipTokenSpaceGuid.PcdNumEhciController|2
+  gRockchipTokenSpaceGuid.PcdEhciSize|0x80000
+
+  #
+  # DWC3 controller
+  #
+  gRockchipTokenSpaceGuid.PcdDwc3BaseAddresses|{ UINT32(0xfc000000), UINT32(0xfc400000), UINT32(0xfcd00000) }
+  gRockchipTokenSpaceGuid.PcdDwc3Size|0x400000
+
+  #
+  # Android Loader
+  #
+  gRK3588TokenSpaceGuid.PcdAndroidBootDevicePath|L"\\EFI\\BOOT\\GRUBAA64.EFI"
+  gRK3588TokenSpaceGuid.PcdSdBootDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00E023F70000000000)/SD(0x0)"
+  gRK3588TokenSpaceGuid.PcdKernelBootArg|L"earlycon=uart8250,mmio32,0xfeb50000 root=PARTUUID=614e0000-0000 rw rootwait"
+  gEmbeddedTokenSpaceGuid.PcdAndroidBootDevicePath|L"VenHw(100C2CFA-B586-4198-9B4C-1683D195B1DA)/HD(3,GPT,7A3F0000-0000-446A-8000-702F00006273,0x8000,0x20000)"
+  #
+  # Make VariableRuntimeDxe work at emulated non-volatile variable mode.
+  #
+  gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
+
+  # ACPI Enable
+  gRK3588TokenSpaceGuid.AcpiEnable|TRUE
+
+  #
+  # Display
+  #
+  gRockchipTokenSpaceGuid.PcdLcdPixelFormat|0x00000001
+  gRockchipTokenSpaceGuid.PcdEdpId|0x00000000 #edp0
+  #gRockchipTokenSpaceGuid.PcdEdpId|0x00000001 #edp1
+  gRockchipTokenSpaceGuid.PcdHdmiId|0x00000000 #hdmi0
+  #gRockchipTokenSpaceGuid.PcdHdmiId|0x00000001 #hdmi1
+
+  #
+  # ComboPhy
+  #
+  gRockchipTokenSpaceGuid.PcdComboPhyMode|{ $(CP_SATA), $(CP_PCIE), $(CP_USB3) }
+
+  #  BIT0  - Initialization message.<BR>
+  #  BIT1  - Warning message.<BR>
+  #  BIT2  - Load Event message.<BR>
+  #  BIT3  - File System message.<BR>
+  #  BIT4  - Allocate or Free Pool message.<BR>
+  #  BIT5  - Allocate or Free Page message.<BR>
+  #  BIT6  - Information message.<BR>
+  #  BIT7  - Dispatcher message.<BR>
+  #  BIT8  - Variable message.<BR>
+  #  BIT10 - Boot Manager message.<BR>
+  #  BIT12 - BlockIo Driver message.<BR>
+  #  BIT14 - Network Driver message.<BR>
+  #  BIT16 - UNDI Driver message.<BR>
+  #  BIT17 - LoadFile message.<BR>
+  #  BIT19 - Event message.<BR>
+  #  BIT20 - Global Coherency Database changes message.<BR>
+  #  BIT21 - Memory range cachability changes message.<BR>
+  #  BIT22 - Detailed debug message.<BR>
+  #  BIT31 - Error message.<BR>
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0e
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000000
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0f
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x800B0507
+!endif
+# 0x800B05C7
+# Use 0x807B55FF to enable all debug messages
+
+[PcdsDynamicDefault.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x007C0000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x007CF000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x007D0000
+
+  #
+  # Display
+  #
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x780
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x438
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+  #
+  # PEI Phase modules
+  #
+  ArmPlatformPkg/PrePi/PeiUniCore.inf
+  MdeModulePkg/Core/Pei/PeiMain.inf
+  MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+
+  #
+  # DXE
+  #
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+  }
+
+  #
+  # Architectural Protocols
+  #
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+  #EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
+  <LibraryClasses>
+    RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
+  }
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  #PCIe
+  #Silicon/Rockchip/Library/PciExpressLib/PciExpressLib.inf
+  #Silicon/Rockchip/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+  #Silicon/Rockchip/Drivers/PciPlatform/PcieInitDxe.inf
+  ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  #MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+  #MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.inf
+  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+
+  MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+  
+
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+
+  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf
+  #Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
+  Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf
+  Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
+
+  Platform/OrangePi/Drivers/LogoDxe/LogoDxe.inf
+
+  #
+  # SCMI Driver
+  #
+  ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf
+
+  #
+  # ACPI Support
+  #
+  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+  Platform/OrangePi/OrangePi5/AcpiTables/AcpiTables.inf
+
+  #
+  # Device tree
+  #
+  EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf {
+  <LibraryClasses>
+    DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefault/DxeDtPlatformDtbLoaderLibDefault.inf
+  }
+
+  #
+  # GPIO
+  #
+  Platform/Rockchip/RK3588/RK3588GpioDxe/RK3588GpioDxe.inf
+
+  #
+  # Virtual Keyboard
+  #
+  EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
+
+  # I2C drivers
+  Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.inf
+  MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
+  Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.inf
+  Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.inf
+
+  #
+  # MMC/SD
+  #
+  #EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
+  #Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  Silicon/Rockchip/Drivers/MmcDxe/MmcDxe.inf
+  # sdcard is dwemmc, sdhci is for eMMC.
+  Silicon/Rockchip/RK3588/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  Silicon/Rockchip/Drivers/SdhciHostDxe/SdhciHostDxe.inf
+
+  #
+  # NOR FLASH
+  #
+  Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.inf
+  Silicon/Rockchip/Drivers/NorFlashDxe/RkFvbDxe.inf
+  Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+
+  #
+  # AHCI Support
+  #
+  Silicon/Rockchip/Drivers/SataControllerDxe/SataControllerDxe.inf
+  Silicon/Rockchip/Drivers/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+  #
+  # SPI TEST
+  #
+  # Silicon/Rockchip/Library/SpiLib/SpiTest.inf
+
+  #
+  # SMBIOS Support
+  #
+  Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  
+  #
+  # USB Ohci Controller
+  #
+  Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf
+
+  #
+  # USB Ehci Controller
+  #
+  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+
+  #
+  # USB Dwc3 Controller
+  #
+  Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
+  #
+  # USB Xhci Controller
+  #
+  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+
+  #
+  # USB Host Support
+  #
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+  #
+  # USB Mass Storage Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # USB Kb Support
+  #
+  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+  #
+  # USB Mouse Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+
+  #
+  # USB MouseAbsolutePointer Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointerDxe.inf
+
+  #
+  # USB Peripheral Support
+  #
+  EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
+
+  #
+  # Fastboot
+  #
+  EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
+
+  #
+  # Android Boot applications
+  #
+  EmbeddedPkg/Application/AndroidBoot/AndroidBootApp.inf
+
+  #
+  # UEFI Network Stack
+  #
+!include NetworkPkg/Network.dsc.inc
+  #
+  # AX88772 Ethernet Driver
+  #
+  Drivers/ASIX/Bus/Usb/UsbNetworking/Ax88772c/Ax88772c.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+  FatPkg/EnhancedFatDxe/Fat.inf
+
+  #
+  # Bds
+  #
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  MdeModulePkg/Application/UiApp/UiApp.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  ShellPkg/Application/Shell/Shell.inf {
+    <LibraryClasses>
+      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+      NULL|Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.inf
+      NULL|Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf
+      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+      OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
+      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+      gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+  }
+!ifdef $(INCLUDE_TFTP_COMMAND)
+  ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+!endif #$(INCLUDE_TFTP_COMMAND)
+
+  #
+  # Custom Applications and drivers
+  #
+  Silicon/Rockchip/Applications/MaskromReset/maskrom.inf
+
+  # Platform drivers
+  Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf
+

edk2-platforms/Platform/OrangePi/OrangePi5/OrangePi5.fdf

@@ -0,0 +1,374 @@
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2021-2022, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.NOR_FLASH_IMAGE]
+BaseAddress   = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
+Size          = 0x00800000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize     = 0x00001000
+NumBlocks     = 0x800
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+0x00200000|0x00100000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = BL33_AP_UEFI
+
+# NV_VARIABLE_STORE
+0x007C0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+
+# NV_FTW_WORKING header
+0x007D0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+# NV_FTW_WORKING data
+0x007E0000|0x00010000
+gRockchipTokenSpaceGuid.PcdNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+BlockSize          = 0x40
+NumBlocks          = 0         # This FV gets compressed so make it just big enough
+FvAlignment        = 8         # FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  APRIORI DXE {
+    INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+  }
+
+  INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+  #
+  # PI DXE Drivers producing Architectural Protocols (EFI Services)
+  #
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  #
+  # Multiple Console IO support
+  #
+  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+
+  INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+
+  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  #
+  # ACPI Support
+  #
+  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+  INF RuleOverride = ACPITABLE Platform/OrangePi/OrangePi5/AcpiTables/AcpiTables.inf
+
+  #
+  # Device tree
+  #
+  INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf
+  # FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 {
+  #   SECTION RAW = Platform/Rockchip/DeviceTree/rk3588.dtb
+  # }
+
+  #
+  # GPIO
+  #
+  INF Platform/Rockchip/RK3588/RK3588GpioDxe/RK3588GpioDxe.inf
+  #INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf
+
+  #
+  # I2C
+  #
+  INF Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.inf
+  INF MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
+  # INF Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.inf
+
+  #
+  # Virtual Keyboard
+  #
+  INF EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
+
+  #
+  # Display Support
+  #
+  
+  INF Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf
+  #INF Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
+  INF Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf
+  INF Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
+  INF Platform/OrangePi/Drivers/LogoDxe/LogoDxe.inf
+
+  INF Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf
+
+  #
+  # SMBIOS Support
+  #
+  INF Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+  INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+
+  #
+  # USB Ehci Controller
+  #
+  INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+
+  #
+  # USB Ohci Controller
+  #
+  INF Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf
+
+  #
+  # USB Dwc3 Controller
+  #
+  INF Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
+  #
+  # USB Xhci Controller
+  #
+  INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+
+  #
+  # USB Host Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+  #
+  # USB Mass Storage Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # USB Kb Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+  #
+  # USB Mouse Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+
+  #
+  # USB MouseAbsolutePointer Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointerDxe.inf
+
+  #
+  # USB Peripheral Support
+  #
+  INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
+
+  #
+  # Fastboot
+  #
+  INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
+
+
+  #PCIe
+  #INF Silicon/Rockchip/Drivers/PciPlatform/PcieInitDxe.inf
+
+  # Required by PCI
+  INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
+  # PCI Support
+  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  #INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+  #INF MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.inf
+
+  #INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+  INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+  INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+
+  #
+  # Android Boot applications
+  #
+  INF EmbeddedPkg/Application/AndroidBoot/AndroidBootApp.inf
+
+  #
+  # UEFI Network Stack
+  #
+!include NetworkPkg/Network.fdf.inc
+
+  #
+  # AX88772 Ethernet Driver for Apple Ethernet Adapter
+  #
+  INF Drivers/ASIX/Bus/Usb/UsbNetworking/Ax88772c/Ax88772c.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF FatPkg/EnhancedFatDxe/Fat.inf
+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  #
+  # Multimedia Card Interface
+  #
+  # INF Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  INF Silicon/Rockchip/Drivers/MmcDxe/MmcDxe.inf
+  # sdcard is dwemmc, sdhci is for eMMC.
+  INF Silicon/Rockchip/RK3588/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  
+  # Needs to be disabled if booting from eMMC
+  # INF Silicon/Rockchip/Drivers/SdhciHostDxe/SdhciHostDxe.inf
+
+  #
+  # AHCI Support
+  #
+  INF Silicon/Rockchip/Drivers/SataControllerDxe/SataControllerDxe.inf
+  INF Silicon/Rockchip/Drivers/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+  #
+  # SPI NOR FLASH
+  #
+  INF Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.inf
+
+  # Variable services
+  INF Silicon/Rockchip/Drivers/NorFlashDxe/RkFvbDxe.inf
+  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+
+  # Human interface
+  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  # Custom
+  INF Silicon/Rockchip/Applications/MaskromReset/maskrom.inf
+  
+  # SCMI Driver
+  INF ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf
+
+  #
+  # UEFI applications
+  #
+  INF ShellPkg/Application/Shell/Shell.inf
+!ifdef $(INCLUDE_TFTP_COMMAND)
+  INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+!endif #$(INCLUDE_TFTP_COMMAND)
+  #INF Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
+
+  #
+  # Bds
+  #
+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+[FV.BL33_AP_UEFI]
+FvAlignment        = 8
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+
+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FVMAIN
+    }
+  }
+
+!include Silicon/Rockchip/Rockchip.fdf.inc
+
+!ifdef $(ROCKCHIP_ACPIEN)
+[Rule.Common.DXE_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX	 DXE_DEPEX		Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32	 PE32			$(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI		 STRING="$(MODULE_NAME)" Optional
+    RAW 	 ACPI  Optional 	      |.acpi
+    RAW 	 ASL   Optional 	      |.aml
+  }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW ACPI		   |.acpi
+    RAW ASL		   |.aml
+  }
+!endif

edk2-platforms/Platform/Radxa/Drivers/LogoDxe/Logo.c

@@ -0,0 +1,144 @@
+/** @file
+  Logo DXE Driver, install Edkii Platform Logo protocol.
+
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+  Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Protocol/HiiDatabase.h>
+#include <Protocol/GraphicsOutput.h>
+#include <Protocol/HiiImageEx.h>
+#include <Protocol/PlatformLogo.h>
+#include <Protocol/HiiPackageList.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+
+typedef struct {
+  EFI_IMAGE_ID                          ImageId;
+  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
+  INTN                                  OffsetX;
+  INTN                                  OffsetY;
+} LOGO_ENTRY;
+
+STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
+STATIC EFI_HII_HANDLE            mHiiHandle;
+STATIC LOGO_ENTRY                mLogos[] = {
+  {
+    IMAGE_TOKEN (IMG_LOGO),
+    EdkiiPlatformLogoDisplayAttributeCenter,
+    0,
+    0
+  }
+};
+
+/**
+  Load a platform logo image and return its data and attributes.
+
+  @param This              The pointer to this protocol instance.
+  @param Instance          The visible image instance is found.
+  @param Image             Points to the image.
+  @param Attribute         The display attributes of the image returned.
+  @param OffsetX           The X offset of the image regarding the Attribute.
+  @param OffsetY           The Y offset of the image regarding the Attribute.
+
+  @retval EFI_SUCCESS      The image was fetched successfully.
+  @retval EFI_NOT_FOUND    The specified image could not be found.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GetImage (
+  IN     EDKII_PLATFORM_LOGO_PROTOCOL          *This,
+  IN OUT UINT32                                *Instance,
+     OUT EFI_IMAGE_INPUT                       *Image,
+     OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
+     OUT INTN                                  *OffsetX,
+     OUT INTN                                  *OffsetY
+  )
+{
+  UINT32 Current;
+
+  if (Instance == NULL || Image == NULL ||
+      Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Current = *Instance;
+  if (Current >= ARRAY_SIZE (mLogos)) {
+    return EFI_NOT_FOUND;
+  }
+
+  (*Instance)++;
+  *Attribute = mLogos[Current].Attribute;
+  *OffsetX   = mLogos[Current].OffsetX;
+  *OffsetY   = mLogos[Current].OffsetY;
+
+  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
+                        mLogos[Current].ImageId, Image);
+}
+
+STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+  GetImage
+};
+
+/**
+  Entrypoint of this module.
+
+  This function is the entrypoint of this module. It installs the Edkii
+  Platform Logo protocol.
+
+  @param  ImageHandle       The firmware allocated handle for the EFI image.
+  @param  SystemTable       A pointer to the EFI System Table.
+
+  @retval EFI_SUCCESS       The entry point is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeLogo (
+  IN EFI_HANDLE               ImageHandle,
+  IN EFI_SYSTEM_TABLE         *SystemTable
+  )
+{
+  EFI_STATUS                  Status;
+  EFI_HII_PACKAGE_LIST_HEADER *PackageList;
+  EFI_HII_DATABASE_PROTOCOL   *HiiDatabase;
+  EFI_HANDLE                  Handle;
+
+  Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
+                  (VOID **) &HiiDatabase);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
+                  (VOID **) &mHiiImageEx);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Retrieve HII package list from ImageHandle
+  //
+  Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
+                  (VOID **) &PackageList, ImageHandle, NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR,
+      "HII Image Package with logo not found in PE/COFF resource section\n"));
+    return Status;
+  }
+
+  //
+  // Publish HII package list to HII Database.
+  //
+  Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
+                          &mHiiHandle);
+  if (!EFI_ERROR (Status)) {
+    Handle = NULL;
+    Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
+                    &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
+  }
+  return Status;
+}

edk2-platforms/Platform/Radxa/Drivers/LogoDxe/Logo.idf

@@ -0,0 +1,10 @@
+// @file
+// Platform Logo image definition file.
+//
+// Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+// Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+
+#image IMG_LOGO Logo.bmp

edk2-platforms/Platform/Radxa/Drivers/LogoDxe/LogoDxe.inf

@@ -0,0 +1,48 @@
+## @file
+#  The default logo bitmap picture shown on setup screen.
+#
+#  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+#  Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = LogoDxe
+  FILE_GUID                      = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = InitializeLogo
+#
+#  This flag specifies whether HII resource section is generated into PE image.
+#
+  UEFI_HII_RESOURCE_SECTION      = TRUE
+
+[Sources]
+  Logo.bmp
+  Logo.c
+  Logo.idf
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  DebugLib
+
+[Protocols]
+  gEfiHiiDatabaseProtocolGuid        ## CONSUMES
+  gEfiHiiImageExProtocolGuid         ## CONSUMES
+  gEfiHiiPackageListProtocolGuid     ## PRODUCES CONSUMES
+  gEdkiiPlatformLogoProtocolGuid     ## PRODUCES
+
+[Depex]
+  gEfiHiiDatabaseProtocolGuid AND
+  gEfiHiiImageExProtocolGuid

edk2-platforms/Platform/Radxa/ROCK5B/AcpiTables/AcpiTables.inf

@@ -15,6 +15,7 @@
   FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
   MODULE_TYPE                    = USER_DEFINED
   VERSION_STRING                 = 1.0
+  RK_COMMON_ACPI_DIR             = Silicon/Rockchip/RK3588/AcpiTables
 
 #
 # The following information is for reference only and not required by the build tools.
@@ -23,15 +24,14 @@
 #
 
 [Sources]
-  AcpiTables.h
-  Madt.aslc
-  Fadt.aslc
-  Gtdt.aslc
   Dsdt.asl
-  Spcr.aslc
-  Mcfg.aslc
-  RK3588PcieIort.aslc
-  Dbg2.aslc
+  $(RK_COMMON_ACPI_DIR)/Madt.aslc
+  $(RK_COMMON_ACPI_DIR)/Fadt.aslc
+  $(RK_COMMON_ACPI_DIR)/Gtdt.aslc
+  $(RK_COMMON_ACPI_DIR)/Spcr.aslc
+  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
+  $(RK_COMMON_ACPI_DIR)/RK3588PcieIort.aslc
+  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
 
 [Packages]
   ArmPkg/ArmPkg.dec

edk2-platforms/Platform/Radxa/ROCK5B/AcpiTables/Dsdt.asl

@@ -17,88 +17,12 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
 {
   Scope (\_SB_)
   {
-    Device (CPU0)
-    {
-      Name (_HID, "ACPI0007")
-      Name (_UID, 0x0)
-      Method (_STA)
-      {
-        Return (0xf)
-      }
-    }
-    Device (CPU1)
-    {
-      Name (_HID, "ACPI0007")
-      Name (_UID, 0x1)
-      Method (_STA)
-      {
-        Return (0xf)
-      }
-    }
-
-    Device (CPU2)
-    {
-      Name (_HID, "ACPI0007")
-      Name (_UID, 0x2)
-      Method (_STA)
-      {
-        Return (0xf)
-      }
-    }
-
-    Device (CPU3)
-    {
-      Name (_HID, "ACPI0007")
-      Name (_UID, 0x3)
-      Method (_STA)
-      {
-        Return (0xf)
-      }
-    }
-
-    Device (CPU4)
-    {
-      Name (_HID, "ACPI0007")
-      Name (_UID, 0x4)
-      Method (_STA)
-      {
-        Return (0xf)
-      }
-    }
-
-    Device (CPU5)
-    {
-      Name (_HID, "ACPI0007")
-      Name (_UID, 0x5)
-      Method (_STA)
-      {
-        Return (0xf)
-      }
-    }
-
-    Device (CPU6)
-    {
-      Name (_HID, "ACPI0007")
-      Name (_UID, 0x6)
-      Method (_STA)
-      {
-        Return (0xf)
-      }
-    }
-
-    Device (CPU7)
-    {
-      Name (_HID, "ACPI0007")
-      Name (_UID, 0x7)
-      Method (_STA)
-      {
-        Return (0xf)
-      }
-    }
+    include ("Cpu.asl")
 
     include ("Pcie.asl")
     // include ("Sata.asl")
     // include ("Emmc.asl")
+    include ("Sdhc.asl")
     // include ("Gmac.asl")
     // include ("Gpio.asl")
     // include ("I2c.asl")
@@ -108,6 +32,8 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
     // won't work on Windows, will trigger bugcheck by usbehci
     // include ("Usb2.asl")
 
-    include ("Usb3.asl")
+    include ("Usb3Host0.asl")
+    include ("Usb3Host1.asl")
+    include ("Usb3Host2.asl")
   }
 }

edk2-platforms/Platform/Radxa/ROCK5B/AcpiTables/Usb3.asl

@@ -1,54 +0,0 @@
-/** @file
-*  DWC3 XHCI Controllers.
-*
-*  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
-*
-*  SPDX-License-Identifier: BSD-2-Clause-Patent
-**/
-
-#include "AcpiTables.h"
-
-Device (XHC0) {
-    Name (_HID, "PNP0D10")
-    Name (_UID, Zero)
-    Name (_CCA, Zero)
-
-    Method (_CRS, 0x0, Serialized) {
-        Name (RBUF, ResourceTemplate() {
-            Memory32Fixed (ReadWrite, 0xfc000000, 0x400000)
-            Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 252 }
-        })
-        Return (RBUF)
-    }   
-}
-
-Device (XHC1) {
-    Name (_HID, "PNP0D10")
-    Name (_UID, One)
-    Name (_CCA, Zero)
-
-    Method (_CRS, 0x0, Serialized) {
-        Name (RBUF, ResourceTemplate() {
-            Memory32Fixed (ReadWrite, 0xfc400000, 0x400000)
-            Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 253 }
-        })
-        Return (RBUF)
-    }   
-}
-
-// This only supports USB 3.0 devices.
-// USB2 DP / DM are connected to one of the EHCI controllers instead (EHC1 on ROCK 5B).
-
-Device (XHC2) {
-    Name (_HID, "PNP0D10")
-    Name (_UID, 2)
-    Name (_CCA, Zero)
-
-    Method (_CRS, 0x0, Serialized) {
-        Name (RBUF, ResourceTemplate() {
-            Memory32Fixed (ReadWrite, 0xfcd00000, 0x400000)
-            Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 254 }
-        })
-        Return (RBUF)
-    }   
-}

edk2-platforms/Platform/Radxa/ROCK5B/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.c

@@ -1,296 +0,0 @@
-/** @file
-  UART Serial Port library functions
-
-  Copyright (c) 2006 - 2009, Intel Corporation
-  Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved.
-  Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved.
-  SPDX-License-Identifier: BSD-2-Clause-Patent
-
-  Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/
-**/
-#include <Uefi.h>
-#include <Library/PcdLib.h>
-#include <Library/SerialPortLib.h>
-#include <Library/IoLib.h>
-#include <Protocol/SerialIo.h>
-
-#include "Dw8250SerialPortLib.h"
-
-
-/**
-  Initialize the serial device hardware.
-
-  If no initialization is required, then return RETURN_SUCCESS.
-  If the serial device was successfuly initialized, then return RETURN_SUCCESS.
-  If the serial device could not be initialized, then return RETURN_DEVICE_ERROR.
-
-  @retval RETURN_SUCCESS        The serial device was initialized.
-  @retval RETURN_DEVICE_ERROR   The serail device could not be initialized.
-
-**/
-RETURN_STATUS
-EFIAPI
-SerialPortInitialize (
-  VOID
-  )
-{
-    UINT32 ulUartClkFreq;
-
-    MmioWrite8 (UART_LCR_REG, UART_LCR_DLS8);
-    MmioWrite8 (UART_FCR_REG, UART_FCR_EN | UART_FCR_RXCLR | UART_FCR_TXCLR);
-    MmioWrite8 (UART_LCR_REG, UART_LCR_DLAB | UART_LCR_DLS8);
-
-    ulUartClkFreq = PcdGet32(PcdUartClkInHz);
-
-    MmioWrite8 (UART_DLL_REG, (ulUartClkFreq / (16 * (UINT32)BAUDRATE) ) & 0xff);
-    MmioWrite8 (UART_DLH_REG, ((ulUartClkFreq/ (16 * (UINT32)BAUDRATE) ) >> 8 ) & 0xff);
-    MmioWrite8 (UART_LCR_REG, UART_LCR_DLS8);
-    MmioWrite8 (UART_IEL_REG, 0x00);
-
-    return RETURN_SUCCESS;
-}
-
-
-/**
-  Write data from buffer to serial device.
-
-  Writes NumberOfBytes data bytes from Buffer to the serial device.
-  The number of bytes actually written to the serial device is returned.
-  If the return value is less than NumberOfBytes, then the write operation failed.
-
-  If Buffer is NULL, then ASSERT().
-
-  If NumberOfBytes is zero, then return 0.
-
-  @param  Buffer           Pointer to the data buffer to be written.
-  @param  NumberOfBytes    Number of bytes to written to the serial device.
-
-  @retval 0                NumberOfBytes is 0.
-  @retval >0               The number of bytes written to the serial device.
-                           If this value is less than NumberOfBytes, then the read operation failed.
-
-**/
-UINTN
-EFIAPI
-SerialPortWrite (
-  IN UINT8     *Buffer,
-  IN UINTN     NumberOfBytes
-)
-{
-  UINTN  Result;
-
-  if (NULL == Buffer) {
-    return 0;
-  }
-
-  Result = NumberOfBytes;
-
-  while (NumberOfBytes--) {
-
-    SerialPortWriteChar(*Buffer);
-    Buffer++;
-  }
-
-  return Result;
-}
-
-
-/**
-  Reads data from a serial device into a buffer.
-
-  @param  Buffer           Pointer to the data buffer to store the data read from the serial device.
-  @param  NumberOfBytes    Number of bytes to read from the serial device.
-
-  @retval 0                NumberOfBytes is 0.
-  @retval >0               The number of bytes read from the serial device.
-                           If this value is less than NumberOfBytes, then the read operation failed.
-
-**/
-UINTN
-EFIAPI
-SerialPortRead (
-  OUT UINT8     *Buffer,
-  IN  UINTN     NumberOfBytes
-)
-{
-  UINTN  Result;
-
-  if (NULL == Buffer) {
-    return 0;
-  }
-
-  Result = 0;
-
-  while (NumberOfBytes--) {
-    //
-    // Wait for the serail port to be ready.
-    //
-    *Buffer=SerialPortReadChar();
-    Buffer++ ;
-    Result++;
-  }
-
-  return Result;
-}
-
-/**
-  Polls a serial device to see if there is any data waiting to be read.
-
-  Polls aserial device to see if there is any data waiting to be read.
-  If there is data waiting to be read from the serial device, then TRUE is returned.
-  If there is no data waiting to be read from the serial device, then FALSE is returned.
-
-  @retval TRUE             Data is waiting to be read from the serial device.
-  @retval FALSE            There is no data waiting to be read from the serial device.
-
-**/
-BOOLEAN
-EFIAPI
-SerialPortPoll (
-  VOID
-  )
-{
-
-  return (BOOLEAN) ((MmioRead8 (UART_LSR_REG) & UART_LSR_DR) == UART_LSR_DR);
-
-}
-
-
-VOID SerialPortWriteChar(UINT8 scShowChar)
-{
-    UINT32 ulLoop = 0;
-
-    while(ulLoop < (UINT32)UART_SEND_DELAY)
-    {
-
-        if ((MmioRead8 (UART_USR_REG) & 0x02) == 0x02)
-        {
-            break;
-        }
-
-        ulLoop++;
-    }
-    MmioWrite8 (UART_THR_REG, (UINT8)scShowChar);
-
-    ulLoop = 0;
-    while(ulLoop < (UINT32)UART_SEND_DELAY)
-    {
-        if ((MmioRead8 (UART_USR_REG) & 0x04) == 0x04)
-        {
-            break;
-        }
-        ulLoop++;
-    }
-
-    return;
-}
-
-
-UINT8 SerialPortReadChar(VOID)
-{
-    UINT8 recvchar = 0;
-
-    while(1)
-    {
-        if ((MmioRead8 (UART_LSR_REG) & UART_LSR_DR) == UART_LSR_DR)
-        {
-            break;
-        }
-    }
-
-    recvchar = MmioRead8 (UART_RBR_REG);
-
-    return recvchar;
-}
-
-/**
-  Sets the baud rate, receive FIFO depth, transmit/receice time out, parity,
-  data bits, and stop bits on a serial device.
-
-  @param BaudRate           The requested baud rate. A BaudRate value of 0 will use the
-                            device's default interface speed.
-                            On output, the value actually set.
-  @param ReveiveFifoDepth   The requested depth of the FIFO on the receive side of the
-                            serial interface. A ReceiveFifoDepth value of 0 will use
-                            the device's default FIFO depth.
-                            On output, the value actually set.
-  @param Timeout            The requested time out for a single character in microseconds.
-                            This timeout applies to both the transmit and receive side of the
-                            interface. A Timeout value of 0 will use the device's default time
-                            out value.
-                            On output, the value actually set.
-  @param Parity             The type of parity to use on this serial device. A Parity value of
-                            DefaultParity will use the device's default parity value.
-                            On output, the value actually set.
-  @param DataBits           The number of data bits to use on the serial device. A DataBits
-                            vaule of 0 will use the device's default data bit setting.
-                            On output, the value actually set.
-  @param StopBits           The number of stop bits to use on this serial device. A StopBits
-                            value of DefaultStopBits will use the device's default number of
-                            stop bits.
-                            On output, the value actually set.
-
-  @retval RETURN_SUCCESS            The new attributes were set on the serial device.
-  @retval RETURN_UNSUPPORTED        The serial device does not support this operation.
-  @retval RETURN_INVALID_PARAMETER  One or more of the attributes has an unsupported value.
-  @retval RETURN_DEVICE_ERROR       The serial device is not functioning correctly.
-
-**/
-RETURN_STATUS
-EFIAPI
-SerialPortSetAttributes (
-  IN OUT UINT64             *BaudRate,
-  IN OUT UINT32             *ReceiveFifoDepth,
-  IN OUT UINT32             *Timeout,
-  IN OUT EFI_PARITY_TYPE    *Parity,
-  IN OUT UINT8              *DataBits,
-  IN OUT EFI_STOP_BITS_TYPE *StopBits
-  )
-{
-  return RETURN_UNSUPPORTED;
-}
-
-/**
-  Set the serial device control bits.
-
-  @param  Control                 Control bits which are to be set on the serial device.
-
-  @retval EFI_SUCCESS             The new control bits were set on the serial device.
-  @retval EFI_UNSUPPORTED         The serial device does not support this operation.
-  @retval EFI_DEVICE_ERROR        The serial device is not functioning correctly.
-
-**/
-RETURN_STATUS
-EFIAPI
-SerialPortSetControl (
-  IN UINT32                  Control
-  )
-{
-  return EFI_UNSUPPORTED;
-}
-
-/**
-  Get the serial device control bits.
-
-  @param  Control                 Control signals read from the serial device.
-
-  @retval EFI_SUCCESS             The control bits were read from the serial device.
-  @retval EFI_DEVICE_ERROR        The serial device is not functioning correctly.
-
-**/
-RETURN_STATUS
-EFIAPI
-SerialPortGetControl (
-  OUT UINT32                  *Control
-  )
-{
-
-    if (SerialPortPoll ()) {
-        // If a character is pending don't set EFI_SERIAL_INPUT_BUFFER_EMPTY
-        *Control = EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
-    } else {
-        *Control = EFI_SERIAL_INPUT_BUFFER_EMPTY | EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
-    }
-    return EFI_SUCCESS;
-}
-

edk2-platforms/Platform/Radxa/ROCK5B/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.h

@@ -1,110 +0,0 @@
-/** @file
-*
-*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
-*  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
-*  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
-*
-*  SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-*  Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/
-**/
-
-#ifndef __DW8250_SERIALPORTLIB_H__
-#define __DW8250_SERIALPORTLIB_H__
-
-
-#define SERIAL_0_BASE_ADR     (PcdGet64(PcdSerialRegisterBase))
-
-
-#define UART_SEND_DELAY      (PcdGet32(PcdSerialPortSendDelay))
-#define BAUDRATE             (PcdGet64(PcdUartDefaultBaudRate))
-
-
-#define UART_THR_REG         (SERIAL_0_BASE_ADR + UART_THR)
-#define UART_RBR_REG         (SERIAL_0_BASE_ADR + UART_RBR)
-#define UART_DLL_REG         (SERIAL_0_BASE_ADR + UART_DLL)
-#define UART_DLH_REG         (SERIAL_0_BASE_ADR + UART_DLH)
-#define UART_IEL_REG         (SERIAL_0_BASE_ADR + UART_IEL)
-#define UART_IIR_REG         (SERIAL_0_BASE_ADR + UART_IIR)
-#define UART_FCR_REG         (SERIAL_0_BASE_ADR + UART_FCR)
-#define UART_LCR_REG         (SERIAL_0_BASE_ADR + UART_LCR)
-#define UART_LSR_REG         (SERIAL_0_BASE_ADR + UART_LSR)
-#define UART_USR_REG         (SERIAL_0_BASE_ADR + UART_USR)
-
-
-#define UART_RBR     0x00
-#define UART_THR     0x00
-#define UART_DLL     0x00
-#define UART_DLH     0x04
-#define UART_IEL     0x04
-#define UART_IIR     0x08
-#define UART_FCR     0x08
-#define UART_LCR     0x0C
-#define UART_MCR     0x10
-#define UART_LSR     0x14
-#define UART_USR     0x7C
-
-/* register definitions */
-
-#define UART_FCR_EN          0x01
-#define UART_FCR_RXCLR       0x02
-#define UART_FCR_TXCLR       0x04
-#define UART_FCR_CLEARFIFO   0x00
-#define UART_FCR_RXL1        0x00
-#define UART_FCR_RXL4        0x40
-#define UART_FCR_RXL8        0x80
-#define UART_FCR_RXL14       0xc0
-#define UART_FCR_TXL0        0x00
-#define UART_FCR_TXL4        0x20
-#define UART_FCR_TXL8        0x30
-#define UART_FCR_TXL14       0x10
-
-/*LCR Name: Line Control Register fields*/
-#define UART_LCR_DLAB   0x80
-#define UART_LCR_EPS    0x10
-#define UART_LCR_PEN    0x08
-#define UART_LCR_STOP   0x04
-#define UART_LCR_DLS8   0x03
-#define UART_LCR_DLS7   0x02
-#define UART_LCR_DLS6   0x01
-#define UART_LCR_DLS5   0x00
-
-
-#define UART_DLH_AND_DLL_WIDTH 0xFF
-
-
-#define UART_IER_PTIME  0x80
-#define UART_IER_ELSI   0x04
-#define UART_IER_ETBEI  0x02
-#define UART_IER_ERBFI  0x01
-
-
-#define UART_IIR_FIFOSE         0xC0
-
-
-#define UART_IIR_InterruptID   0x01
-#define UART_IIR_INTIDTE       0x02
-#define UART_IIR_INTIDRA       0x04
-#define UART_IIR_INTIDRLS      0x06
-#define UART_IIR_INTMASK       0x0f
-#define UART_IIR_RDA           0x04
-#define UART_IIR_TE            0x02
-
-#define UART_LSR_TEMT       0x40
-#define UART_LSR_THRE       0x20
-#define UART_LSR_BI         0x10
-#define UART_LSR_FE         0x08
-#define UART_LSR_PE         0x04
-#define UART_LSR_R          0x02
-#define UART_LSR_DR         0x01
-
-
-#define UART_USR_BUSY  0x01
-
-#define FIFO_MAXSIZE    32
-
-extern UINT8 SerialPortReadChar(VOID);
-extern VOID SerialPortWriteChar(UINT8 scShowChar);
-
-#endif
-

edk2-platforms/Platform/Radxa/ROCK5B/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf

@@ -1,36 +0,0 @@
-#/** @file
-#
-#  Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
-#  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
-#  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
-#  SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-#  Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = Dw8250SerialPortLib
-  FILE_GUID                      = 78337705-D2A8-4EA7-9C18-27FC4A8A2C6E
-  MODULE_TYPE                    = BASE
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = SerialPortLib
-
-[Sources.common]
-  Dw8250SerialPortLib.c
-
-[Packages]
-  MdePkg/MdePkg.dec
-  MdeModulePkg/MdeModulePkg.dec
-  ArmPlatformPkg/ArmPlatformPkg.dec
-  Platform/Radxa/ROCK5B/ROCK5B.dec
-
-[LibraryClasses]
-  BaseLib
-  IoLib
-
-[Pcd]
-  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
-  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
-  gROCK5BTokenSpaceGuid.PcdSerialPortSendDelay
-  gROCK5BTokenSpaceGuid.PcdUartClkInHz

edk2-platforms/Platform/Radxa/ROCK5B/Library/PlatformBootManagerLib/PlatformBm.h

@@ -1,53 +0,0 @@
-/** @file
-  Head file for BDS Platform specific code
-
-  Copyright (C) 2015-2016, Red Hat, Inc.
-  Copyright (c) 2004 - 2008, Intel Corporation. All rights reserved.<BR>
-  Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
-
-  SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef PLATFORM_BM_H_
-#define PLATFORM_BM_H_
-
-#include <Library/BaseLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/DebugLib.h>
-#include <Library/DevicePathLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiLib.h>
-#include <Library/UefiRuntimeServicesTableLib.h>
-
-/**
-  Use SystemTable Conout to stop video based Simple Text Out consoles from
-  going to the video device. Put up LogoFile on every video device that is a
-  console.
-
-  @param[in]  LogoFile   File name of logo to display on the center of the
-                         screen.
-
-  @retval EFI_SUCCESS     ConsoleControl has been flipped to graphics and logo
-                          displayed.
-  @retval EFI_UNSUPPORTED Logo not found
-**/
-EFI_STATUS
-EnableQuietBoot (
-  IN  EFI_GUID  *LogoFile
-  );
-
-/**
-  Use SystemTable Conout to turn on video based Simple Text Out consoles. The
-  Simple Text Out screens will now be synced up with all non video output
-  devices
-
-  @retval EFI_SUCCESS     UGA devices are back in text mode and synced up.
-**/
-EFI_STATUS
-DisableQuietBoot (
-  VOID
-  );
-
-#endif // PLATFORM_BM_H_

edk2-platforms/Platform/Radxa/ROCK5B/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf

@@ -1,97 +0,0 @@
-## @file
-#  Implementation for PlatformBootManagerLib library class interfaces.
-#
-#  Copyright (C) 2015-2016, Red Hat, Inc.
-#  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
-#  Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
-#  Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
-#
-#  SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-##
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = PlatformBootManagerLib
-  FILE_GUID                      = 92FD2DE3-B9CB-4B35-8141-42AD34D73C9F
-  MODULE_TYPE                    = DXE_DRIVER
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = PlatformBootManagerLib|DXE_DRIVER
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-#  VALID_ARCHITECTURES           = ARM AARCH64
-#
-
-[Sources]
-  PlatformBm.c
-  PlatformBm.h
-
-[Packages]
-  EmbeddedPkg/EmbeddedPkg.dec
-  MdeModulePkg/MdeModulePkg.dec
-  MdePkg/MdePkg.dec
-  ShellPkg/ShellPkg.dec
-  Platform/Radxa/ROCK5B/ROCK5B.dec
-  SimpleInit.dec
-
-[LibraryClasses]
-  BaseLib
-  BaseMemoryLib
-  BootLogoLib
-  CapsuleLib
-  DebugLib
-  DevicePathLib
-  DxeServicesLib
-  HobLib
-  MemoryAllocationLib
-  PcdLib
-  PrintLib
-  UefiBootManagerLib
-  UefiBootServicesTableLib
-  UefiLib
-  UefiRuntimeServicesTableLib
-
-[FeaturePcd]
-  gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport
-
-[FixedPcd]
-  gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
-  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
-  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
-  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
-  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
-  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType
-
-[Pcd]
-  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
-  gEfiMdeModulePkgTokenSpaceGuid.PcdBootDiscoveryPolicy
-
-[Guids]
-  gBootDiscoveryPolicyMgrFormsetGuid
-  gEdkiiNonDiscoverableEhciDeviceGuid
-  gEdkiiNonDiscoverableUhciDeviceGuid
-  gEdkiiNonDiscoverableXhciDeviceGuid
-  gEfiBootManagerPolicyNetworkGuid
-  gEfiBootManagerPolicyConnectAllGuid
-  gEfiFileInfoGuid
-  gEfiFileSystemInfoGuid
-  gEfiFileSystemVolumeLabelInfoIdGuid
-  gEfiEndOfDxeEventGroupGuid
-  gEfiTtyTermGuid
-  gUefiShellFileGuid
-  gSimpleInitFileGuid
-  gMaskromFileGuid
-
-[Protocols]
-  gEdkiiNonDiscoverableDeviceProtocolGuid
-  gEfiBootManagerPolicyProtocolGuid
-  gEfiDevicePathProtocolGuid
-  gEfiGraphicsOutputProtocolGuid
-  gEfiLoadedImageProtocolGuid
-  gEfiPciRootBridgeIoProtocolGuid
-  gEfiSimpleFileSystemProtocolGuid
-  gEsrtManagementProtocolGuid
-  gPlatformBootManagerProtocolGuid

edk2-platforms/Platform/Radxa/ROCK5B/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -9,8 +9,41 @@
 #include <Library/DebugLib.h>
 #include <Library/IoLib.h>
 #include <Library/GpioLib.h>
+#include <Library/RK806.h>
 #include <Soc.h>
 
+static struct regulator_init_data rk806_init_data[] = {
+  /* Master PMIC */
+
+  /* TODO: Figure out the correct voltages
+  
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK2, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1100000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 900000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 850000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  */
+
+  /* No dual PMICs on this platform */
+};
+
 void DebugPrintHex(void *buf, UINT32 width, UINT32 len)
 {
   UINT32 i,j;
@@ -44,14 +77,17 @@ void
 EFIAPI
 DwEmmcDxeIoMux(void)
 {
-  /* sdmmc0 iomux */
+  /* sdmmc0 iomux (microSD socket) */
+  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
 }
 
 void
 EFIAPI
 SdhciEmmcDxeIoMux(void)
 {
-  /* sdmmc0 iomux */
+  /* sdhci0 iomux (eMMC socket) */
   BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
   BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
   BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
@@ -73,6 +109,20 @@ Rk806SpiIomux(void)
   MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
 }
 
+VOID
+EFIAPI
+Rk806Configure(
+  VOID
+)
+{
+  UINTN RegCfgIndex;
+
+  RK806Init();
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
+    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+}
+
 void
 EFIAPI
 NorFspiIomux(void)

edk2-platforms/Platform/Radxa/ROCK5B/Library/RockchipPlatformLib/RockchipPlatformLib.inf

@@ -11,6 +11,7 @@
   MODULE_TYPE                    = BASE
   VERSION_STRING                 = 1.0
   LIBRARY_CLASS                  = RockchipPlatformLib
+  RKPLATLIB_COMMON_DIR           = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon
 
 [Packages]
   EmbeddedPkg/EmbeddedPkg.dec
@@ -19,7 +20,6 @@
   Platform/Rockchip/RK3588/RK3588.dec
   Silicon/Rockchip/RK3588/RK3588.dec
   Silicon/Rockchip/RockchipPkg.dec
-  Platform/Radxa/ROCK5B/ROCK5B.dec
 
 [LibraryClasses]
   ArmLib
@@ -32,8 +32,8 @@
 
 [Sources.common]
   RockchipPlatformLib.c
-  RK3588CruLib.c
-  RockchipSdhci.c
+  $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c
+  $(RKPLATLIB_COMMON_DIR)/RockchipSdhci.c
 
 [Sources.AARCH64]
 

edk2-platforms/Platform/Radxa/ROCK5B/ROCK5B.dec

@@ -1,35 +0,0 @@
-#
-#  Copyright (c) 2018, Linaro Limited. All rights reserved.
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-
-[Defines]
-  DEC_SPECIFICATION              = 0x0001001a
-  PACKAGE_NAME                   = ROCK5B
-  PACKAGE_GUID                   = 7eb1de03-3910-4d1d-84ce-c17b53636b9a
-  PACKAGE_VERSION                = 1.0
-
-[Includes.common]
-  Include                        # Root include for the package
-
-[Guids.common]
-  gROCK5BTokenSpaceGuid          = { 0x99a14446, 0xaad7, 0xe460, { 0xb4, 0xe5, 0x1f, 0x79, 0xaa, 0xa4, 0x93, 0xfd } }
-  gMaskromFileGuid               = { 0x6987437F, 0xED34, 0x44db, { 0xae, 0x97, 0x1f, 0xa5, 0xe4, 0xed, 0x21, 0x16 } }
-
-[Protocols]
-
-[Guids]
-
-[PcdsFixedAtBuild.common]
-  gROCK5BTokenSpaceGuid.PcdSerialPortSendDelay|500000|UINT32|0x01000010
-  gROCK5BTokenSpaceGuid.PcdUartClkInHz|24000000|UINT32|0x0100001F
-  gROCK5BTokenSpaceGuid.PcdRkMtlMailBoxBase|0x0010f000|UINT64|0x00001000
-  gROCK5BTokenSpaceGuid.PcdRkMtlMailBoxSize|0x100|UINT32|0x00001001
-  gROCK5BTokenSpaceGuid.PcdRkMtlMailBoxSmcId|0x82000010|UINT32|0x00010002

edk2-platforms/Platform/Radxa/ROCK5B/ROCK5B.dsc

@@ -39,10 +39,14 @@
   DEFINE NETWORK_VLAN_ENABLE            = FALSE
 !include Silicon/Rockchip/Rockchip.dsc.inc
 !include MdePkg/MdeLibs.dsc.inc
-!include SimpleInit.inc
+
+!if $(ENABLE_SIMPLE_INIT)
+  !include SimpleInit.inc
+!endif
 
 [LibraryClasses.common]
   ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmPlatformLib|Silicon/Rockchip/RK3588/Library/PlatformLib/PlatformLib.inf
   AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf
   CruLib|Silicon/Rockchip/Library/CruLib/CruLib.inf
 
@@ -85,25 +89,26 @@
   UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
   LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf
 
+  # OTP Library
+  OtpLib|Silicon/Rockchip/RK3588/Library/OtpLib/OtpLib.inf
 
   #
   # Custom libraries
   #
-  ArmPlatformLib|Platform/Radxa/ROCK5B/Library/PlatformLib/PlatformLib.inf
   RockchipPlatformLib|Platform/Radxa/ROCK5B/Library/RockchipPlatformLib/RockchipPlatformLib.inf
-  ResetSystemLib|Platform/Radxa/ROCK5B/Library/ResetSystemLib/ResetSystemLib.inf
-  PlatformBootManagerLib|Platform/Radxa/ROCK5B/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
-  SerialPortLib|Platform/Radxa/ROCK5B/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf
-  GpioLib|Platform/Radxa/ROCK5B/Library/GpioLib/GpioLib.inf
+  ResetSystemLib|Silicon/Rockchip/Library/ResetSystemLib/ResetSystemLib.inf
+  PlatformBootManagerLib|Silicon/Rockchip/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+  SerialPortLib|Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf
+  GpioLib|Silicon/Rockchip/RK3588/Library/GpioLib/GpioLib.inf
   # SCMI Mailbox Transport Layer
-  ArmMtlLib|Platform/Radxa/ROCK5B/Library/RkMtlLib/RkMtlLib.inf
+  ArmMtlLib|Silicon/Rockchip/Library/RkMtlLib/RkMtlLib.inf
 
 [LibraryClasses.common.SEC]
   PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
   ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
   HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
   MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
-  MemoryInitPeiLib|Platform/Radxa/ROCK5B/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
+  MemoryInitPeiLib|Silicon/Rockchip/RK3588/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
   PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
   PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
 
@@ -132,12 +137,18 @@
   # System Memory (1GB)
   gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
   gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000
-  gRK3588TokenSpaceGuid.PcdTotalMemorySize|0x200000000
   
   # RK3588 CPU profile
   gArmPlatformTokenSpaceGuid.PcdCoreCount|8
   gArmPlatformTokenSpaceGuid.PcdClusterCount|1
 
+  # SMBIOS platform config
+  gRockchipTokenSpaceGuid.PcdPlatformName|"ROCK 5 Model B"
+  gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Radxa"
+  gRockchipTokenSpaceGuid.PcdFamilyName|"ROCK 5"
+  gRockchipTokenSpaceGuid.PcdProductUrl|"https://wiki.radxa.com/Rock5/hardware/5b"
+  gRockchipTokenSpaceGuid.PcdMemoryVendorName|"TBD"
+
   # I2C
   gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x51 }
   gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x2 }
@@ -152,6 +163,8 @@
   DEFINE SERIAL_BASE = 0xFEB50000 # UART2
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|$(SERIAL_BASE)
   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|1500000
+  gHisiTokenSpaceGuid.PcdSerialPortSendDelay|500000
+  gHisiTokenSpaceGuid.PcdUartClkInHz|24000000
 
   ## SPI - SPI2 for test
   gRockchipTokenSpaceGuid.SpiTestBaseAddr|0xFEB20000
@@ -261,7 +274,7 @@
   #
   # ComboPhy
   #
-  gRockchipTokenSpaceGuid.PcdComboPhyMode|{ $(CP_SATA), $(CP_PCIE), $(CP_USB3) }
+  gRockchipTokenSpaceGuid.PcdComboPhyMode|{ $(CP_PCIE), $(CP_PCIE), $(CP_USB3) }
 
   #  BIT0  - Initialization message.<BR>
   #  BIT1  - Warning message.<BR>
@@ -379,7 +392,7 @@
   Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf
   Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
 
-  Platform/Rockchip/RK3588/LogoDxe/LogoDxe.inf
+  Platform/Radxa/Drivers/LogoDxe/LogoDxe.inf
 
   #
   # SCMI Driver
@@ -423,7 +436,7 @@
   #EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
   #Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
   Silicon/Rockchip/Drivers/MmcDxe/MmcDxe.inf
-  #Silicon/Rockchip/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  Silicon/Rockchip/RK3588/Drivers/DwEmmcDxe/DwEmmcDxe.inf
   Silicon/Rockchip/Drivers/SdhciHostDxe/SdhciHostDxe.inf
 
   #
@@ -448,13 +461,13 @@
   #
   # SMBIOS Support
   #
-  Platform/Radxa/ROCK5B/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+  Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
   MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
   
   #
   # USB Ohci Controller
   #
-  #Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf
+  Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf
 
   #
   # USB Ehci Controller
@@ -526,6 +539,7 @@
   MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
   MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
   MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+  MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf
   FatPkg/EnhancedFatDxe/Fat.inf
 
   #
@@ -575,8 +589,8 @@
   #
   # Custom Applications and drivers
   #
-  Platform/Radxa/ROCK5B/Applications/maskrom/maskrom.inf
+  Silicon/Rockchip/Applications/MaskromReset/maskrom.inf
 
   # Platform drivers
-  Platform/Radxa/ROCK5B/Drivers/RK3588Dxe_rock5b/RK3588Dxe.inf
+  Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf
 

edk2-platforms/Platform/Radxa/ROCK5B/ROCK5B.fdf

@@ -167,14 +167,14 @@ READ_LOCK_STATUS   = TRUE
   #INF Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
   INF Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf
   INF Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
-  INF Platform/Rockchip/RK3588/LogoDxe/LogoDxe.inf
+  INF Platform/Radxa/Drivers/LogoDxe/LogoDxe.inf
 
-  INF Platform/Radxa/ROCK5B/Drivers/RK3588Dxe_rock5b/RK3588Dxe.inf
+  INF Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf
 
   #
   # SMBIOS Support
   #
-  INF Platform/Radxa/ROCK5B/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+  INF Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
   INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
 
   #
@@ -185,7 +185,7 @@ READ_LOCK_STATUS   = TRUE
   #
   # USB Ohci Controller
   #
-  #INF Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf
+  INF Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf
 
   #
   # USB Dwc3 Controller
@@ -270,6 +270,7 @@ READ_LOCK_STATUS   = TRUE
   #
   INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
   INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf
   INF FatPkg/EnhancedFatDxe/Fat.inf
   INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
 
@@ -278,7 +279,7 @@ READ_LOCK_STATUS   = TRUE
   #
   # INF Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
   INF Silicon/Rockchip/Drivers/MmcDxe/MmcDxe.inf
-  # INF Silicon/Rockchip/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+  INF Silicon/Rockchip/RK3588/Drivers/DwEmmcDxe/DwEmmcDxe.inf
   
   # Needs to be disabled if booting from eMMC
   # INF Silicon/Rockchip/Drivers/SdhciHostDxe/SdhciHostDxe.inf
@@ -304,7 +305,7 @@ READ_LOCK_STATUS   = TRUE
   INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
 
   # Custom
-  INF Platform/Radxa/ROCK5B/Applications/maskrom/maskrom.inf
+  INF Silicon/Rockchip/Applications/MaskromReset/maskrom.inf
   
   # SCMI Driver
   INF ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf
@@ -330,7 +331,9 @@ READ_LOCK_STATUS   = TRUE
   #
   # Simple Init GUI
   #
+!if $(ENABLE_SIMPLE_INIT)
   INF src/main/SimpleInitMain.inf
+!endif
 
 [FV.BL33_AP_UEFI]
 FvAlignment        = 8

edk2-platforms/Silicon/Rockchip/Applications/MaskromReset/maskrom.inf

@@ -12,7 +12,7 @@
 [Packages]
   MdePkg/MdePkg.dec
   MdeModulePkg/MdeModulePkg.dec
-  Platform/Radxa/ROCK5B/ROCK5B.dec
+  Silicon/Rockchip/RockchipPkg.dec
 
 [LibraryClasses]
   UefiApplicationEntryPoint

edk2-platforms/Silicon/Rockchip/Drivers/PlatformSmbiosDxe/Crc32Table.h

@@ -0,0 +1,266 @@
+/** @file
+ *
+ *  Copyright (c) 2022, Jared McNeill <jmcneill@invisible.ca>
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+ 
+GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32  mCrcTable[256] = {
+  0x00000000,
+  0x77073096,
+  0xEE0E612C,
+  0x990951BA,
+  0x076DC419,
+  0x706AF48F,
+  0xE963A535,
+  0x9E6495A3,
+  0x0EDB8832,
+  0x79DCB8A4,
+  0xE0D5E91E,
+  0x97D2D988,
+  0x09B64C2B,
+  0x7EB17CBD,
+  0xE7B82D07,
+  0x90BF1D91,
+  0x1DB71064,
+  0x6AB020F2,
+  0xF3B97148,
+  0x84BE41DE,
+  0x1ADAD47D,
+  0x6DDDE4EB,
+  0xF4D4B551,
+  0x83D385C7,
+  0x136C9856,
+  0x646BA8C0,
+  0xFD62F97A,
+  0x8A65C9EC,
+  0x14015C4F,
+  0x63066CD9,
+  0xFA0F3D63,
+  0x8D080DF5,
+  0x3B6E20C8,
+  0x4C69105E,
+  0xD56041E4,
+  0xA2677172,
+  0x3C03E4D1,
+  0x4B04D447,
+  0xD20D85FD,
+  0xA50AB56B,
+  0x35B5A8FA,
+  0x42B2986C,
+  0xDBBBC9D6,
+  0xACBCF940,
+  0x32D86CE3,
+  0x45DF5C75,
+  0xDCD60DCF,
+  0xABD13D59,
+  0x26D930AC,
+  0x51DE003A,
+  0xC8D75180,
+  0xBFD06116,
+  0x21B4F4B5,
+  0x56B3C423,
+  0xCFBA9599,
+  0xB8BDA50F,
+  0x2802B89E,
+  0x5F058808,
+  0xC60CD9B2,
+  0xB10BE924,
+  0x2F6F7C87,
+  0x58684C11,
+  0xC1611DAB,
+  0xB6662D3D,
+  0x76DC4190,
+  0x01DB7106,
+  0x98D220BC,
+  0xEFD5102A,
+  0x71B18589,
+  0x06B6B51F,
+  0x9FBFE4A5,
+  0xE8B8D433,
+  0x7807C9A2,
+  0x0F00F934,
+  0x9609A88E,
+  0xE10E9818,
+  0x7F6A0DBB,
+  0x086D3D2D,
+  0x91646C97,
+  0xE6635C01,
+  0x6B6B51F4,
+  0x1C6C6162,
+  0x856530D8,
+  0xF262004E,
+  0x6C0695ED,
+  0x1B01A57B,
+  0x8208F4C1,
+  0xF50FC457,
+  0x65B0D9C6,
+  0x12B7E950,
+  0x8BBEB8EA,
+  0xFCB9887C,
+  0x62DD1DDF,
+  0x15DA2D49,
+  0x8CD37CF3,
+  0xFBD44C65,
+  0x4DB26158,
+  0x3AB551CE,
+  0xA3BC0074,
+  0xD4BB30E2,
+  0x4ADFA541,
+  0x3DD895D7,
+  0xA4D1C46D,
+  0xD3D6F4FB,
+  0x4369E96A,
+  0x346ED9FC,
+  0xAD678846,
+  0xDA60B8D0,
+  0x44042D73,
+  0x33031DE5,
+  0xAA0A4C5F,
+  0xDD0D7CC9,
+  0x5005713C,
+  0x270241AA,
+  0xBE0B1010,
+  0xC90C2086,
+  0x5768B525,
+  0x206F85B3,
+  0xB966D409,
+  0xCE61E49F,
+  0x5EDEF90E,
+  0x29D9C998,
+  0xB0D09822,
+  0xC7D7A8B4,
+  0x59B33D17,
+  0x2EB40D81,
+  0xB7BD5C3B,
+  0xC0BA6CAD,
+  0xEDB88320,
+  0x9ABFB3B6,
+  0x03B6E20C,
+  0x74B1D29A,
+  0xEAD54739,
+  0x9DD277AF,
+  0x04DB2615,
+  0x73DC1683,
+  0xE3630B12,
+  0x94643B84,
+  0x0D6D6A3E,
+  0x7A6A5AA8,
+  0xE40ECF0B,
+  0x9309FF9D,
+  0x0A00AE27,
+  0x7D079EB1,
+  0xF00F9344,
+  0x8708A3D2,
+  0x1E01F268,
+  0x6906C2FE,
+  0xF762575D,
+  0x806567CB,
+  0x196C3671,
+  0x6E6B06E7,
+  0xFED41B76,
+  0x89D32BE0,
+  0x10DA7A5A,
+  0x67DD4ACC,
+  0xF9B9DF6F,
+  0x8EBEEFF9,
+  0x17B7BE43,
+  0x60B08ED5,
+  0xD6D6A3E8,
+  0xA1D1937E,
+  0x38D8C2C4,
+  0x4FDFF252,
+  0xD1BB67F1,
+  0xA6BC5767,
+  0x3FB506DD,
+  0x48B2364B,
+  0xD80D2BDA,
+  0xAF0A1B4C,
+  0x36034AF6,
+  0x41047A60,
+  0xDF60EFC3,
+  0xA867DF55,
+  0x316E8EEF,
+  0x4669BE79,
+  0xCB61B38C,
+  0xBC66831A,
+  0x256FD2A0,
+  0x5268E236,
+  0xCC0C7795,
+  0xBB0B4703,
+  0x220216B9,
+  0x5505262F,
+  0xC5BA3BBE,
+  0xB2BD0B28,
+  0x2BB45A92,
+  0x5CB36A04,
+  0xC2D7FFA7,
+  0xB5D0CF31,
+  0x2CD99E8B,
+  0x5BDEAE1D,
+  0x9B64C2B0,
+  0xEC63F226,
+  0x756AA39C,
+  0x026D930A,
+  0x9C0906A9,
+  0xEB0E363F,
+  0x72076785,
+  0x05005713,
+  0x95BF4A82,
+  0xE2B87A14,
+  0x7BB12BAE,
+  0x0CB61B38,
+  0x92D28E9B,
+  0xE5D5BE0D,
+  0x7CDCEFB7,
+  0x0BDBDF21,
+  0x86D3D2D4,
+  0xF1D4E242,
+  0x68DDB3F8,
+  0x1FDA836E,
+  0x81BE16CD,
+  0xF6B9265B,
+  0x6FB077E1,
+  0x18B74777,
+  0x88085AE6,
+  0xFF0F6A70,
+  0x66063BCA,
+  0x11010B5C,
+  0x8F659EFF,
+  0xF862AE69,
+  0x616BFFD3,
+  0x166CCF45,
+  0xA00AE278,
+  0xD70DD2EE,
+  0x4E048354,
+  0x3903B3C2,
+  0xA7672661,
+  0xD06016F7,
+  0x4969474D,
+  0x3E6E77DB,
+  0xAED16A4A,
+  0xD9D65ADC,
+  0x40DF0B66,
+  0x37D83BF0,
+  0xA9BCAE53,
+  0xDEBB9EC5,
+  0x47B2CF7F,
+  0x30B5FFE9,
+  0xBDBDF21C,
+  0xCABAC28A,
+  0x53B39330,
+  0x24B4A3A6,
+  0xBAD03605,
+  0xCDD70693,
+  0x54DE5729,
+  0x23D967BF,
+  0xB3667A2E,
+  0xC4614AB8,
+  0x5D681B02,
+  0x2A6F2B94,
+  0xB40BBE37,
+  0xC30C8EA1,
+  0x5A05DF1B,
+  0x2D02EF8D
+};

edk2-platforms/Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c

@@ -1,7 +1,7 @@
 /** @file
  *
- *  Static SMBIOS Table for the RaspberryPi platform
- *  Derived from EmulatorPkg package
+ *  Static SMBIOS Table for RK35xx based platforms
+ *  Derived from the quartz64_uefi, RaspberryPi and EmulatorPkg packages.
  *
  *  Note - Arm SBBR ver 1.2 required and recommended SMBIOS structures:
  *    BIOS Information (Type 0)
@@ -23,12 +23,13 @@
  *    Onboard Devices Extended Information (Type 41) - Recommended
  *    Redfish Host Interface (Type 42) - Required for platforms supporting Redfish Host Interface (not applicable to RPi)
  *
- *  Copyright (c) 2017-2018, Andrey Warkentin <andrey.warkentin@gmail.com>
+ *  Copyright (c) 2017-2021, Andrey Warkentin <andrey.warkentin@gmail.com>
  *  Copyright (c) 2013, Linaro.org
  *  Copyright (c) 2012, Apple Inc. All rights reserved.<BR>
  *  Copyright (c) Microsoft Corporation. All rights reserved.
  *  Copyright (c) 2020, ARM Limited. All rights reserved.
- *  Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd.
+ *  Copyright (c) 2021 Jared McNeill <jmcneill@invisible.ca>
+ *  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
  *
  *  SPDX-License-Identifier: BSD-2-Clause-Patent
  *
@@ -50,9 +51,40 @@
 #include <Library/UefiBootServicesTableLib.h>
 #include <Library/UefiRuntimeServicesTableLib.h>
 #include <Library/PrintLib.h>
-#define ASSET_TAG_STR_STORAGE_SIZE  33
+#include <Library/CruLib.h>
+#include <Library/SdramLib.h>
+#include <Library/OtpLib.h>
+#include <Protocol/ArmScmiClockProtocol.h>
+#include "Crc32Table.h"
+
 #define SMB_IS_DIGIT(c)  (((c) >= '0') && ((c) <= '9'))
 
+STATIC UINT64 mMemorySize = 0;
+
+UINT32
+EFIAPI
+CalculateCrc32NoComp(
+  IN  UINT32                       Crc,
+  IN  VOID                         *Buffer,
+  IN  UINTN                        Length
+  )
+{
+  UINTN   Index;
+  UINT8   *Ptr;
+
+  ASSERT (Buffer != NULL);
+  ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1));
+
+  //
+  // Compute CRC
+  //
+  for (Index = 0, Ptr = Buffer; Index < Length; Index++, Ptr++) {
+    Crc = (Crc >> 8) ^ mCrcTable[(UINT8) Crc ^ *Ptr];
+  }
+
+  return Crc;
+}
+
 /***********************************************************************
         SMBIOS data definition  TYPE0  BIOS Information
 ************************************************************************/
@@ -119,12 +151,12 @@ SMBIOS_TABLE_TYPE0 mBIOSInfoType0 = {
   0,                       // SystemBiosMinorRelease
   0,                       // EmbeddedControllerFirmwareMajorRelease
   0,                       // EmbeddedControllerFirmwareMinorRelease
-  //{ (UINT16) ((FixedPcdGet32 (PcdFdSize) + FixedPcdGet32 (PcdFdtSize)) / 0x100000) }, // BiosSize (in MB since Bits 15:14 = 00b)
+  { (UINT16) (FixedPcdGet32 (PcdFdSize) / 0x100000) }, // BiosSize (in MB since Bits 15:14 = 00b)
 };
 
 CHAR8 mBiosVendor[128]  = "EDK2";
 CHAR8 mBiosVersion[128] = "EDK2-DEV";
-CHAR8 mBiosDate[12]     = "13/05/2022";
+CHAR8 mBiosDate[12]     = "00/00/0000";
 
 CHAR8 *mBIOSInfoType0Strings[] = {
   mBiosVendor,              // Vendor
@@ -150,6 +182,7 @@ SMBIOS_TABLE_TYPE1 mSysInfoType1 = {
 
 CHAR8 mSysInfoManufName[128];
 CHAR8 mSysInfoProductName[128];
+CHAR8 mSysInfoFamilyName[128];
 CHAR8 mSysInfoVersionName[128];
 CHAR8 mSysInfoSerial[sizeof (UINT64) * 2 + 1];
 CHAR8 mSysInfoSKU[sizeof (UINT64) * 2 + 1];
@@ -160,7 +193,7 @@ CHAR8 *mSysInfoType1Strings[] = {
   mSysInfoVersionName,
   mSysInfoSerial,
   mSysInfoSKU,
-  "Rockchip",
+  mSysInfoFamilyName,
   NULL
 };
 
@@ -283,7 +316,7 @@ SMBIOS_TABLE_TYPE4 mProcessorInfoType4 = {
   0,                      // ThreadCount2;
 };
 
-CHAR8 mCpuName[128] = "RK3588";
+CHAR8 mCpuName[128] = "Unknown ARM CPU";
 
 CHAR8 *mProcessorInfoType4Strings[] = {
   "Socket",
@@ -306,13 +339,8 @@ SMBIOS_TABLE_TYPE7 mCacheInfoType7_L1I = {
        //Enabled/Disabled   :1  (Enabled)
        //Operational Mode   :2  (Unknown)
        //Reserved           :6
-#if (RPI_MODEL == 4)
-  0x0030,                   // Maximum Size (RPi4: 48KB)
-  0x0030,                   // Install Size (RPi4: 48KB)
-#else
-  0x0010,                   // Maximum Size (RPi3: 16KB)
-  0x0010,                   // Install Size (RPi3: 16KB)
-#endif
+  0x0020,                   // Maximum Size (32KB)
+  0x0020,                   // Install Size (32KB)
   {                         // Supported SRAM Type
     0,  //Other             :1
     0,  //Unknown           :1
@@ -354,13 +382,8 @@ SMBIOS_TABLE_TYPE7 mCacheInfoType7_L1D = {
        //Enabled/Disabled   :1  (Enabled)
        //Operational Mode   :2  (WB)
        //Reserved           :6
-#if (RPI_MODEL == 4)
-  0x0020,                   // Maximum Size (RPi4: 32KB)
-  0x0020,                   // Install Size (RPi4: 32KB)
-#else
-  0x0010,                   // Maximum Size (RPi3: 16KB)
-  0x0010,                   // Install Size (RPi3: 16KB)
-#endif
+  0x0020,                   // Maximum Size (32KB)
+  0x0020,                   // Install Size (32KB)
   {                         // Supported SRAM Type
     0,  //Other             :1
     0,  //Unknown           :1
@@ -406,8 +429,8 @@ SMBIOS_TABLE_TYPE7 mCacheInfoType7_L2 = {
        //Enabled/Disabled   :1  (Enabled)
        //Operational Mode   :2  (WB)
        //Reserved           :6
-  0x0400,                   // Maximum Size (1MB)
-  0x0400,                   // Install Size (1MB)
+  0x0200,                   // Maximum Size (512KB)
+  0x0200,                   // Install Size (512KB)
   {                         // Supported SRAM Type
     0,  //Other             :1
     0,  //Unknown           :1
@@ -478,12 +501,14 @@ CHAR8 *mSysSlotInfoType9Strings[] = {
         SMBIOS data definition  TYPE 11  OEM Strings
 ************************************************************************/
 
+CHAR8 mOemInfoProductUrl[128];
+
 SMBIOS_TABLE_TYPE11 mOemStringsType11 = {
   { EFI_SMBIOS_TYPE_OEM_STRINGS, sizeof (SMBIOS_TABLE_TYPE11), 0 },
   1 // StringCount
 };
 CHAR8 *mOemStringsType11Strings[] = {
-  "https://github/tianocore/edk2-platforms",
+  mOemInfoProductUrl,
   NULL
 };
 
@@ -507,6 +532,8 @@ CHAR8 *mPhyMemArrayInfoType16Strings[] = {
 /***********************************************************************
         SMBIOS data definition  TYPE17  Memory Device Information
 ************************************************************************/
+CHAR8 mMemDevInfoVendor[128];
+
 SMBIOS_TABLE_TYPE17 mMemDevInfoType17 = {
   { EFI_SMBIOS_TYPE_MEMORY_DEVICE, sizeof (SMBIOS_TABLE_TYPE17), 0 },
   0,                    // MemoryArrayHandle; // Should match SMBIOS_TABLE_TYPE16.Handle, initialized at runtime, refer to PhyMemArrayInfoUpdateSmbiosType16()
@@ -574,7 +601,7 @@ SMBIOS_TABLE_TYPE17 mMemDevInfoType17 = {
 };
 CHAR8 *mMemDevInfoType17Strings[] = {
   "SDRAM",
-  "Micron",
+  mMemDevInfoVendor,
   NULL
 };
 
@@ -607,6 +634,7 @@ CHAR8 *mBootInfoType32Strings[] = {
   NULL
 };
 
+
 /**
 
    Create SMBIOS record.
@@ -727,30 +755,22 @@ BIOSInfoUpdateSmbiosType0 (
   VOID
   )
 {
-  UINT32 EpochSeconds = 0;
-  EFI_TIME Time;
-  INTN   State = 0;
   INTN   i;
+  INTN   State = 0;
   INTN   Value[2];
   INTN   Year = TIME_BUILD_YEAR;
   INTN   Month = TIME_BUILD_MONTH;
   INTN   Day = TIME_BUILD_DAY;
 
-  // Populate the Firmware major and minor.
-    // The firmware revision is really an epoch time which we convert to a
-    // YY.MM major.minor. This is good enough for our purpose, where this
-    // revision is merely provided as a loose indicator of when the
-    // VideoCore firmware was generated.
-    EpochToEfiTime (EpochSeconds, &Time);
-    ASSERT (Time.Year >= 2000 && Time.Year <= 2255);
-    mBIOSInfoType0.EmbeddedControllerFirmwareMajorRelease = (UINT8)(Time.Year - 2000);
-    mBIOSInfoType0.EmbeddedControllerFirmwareMinorRelease = Time.Month;
+  mBIOSInfoType0.EmbeddedControllerFirmwareMajorRelease = 0;
+  mBIOSInfoType0.EmbeddedControllerFirmwareMinorRelease = 0;
+
   // mBiosVendor and mBiosVersion, which are referenced in mBIOSInfoType0Strings,
   // are left unchanged if the following calls fail.
   UnicodeStrToAsciiStrS ((CHAR16*)PcdGetPtr (PcdFirmwareVendor),
-    mBiosVendor, sizeof (mBiosVendor));
+                         mBiosVendor, sizeof (mBiosVendor));
   UnicodeStrToAsciiStrS ((CHAR16*)PcdGetPtr (PcdFirmwareVersionString),
-    mBiosVersion, sizeof (mBiosVersion));
+                         mBiosVersion, sizeof (mBiosVersion));
   ASSERT (Year >= 0 && Year <= 9999);
   ASSERT (Month >= 1 && Month <= 12);
   ASSERT (Day >= 1 && Day <= 31);
@@ -839,15 +859,32 @@ SysInfoUpdateSmbiosType1 (
   VOID
   )
 {
+  UINT8 OtpData[16];
+  UINT8 SerialLo[8];
+  UINT8 SerialHi[8];
   UINT32 BoardRevision = 0;
   UINT64 BoardSerial = 0;
+  UINTN Index;
 
-  AsciiStrCpyS (mSysInfoProductName, sizeof (mSysInfoProductName),"ROCK 5B");
-  AsciiStrCpyS (mSysInfoManufName, sizeof (mSysInfoManufName),"Radxa");
+  // Get serial number from OTP
+  OtpReadId (OtpData);
+  for (Index = 0; Index < 8; Index++) {
+    SerialLo[Index] = OtpData[Index * 2 + 1];
+    SerialHi[Index] = OtpData[Index * 2];
+  }
+  BoardSerial = CalculateCrc32NoComp (0, SerialLo, sizeof SerialLo);
+  BoardSerial |= (UINT64)CalculateCrc32NoComp (BoardSerial, SerialHi, sizeof SerialHi) << 32;
+
+  AsciiStrCpyS (mSysInfoProductName, sizeof (mSysInfoProductName), (CHAR8 *) PcdGetPtr(PcdPlatformName));
+  AsciiStrCpyS (mSysInfoFamilyName, sizeof (mSysInfoFamilyName), (CHAR8 *) PcdGetPtr(PcdFamilyName));
+  AsciiStrCpyS (mSysInfoManufName, sizeof (mSysInfoManufName), (CHAR8 *) PcdGetPtr(PcdPlatformVendorName));
   AsciiSPrint (mSysInfoVersionName, sizeof (mSysInfoVersionName), "%X", BoardRevision);
+
   I64ToHexString (mSysInfoSKU, sizeof (mSysInfoSKU), BoardRevision);
   I64ToHexString (mSysInfoSerial, sizeof (mSysInfoSerial), BoardSerial);
+
   DEBUG ((DEBUG_ERROR, "Board Serial Number: %a\n", mSysInfoSerial));
+
   mSysInfoType1.Uuid.Data1 = BoardRevision;
   mSysInfoType1.Uuid.Data2 = 0x0;
   mSysInfoType1.Uuid.Data3 = 0x0;
@@ -880,12 +917,48 @@ EnclosureInfoUpdateSmbiosType3 (
 {
   EFI_SMBIOS_HANDLE SmbiosHandle;
 
+  // SMBIOS referenced strings cannot be NULL. If no AssetTag is set, default to a blank space.
+  UnicodeStrToAsciiStrS(L" ", mChassisAssetTag, sizeof(mChassisAssetTag));
+
   LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mEnclosureInfoType3, mEnclosureInfoType3Strings, &SmbiosHandle);
 
   // Set Type2 ChassisHandle to point to the newly added Type3 handle
   mBoardInfoType2.ChassisHandle = (UINT16) SmbiosHandle;
 }
 
+
+STATIC UINT32
+ProcessorGetRate (
+  VOID
+  )
+{
+  EFI_STATUS Status;
+  SCMI_CLOCK_PROTOCOL *ClockProtocol;
+  EFI_GUID ClockProtocolGuid = ARM_SCMI_CLOCK_PROTOCOL_GUID;
+  UINT64 Rate;
+  UINT32 ClockId = 0;
+
+  // If we can't query SCMI, fallback to reading from CRU registers
+  //Rate = CruGetCoreClockRate ();
+
+  Rate = 1200;
+  
+  Status = gBS->LocateProtocol (
+                  &ClockProtocolGuid,
+                  NULL,
+                  (VOID**)&ClockProtocol
+                  );
+  if (EFI_ERROR (Status)) {
+    return (UINT32)Rate;
+  }
+
+  ClockProtocol->RateGet (ClockProtocol, ClockId, &Rate);
+
+  DEBUG ((DEBUG_INFO, "SCMI: SMBIOS reported rate %luHz\n", Rate));
+  
+  return (UINT32)Rate;
+}
+
 /***********************************************************************
         SMBIOS data update  TYPE4  Processor Information
 ************************************************************************/
@@ -894,9 +967,10 @@ ProcessorInfoUpdateSmbiosType4 (
   IN UINTN MaxCpus
   )
 {
-  //EFI_STATUS Status;
- // UINT32     Rate;
-  UINT64     *ProcessorId;
+  UINT32 Rate;
+  UINT64 *ProcessorId;
+  UINT16 CpuCode;
+  UINT8 CpuVersion;
 
   mProcessorInfoType4.CoreCount = (UINT8)MaxCpus;
   mProcessorInfoType4.CoreCount2 = (UINT8)MaxCpus;
@@ -904,8 +978,24 @@ ProcessorInfoUpdateSmbiosType4 (
   mProcessorInfoType4.EnabledCoreCount2 = (UINT8)MaxCpus;
   mProcessorInfoType4.ThreadCount = (UINT8)MaxCpus;
   mProcessorInfoType4.ThreadCount2 = (UINT8)MaxCpus;
-  mProcessorInfoType4.MaxSpeed = 2100;    /*2100 MHZ*/
-  mProcessorInfoType4.CurrentSpeed = 1800;/*1800 MHZ*/
+
+  Rate = ProcessorGetRate ();
+  mProcessorInfoType4.MaxSpeed = Rate / 1000000;
+  mProcessorInfoType4.CurrentSpeed = Rate / 1000000;
+
+  OtpReadCpuCode(&CpuCode);
+  OtpReadCpuVersion(&CpuVersion);
+  CpuCode = (CpuCode >> 8) | (CpuCode << 8);
+  
+  AsciiSPrint(mCpuName, sizeof(mCpuName), "Rockchip RK%04X", CpuCode);
+
+  if (CpuVersion & BIT3) {
+    switch (CpuCode) {
+      case 0x3588:
+        AsciiStrCatS(mCpuName, sizeof(mCpuName), "S");
+        break;
+    }
+  }
 
   ProcessorId = (UINT64 *)&(mProcessorInfoType4.ProcessorId);
   *ProcessorId = ArmReadMidr();
@@ -953,6 +1043,8 @@ OemStringsUpdateSmbiosType11 (
   VOID
   )
 {
+  AsciiStrCpyS (mOemInfoProductUrl, sizeof (mOemInfoProductUrl), (CHAR8 *) PcdGetPtr(PcdProductUrl));
+
   LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mOemStringsType11, mOemStringsType11Strings, NULL);
 }
 
@@ -965,8 +1057,6 @@ PhyMemArrayInfoUpdateSmbiosType16 (
   )
 {
   EFI_SMBIOS_HANDLE MemArraySmbiosHandle;
-  EFI_STATUS        Status = 0;
-  UINT32            InstalledMB = 0;
 
  //
  // Update memory size fields:
@@ -975,15 +1065,7 @@ PhyMemArrayInfoUpdateSmbiosType16 (
  //  - Type 17 VolatileSize in Bytes
  //
 
- // The minimum RAM size used on any Raspberry Pi model is 256 MB
-  mMemDevInfoType17.Size = 256;
-
-  //Status = mFwProtocol->GetModelInstalledMB (&InstalledMB);
-  if (Status != EFI_SUCCESS) {
-    DEBUG ((DEBUG_WARN, "Couldn't get the board memory size - defaulting to 256 MB: %r\n", Status));
-  } else {
-    mMemDevInfoType17.Size = InstalledMB; // Size in MB
-  }
+  mMemDevInfoType17.Size = mMemorySize / (1024 * 1024);
 
   mPhyMemArrayInfoType16.MaximumCapacity = mMemDevInfoType17.Size * 1024; // Size in KB
   mMemDevInfoType17.VolatileSize = MultU64x32 (mMemDevInfoType17.Size, 1024 * 1024);  // Size in Bytes
@@ -1005,6 +1087,8 @@ MemDevInfoUpdateSmbiosType17 (
   VOID
   )
 {
+  AsciiStrCpyS (mMemDevInfoVendor, sizeof (mMemDevInfoVendor), (CHAR8 *) PcdGetPtr(PcdMemoryVendorName));
+
   LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mMemDevInfoType17, mMemDevInfoType17Strings, NULL);
 }
 
@@ -1016,15 +1100,11 @@ MemArrMapInfoUpdateSmbiosType19 (
   VOID
   )
 {
-  //EFI_STATUS Status;
-  //UINT32 InstalledMB = 0;
-
   // Note: Type 19 addresses are expressed in KB, not bytes
-  // The memory layout used in all known Pi SoC's starts at 0
-  mMemArrMapInfoType19.StartingAddress = 0;
-  mMemArrMapInfoType19.EndingAddress = 1024 * 1024;
-  mMemArrMapInfoType19.EndingAddress = 8192 * 1024;
-  mMemArrMapInfoType19.EndingAddress -= 1;
+  mMemArrMapInfoType19.StartingAddress = PcdGet64(PcdSystemMemoryBase) / 1024;
+
+  mMemArrMapInfoType19.EndingAddress = mMemArrMapInfoType19.StartingAddress +
+    mMemorySize / 1024 - 1;
 
   LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mMemArrMapInfoType19, mMemArrMapInfoType19Strings, NULL);
 }
@@ -1051,6 +1131,11 @@ PlatformSmbiosDriverEntryPoint (
   IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
+
+  DEBUG ((DEBUG_INFO, "PlatformSmbiosDriverEntryPoint() called\n"));
+
+  mMemorySize = SdramGetMemorySize ();
+
   BIOSInfoUpdateSmbiosType0 ();
 
   SysInfoUpdateSmbiosType1 ();
@@ -1075,5 +1160,7 @@ PlatformSmbiosDriverEntryPoint (
 
   BootInfoUpdateSmbiosType32 ();
 
+  DEBUG ((DEBUG_INFO, "PlatformSmbiosDriverEntryPoint() returning\n"));
+
   return EFI_SUCCESS;
 }

edk2-platforms/Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf

@@ -1,8 +1,10 @@
+
 #/** @file
 #
-#  SMBIOS Table for the RaspberryPi platform
+#  SMBIOS Table for RK35xx platforms
 #
-#  Copyright (c) 2017, Andrei Warkentin <andrey.warkentin@gmail.com>
+#  Copyright (c) 2021 Jared McNeill <jmcneill@invisible.ca>
+#  Copyright (c) 2017-2021 Andrei Warkentin <andrey.warkentin@gmail.com>
 #  Copyright (c) Microsoft Corporation. All rights reserved.
 #  Copyright (c) 2013 Linaro.org
 #  Copyright (c) 2020, ARM Limited. All rights reserved.
@@ -14,7 +16,7 @@
 [Defines]
   INF_VERSION                    = 0x0001001A
   BASE_NAME                      = PlatformSmbiosDxe
-  FILE_GUID                      = BAD0554E-22E9-4D83-9AFD-CC87727A1A45
+  FILE_GUID                      = 196E5BEB-983E-4B58-8292-BC310F6962DF
   MODULE_TYPE                    = DXE_DRIVER
   VERSION_STRING                 = 1.0
   ENTRY_POINT                    = PlatformSmbiosDriverEntryPoint
@@ -27,8 +29,8 @@
   MdeModulePkg/MdeModulePkg.dec
   ArmPlatformPkg/ArmPlatformPkg.dec
   ArmPkg/ArmPkg.dec
-  Platform/Rockchip/RK3588/RK3588.dec
   EmbeddedPkg/EmbeddedPkg.dec
+  Silicon/Rockchip/RockchipPkg.dec
 
 [LibraryClasses]
   ArmLib
@@ -41,24 +43,27 @@
   DebugLib
   PrintLib
   TimeBaseLib
+  CruLib
+  SdramLib
+  OtpLib
 
 [Protocols]
   gEfiSmbiosProtocolGuid           # PROTOCOL SOMETIMES_CONSUMED
-#  gRaspberryPiFirmwareProtocolGuid ## CONSUMES
 
 [Guids]
-# gConfigDxeFormSetGuid
 
 [Depex]
   gEfiSmbiosProtocolGuid
-#  AND gRaspberryPiFirmwareProtocolGuid
 
 [Pcd]
   gArmTokenSpaceGuid.PcdFdBaseAddress
   gArmTokenSpaceGuid.PcdFdSize
+  gArmTokenSpaceGuid.PcdSystemMemoryBase
   gArmTokenSpaceGuid.PcdSystemMemorySize
+  gRockchipTokenSpaceGuid.PcdPlatformName
+  gRockchipTokenSpaceGuid.PcdPlatformVendorName
+  gRockchipTokenSpaceGuid.PcdProductUrl
+  gRockchipTokenSpaceGuid.PcdFamilyName
+  gRockchipTokenSpaceGuid.PcdMemoryVendorName
   gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor
   gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
-#  gRaspberryPiTokenSpaceGuid.PcdFdtSize
-#  gRaspberryPiTokenSpaceGuid.PcdRamMoreThan3GB
-#  gRaspberryPiTokenSpaceGuid.PcdRamLimitTo3GB

edk2-platforms/Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.c

@@ -258,13 +258,6 @@ UsbEndOfDxeCallback (
  
   NumUsb2Controller = PcdGet32 (PcdNumEhciController);
 
-  /* Enable USB PHYs */
-  Usb2PhyResume();
-  
-  UsbDpPhyEnable();
-
-  UsbPortPowerEnable ();
-
   /* Register USB3 controllers */
   for (Index = 0; Index < XhciControllerAddrArraySize; Index += sizeof(UINT32)) {
     XhciControllerAddr = XhciControllerAddrArrayPtr[Index] | 

edk2-platforms/Silicon/Rockchip/Include/Library/BmcConfigBootLib.h

@@ -1,25 +0,0 @@
-/** @file
-*
-*  Copyright (c) 2017, Hisilicon Limited. All rights reserved.
-*  Copyright (c) 2017, Linaro Limited. All rights reserved.
-*
-*  SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-
-#ifndef _BMC_CONFIG_BOOT_LIB_H_
-#define _BMC_CONFIG_BOOT_LIB_H_
-
-VOID
-EFIAPI
-RestoreBootOrder (
-  VOID
-  );
-
-VOID
-EFIAPI
-HandleBmcBootType (
-  VOID
-  );
-
-#endif

edk2-platforms/Silicon/Rockchip/Include/Library/OtpLib.h

@@ -0,0 +1,35 @@
+/** @file
+ *
+ *  Copyright (c) 2022, Jared McNeill <jmcneill@invisible.ca>
+ *  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#ifndef OTPLIB_H__
+#define OTPLIB_H__
+
+VOID
+OtpRead (
+    IN UINT16 Offset,
+    IN UINT16 Length,
+    OUT UINT8 *Data
+    );
+
+VOID
+OtpReadCpuCode (
+    OUT UINT16 *CpuCode
+    );
+
+VOID
+OtpReadId (
+    OUT UINT8 Id[16]
+    );
+
+VOID
+OtpReadCpuVersion (
+    OUT UINT8 *Version
+    );
+
+#endif /* OTPLIB_H__ */

edk2-platforms/Silicon/Rockchip/Include/Library/RockchipPlatformLib.h

@@ -66,6 +66,12 @@ void
 EFIAPI
 Rk806SpiIomux(void);
 
+VOID
+EFIAPI
+Rk806Configure(
+  VOID
+  );
+
 void
 EFIAPI
 NorFspiIomux(void);

edk2-platforms/Silicon/Rockchip/Include/Library/SdramLib.h

@@ -0,0 +1,17 @@
+/** @file
+ *
+ *  Copyright (c) 2022, Jared McNeill <jmcneill@invisible.ca>
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#ifndef SDRAMLIB_H__
+#define SDRAMLIB_H__
+
+UINT64
+SdramGetMemorySize (
+    VOID
+    );
+
+#endif /* SDRAMLIB_H__ */

edk2-platforms/Silicon/Rockchip/Library/BmcConfigBootLib/BmcConfigBootLib.c

@@ -1,460 +0,0 @@
-/** @file
-*
-*  Copyright (c) 2017, Hisilicon Limited. All rights reserved.
-*  Copyright (c) 2017, Linaro Limited. All rights reserved.
-*
-*  SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-#include <Uefi.h>
-#include <Library/BaseLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/DebugLib.h>
-#include <Library/DevicePathLib.h>
-#include <Library/IpmiCmdLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/PrintLib.h>
-#include <Library/UefiBootManagerLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiLib.h>
-#include <Library/UefiRuntimeServicesTableLib.h>
-#include <Guid/GlobalVariable.h>
-#include <Protocol/DevicePathToText.h>
-
-
-STATIC
-UINT16
-EFIAPI
-GetBBSTypeFromFileSysPath (
-  IN CHAR16                   *UsbPathTxt,
-  IN CHAR16                   *FileSysPathTxt,
-  IN EFI_DEVICE_PATH_PROTOCOL *FileSysPath
-  )
-{
-  EFI_DEVICE_PATH_PROTOCOL *Node;
-
-  if (StrnCmp (UsbPathTxt, FileSysPathTxt, StrLen (UsbPathTxt)) == 0) {
-    Node = FileSysPath;
-    while (!IsDevicePathEnd (Node)) {
-      if ((DevicePathType (Node) == MEDIA_DEVICE_PATH) &&
-          (DevicePathSubType (Node) == MEDIA_CDROM_DP)) {
-        return BBS_TYPE_CDROM;
-      }
-      Node = NextDevicePathNode (Node);
-    }
-  }
-
-  return BBS_TYPE_UNKNOWN;
-}
-
-STATIC
-UINT16
-EFIAPI
-GetBBSTypeFromUsbPath (
-  IN CONST EFI_DEVICE_PATH_PROTOCOL *UsbPath
-  )
-{
-  EFI_STATUS                        Status;
-  EFI_HANDLE                        *FileSystemHandles;
-  UINTN                             NumberFileSystemHandles;
-  UINTN                             Index;
-  EFI_DEVICE_PATH_PROTOCOL          *FileSysPath;
-  EFI_DEVICE_PATH_TO_TEXT_PROTOCOL  *DevPathToText;
-  CHAR16                            *UsbPathTxt;
-  CHAR16                            *FileSysPathTxt;
-  UINT16                            Result;
-
-  Status = gBS->LocateProtocol (
-                  &gEfiDevicePathToTextProtocolGuid,
-                  NULL,
-                  (VOID **) &DevPathToText);
-  ASSERT_EFI_ERROR(Status);
-
-  Result = BBS_TYPE_UNKNOWN;
-  UsbPathTxt = DevPathToText->ConvertDevicePathToText (UsbPath, TRUE, TRUE);
-  if (UsbPathTxt == NULL) {
-    return Result;
-  }
-
-  Status = gBS->LocateHandleBuffer (
-                  ByProtocol,
-                  &gEfiSimpleFileSystemProtocolGuid,
-                  NULL,
-                  &NumberFileSystemHandles,
-                  &FileSystemHandles
-                  );
-  if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR, "Locate SimpleFileSystemProtocol error(%r)\n", Status));
-    FreePool (UsbPathTxt);
-    return BBS_TYPE_UNKNOWN;
-  }
-
-  for (Index = 0; Index < NumberFileSystemHandles; Index++) {
-    FileSysPath = DevicePathFromHandle (FileSystemHandles[Index]);
-    FileSysPathTxt = DevPathToText->ConvertDevicePathToText (FileSysPath, TRUE, TRUE);
-
-    if (FileSysPathTxt == NULL) {
-      continue;
-    }
-
-    Result = GetBBSTypeFromFileSysPath (UsbPathTxt, FileSysPathTxt, FileSysPath);
-    FreePool (FileSysPathTxt);
-
-    if (Result != BBS_TYPE_UNKNOWN) {
-      break;
-    }
-  }
-
-  if (NumberFileSystemHandles != 0) {
-    FreePool (FileSystemHandles);
-  }
-
-  FreePool (UsbPathTxt);
-
-  return Result;
-}
-
-STATIC
-UINT16
-EFIAPI
-GetBBSTypeFromMessagingDevicePath (
-  IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
-  IN EFI_DEVICE_PATH_PROTOCOL *Node
-  )
-{
-  VENDOR_DEVICE_PATH       *Vendor;
-  UINT16                   Result;
-
-  Result = BBS_TYPE_UNKNOWN;
-
-  switch (DevicePathSubType (Node)) {
-  case MSG_MAC_ADDR_DP:
-    Result = BBS_TYPE_EMBEDDED_NETWORK;
-    break;
-
-  case MSG_USB_DP:
-    Result = GetBBSTypeFromUsbPath (DevicePath);
-    if (Result == BBS_TYPE_UNKNOWN) {
-      Result = BBS_TYPE_USB;
-    }
-    break;
-
-  case MSG_SATA_DP:
-    Result = BBS_TYPE_HARDDRIVE;
-    break;
-
-  case MSG_VENDOR_DP:
-    Vendor = (VENDOR_DEVICE_PATH *) (Node);
-    if (&Vendor->Guid != NULL) {
-      if (CompareGuid (&Vendor->Guid, &((EFI_GUID) DEVICE_PATH_MESSAGING_SAS))) {
-        Result = BBS_TYPE_HARDDRIVE;
-      }
-    }
-    break;
-
-  default:
-    Result = BBS_TYPE_UNKNOWN;
-    break;
-  }
-
-  return Result;
-}
-
-STATIC
-UINT16
-EFIAPI
-GetBBSTypeByDevicePath (
-  IN EFI_DEVICE_PATH_PROTOCOL *DevicePath
-  )
-{
-  EFI_DEVICE_PATH_PROTOCOL *Node;
-  UINT16                   Result;
-
-  Result = BBS_TYPE_UNKNOWN;
-  if (DevicePath == NULL) {
-    return Result;
-  }
-
-  Node = DevicePath;
-  while (!IsDevicePathEnd (Node)) {
-    switch (DevicePathType (Node)) {
-    case MEDIA_DEVICE_PATH:
-      if (DevicePathSubType (Node) == MEDIA_CDROM_DP) {
-        Result = BBS_TYPE_CDROM;
-      }
-      break;
-
-    case MESSAGING_DEVICE_PATH:
-      Result = GetBBSTypeFromMessagingDevicePath (DevicePath, Node);
-      break;
-
-    default:
-      Result = BBS_TYPE_UNKNOWN;
-      break;
-    }
-
-    if (Result != BBS_TYPE_UNKNOWN) {
-      break;
-    }
-
-    Node = NextDevicePathNode (Node);
-  }
-
-  return Result;
-}
-
-STATIC
-EFI_STATUS
-EFIAPI
-GetBmcBootOptionsSetting (
-  OUT IPMI_GET_BOOT_OPTION *BmcBootOpt
-  )
-{
-  EFI_STATUS   Status;
-
-  Status = IpmiCmdGetSysBootOptions (BmcBootOpt);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR, "Get iBMC BootOpts %r!\n", Status));
-    return Status;
-  }
-
-  if (BmcBootOpt->BootFlagsValid != BOOT_OPTION_BOOT_FLAG_VALID) {
-    return EFI_NOT_FOUND;
-  }
-
-  if (BmcBootOpt->Persistent) {
-    BmcBootOpt->BootFlagsValid = BOOT_OPTION_BOOT_FLAG_VALID;
-  } else {
-    BmcBootOpt->BootFlagsValid = BOOT_OPTION_BOOT_FLAG_INVALID;
-  }
-
-  Status = IpmiCmdSetSysBootOptions (BmcBootOpt);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR, "Set iBMC BootOpts %r!\n", Status));
-  }
-
-  return Status;
-}
-
-VOID
-EFIAPI
-RestoreBootOrder (
-  VOID
-  )
-{
-  EFI_STATUS                Status;
-  UINT16                    *BootOrder;
-  UINTN                     BootOrderSize;
-
-  GetVariable2 (
-    L"BootOrderBackup",
-    &gOemBootVariableGuid,
-    (VOID **) &BootOrder,
-    &BootOrderSize
-    );
-  if (BootOrder == NULL) {
-    return ;
-  }
-
-  Print (L"\nRestore BootOrder(%d).\n", BootOrderSize / sizeof (UINT16));
-
-  Status = gRT->SetVariable (
-                  L"BootOrder",
-                  &gEfiGlobalVariableGuid,
-                  EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS
-                  | EFI_VARIABLE_NON_VOLATILE,
-                  BootOrderSize,
-                  BootOrder
-                  );
-  if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR, "SetVariable BootOrder %r!\n", Status));
-  }
-
-  Status = gRT->SetVariable (
-                  L"BootOrderBackup",
-                  &gOemBootVariableGuid,
-                  EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE,
-                  0,
-                  NULL
-                  );
-  if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR, "SetVariable BootOrderBackup %r!\n", Status));
-  }
-
-  FreePool (BootOrder);
-}
-
-
-STATIC
-VOID
-EFIAPI
-RestoreBootOrderOnReadyToBoot (
-  IN EFI_EVENT        Event,
-  IN VOID             *Context
-  )
-{
-  // restore BootOrder variable in normal condition.
-  RestoreBootOrder ();
-}
-
-STATIC
-VOID
-EFIAPI
-UpdateBootOrder (
-  IN UINT16  *NewOrder,
-  IN UINT16  *BootOrder,
-  IN UINTN   BootOrderSize
-  )
-{
-  EFI_STATUS  Status;
-  EFI_EVENT   Event;
-
-  Status = gRT->SetVariable (
-                  L"BootOrderBackup",
-                  &gOemBootVariableGuid,
-                  EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE,
-                  BootOrderSize,
-                  BootOrder
-                  );
-  if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR, "Set BootOrderBackup Variable:%r!\n", Status));
-    return;
-  }
-
-  Status = gRT->SetVariable (
-                  L"BootOrder",
-                  &gEfiGlobalVariableGuid,
-                  EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS
-                  | EFI_VARIABLE_NON_VOLATILE,
-                  BootOrderSize,
-                  NewOrder
-                  );
-  if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR, "Set BootOrder Variable:%r!\n", Status));
-    return;
-  }
-
-  // Register notify function to restore BootOrder variable on ReadyToBoot Event.
-  Status = gBS->CreateEventEx (
-                  EVT_NOTIFY_SIGNAL,
-                  TPL_CALLBACK,
-                  RestoreBootOrderOnReadyToBoot,
-                  NULL,
-                  &gEfiEventReadyToBootGuid,
-                  &Event
-                  );
-  if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR, "Create ready to boot event %r!\n", Status));
-  }
-}
-
-STATIC
-VOID
-EFIAPI
-SetBootOrder (
-  IN UINT16 BootType
-  )
-{
-  EFI_STATUS                   Status;
-  UINT16                       *NewOrder;
-  UINT16                       *RemainBoots;
-  UINT16                       *BootOrder;
-  UINTN                        BootOrderSize;
-  EFI_BOOT_MANAGER_LOAD_OPTION Option;
-  CHAR16                       OptionName[sizeof ("Boot####")];
-  UINTN                        Index;
-  UINTN                        SelectCnt;
-  UINTN                        RemainCnt;
-
-  GetEfiGlobalVariable2 (L"BootOrder", (VOID **) &BootOrder, &BootOrderSize);
-  if (BootOrder == NULL) {
-    return ;
-  }
-
-  NewOrder = AllocatePool (BootOrderSize);
-  RemainBoots = AllocatePool (BootOrderSize);
-  if ((NewOrder == NULL) || (RemainBoots == NULL)) {
-    DEBUG ((DEBUG_ERROR, "Out of resources."));
-    goto Exit;
-  }
-
-  SelectCnt = 0;
-  RemainCnt = 0;
-
-  for (Index = 0; Index < BootOrderSize / sizeof (UINT16); Index++) {
-    UnicodeSPrint (OptionName, sizeof (OptionName), L"Boot%04x", BootOrder[Index]);
-    Status = EfiBootManagerVariableToLoadOption (OptionName, &Option);
-    if (EFI_ERROR (Status)) {
-      DEBUG ((DEBUG_ERROR, "Boot%04x is invalid option!\n", BootOrder[Index]));
-      continue;
-    }
-
-    if (GetBBSTypeByDevicePath (Option.FilePath) == BootType) {
-      NewOrder[SelectCnt++] = BootOrder[Index];
-    } else {
-      RemainBoots[RemainCnt++] = BootOrder[Index];
-    }
-  }
-
-  if (SelectCnt != 0) {
-    // append RemainBoots to NewOrder
-    for (Index = 0; Index < RemainCnt; Index++) {
-      NewOrder[SelectCnt + Index] = RemainBoots[Index];
-    }
-
-    if (CompareMem (NewOrder, BootOrder, BootOrderSize) != 0) {
-      UpdateBootOrder (NewOrder, BootOrder, BootOrderSize);
-    }
-  }
-
-Exit:
-  FreePool (BootOrder);
-  if (NewOrder != NULL) {
-    FreePool (NewOrder);
-  }
-  if (RemainBoots != NULL) {
-    FreePool (RemainBoots);
-  }
-}
-
-VOID
-EFIAPI
-HandleBmcBootType (
-  VOID
-  )
-{
-  EFI_STATUS                Status;
-  IPMI_GET_BOOT_OPTION      BmcBootOpt;
-  UINT16                    BootType;
-
-  Status = GetBmcBootOptionsSetting (&BmcBootOpt);
-  if (EFI_ERROR (Status)) {
-    return;
-  }
-
-  Print (L"Boot Type from BMC is %x\n", BmcBootOpt.BootDeviceSelector);
-
-  switch (BmcBootOpt.BootDeviceSelector) {
-  case ForcePxe:
-    BootType = BBS_TYPE_EMBEDDED_NETWORK;
-    break;
-
-  case ForcePrimaryRemovableMedia:
-    BootType = BBS_TYPE_USB;
-    break;
-
-  case ForceDefaultHardDisk:
-    BootType = BBS_TYPE_HARDDRIVE;
-    break;
-
-  case ForceDefaultCD:
-    BootType = BBS_TYPE_CDROM;
-    break;
-
-  default:
-    return;
-  }
-
-  SetBootOrder (BootType);
-}
-

edk2-platforms/Silicon/Rockchip/Library/BmcConfigBootLib/BmcConfigBootLib.inf

@@ -1,46 +0,0 @@
-#/** @file
-#
-#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-#    Copyright (c) 2015, Linaro Limited. All rights reserved.
-#
-#    SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x0001001A
-  BASE_NAME                      = BmcConfigBootLib
-  FILE_GUID                      = 87150b08-3177-11ec-95b4-f42a7dcb925d
-  MODULE_TYPE                    = BASE
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = BmcConfigBootLib
-
-[Sources.common]
-  BmcConfigBootLib.c
-
-[Packages]
-  MdeModulePkg/MdeModulePkg.dec
-  MdePkg/MdePkg.dec
-  Silicon/Rockchip/RockchipNonOsi.dec
-  Silicon/Rockchip/RockchipPkg.dec
-
-[LibraryClasses]
-  BaseLib
-  BaseMemoryLib
-  DebugLib
-  DevicePathLib
-  IpmiCmdLib
-  PcdLib
-  PrintLib
-  UefiBootManagerLib
-
-[Guids]
-  gEfiEventReadyToBootGuid
-  gOemBootVariableGuid
-
-[Protocols]
-  gEfiDevicePathToTextProtocolGuid              ## CONSUMES
-  gEfiSimpleFileSystemProtocolGuid              ## CONSUMES
-
-[Depex]
-  gEfiDevicePathToTextProtocolGuid

edk2-platforms/Silicon/Rockchip/Library/PlatformBootManagerLib/PlatformBm.h

@@ -1,16 +1,16 @@
 /** @file
   Head file for BDS Platform specific code
 
-  Copyright (c) 2018, ARM Ltd. All rights reserved.<BR>
-  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
-  Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
+  Copyright (C) 2015-2016, Red Hat, Inc.
+  Copyright (c) 2004 - 2008, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
-#ifndef _PLATFORM_BM_H_
-#define _PLATFORM_BM_H_
+#ifndef PLATFORM_BM_H_
+#define PLATFORM_BM_H_
 
 #include <Library/BaseLib.h>
 #include <Library/BaseMemoryLib.h>
@@ -21,5 +21,33 @@
 #include <Library/UefiLib.h>
 #include <Library/UefiRuntimeServicesTableLib.h>
 
+/**
+  Use SystemTable Conout to stop video based Simple Text Out consoles from
+  going to the video device. Put up LogoFile on every video device that is a
+  console.
 
-#endif // _PLATFORM_BM_H_
+  @param[in]  LogoFile   File name of logo to display on the center of the
+                         screen.
+
+  @retval EFI_SUCCESS     ConsoleControl has been flipped to graphics and logo
+                          displayed.
+  @retval EFI_UNSUPPORTED Logo not found
+**/
+EFI_STATUS
+EnableQuietBoot (
+  IN  EFI_GUID  *LogoFile
+  );
+
+/**
+  Use SystemTable Conout to turn on video based Simple Text Out consoles. The
+  Simple Text Out screens will now be synced up with all non video output
+  devices
+
+  @retval EFI_SUCCESS     UGA devices are back in text mode and synced up.
+**/
+EFI_STATUS
+DisableQuietBoot (
+  VOID
+  );
+
+#endif // PLATFORM_BM_H_

edk2-platforms/Silicon/Rockchip/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf

@@ -1,18 +1,19 @@
 ## @file
 #  Implementation for PlatformBootManagerLib library class interfaces.
 #
-#  Copyright (c) 2018, ARM Ltd. All rights reserved.<BR>
-#  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
-#  Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
+#  Copyright (C) 2015-2016, Red Hat, Inc.
+#  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+#  Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 ##
 
 [Defines]
-  INF_VERSION                    = 0x0001001A
+  INF_VERSION                    = 0x00010005
   BASE_NAME                      = PlatformBootManagerLib
-  FILE_GUID                      = 7cee5710-3177-11ec-95b4-f42a7dcb925d
+  FILE_GUID                      = 92FD2DE3-B9CB-4B35-8141-42AD34D73C9F
   MODULE_TYPE                    = DXE_DRIVER
   VERSION_STRING                 = 1.0
   LIBRARY_CLASS                  = PlatformBootManagerLib|DXE_DRIVER
@@ -25,48 +26,72 @@
 
 [Sources]
   PlatformBm.c
+  PlatformBm.h
 
 [Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
   MdeModulePkg/MdeModulePkg.dec
   MdePkg/MdePkg.dec
-  Silicon/Rockchip/RockchipNonOsi.dec
+  ShellPkg/ShellPkg.dec
   Silicon/Rockchip/RockchipPkg.dec
+  SimpleInit.dec
 
 [LibraryClasses]
   BaseLib
   BaseMemoryLib
   BootLogoLib
-  BmcConfigBootLib
+  CapsuleLib
   DebugLib
   DevicePathLib
   DxeServicesLib
-  IpmiCmdLib
+  HobLib
   MemoryAllocationLib
   PcdLib
   PrintLib
-  TimerLib
   UefiBootManagerLib
   UefiBootServicesTableLib
   UefiLib
+  UefiRuntimeServicesTableLib
+
+[FeaturePcd]
+  gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport
 
 [FixedPcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
   gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType
-  gRockchipTokenSpaceGuid.PcdShellFile
 
 [Pcd]
   gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBootDiscoveryPolicy
 
 [Guids]
+  gBootDiscoveryPolicyMgrFormsetGuid
+  gEdkiiNonDiscoverableEhciDeviceGuid
+  gEdkiiNonDiscoverableUhciDeviceGuid
+  gEdkiiNonDiscoverableXhciDeviceGuid
+  gEfiBootManagerPolicyNetworkGuid
+  gEfiBootManagerPolicyConnectAllGuid
+  gEfiFileInfoGuid
+  gEfiFileSystemInfoGuid
+  gEfiFileSystemVolumeLabelInfoIdGuid
   gEfiEndOfDxeEventGroupGuid
   gEfiTtyTermGuid
-  gOemConfigGuid
+  gUefiShellFileGuid
+  gSimpleInitFileGuid
+  gMaskromFileGuid
 
 [Protocols]
-  gEfiGenericMemTestProtocolGuid
+  gEdkiiNonDiscoverableDeviceProtocolGuid
+  gEfiBootManagerPolicyProtocolGuid
+  gEfiDevicePathProtocolGuid
+  gEfiGraphicsOutputProtocolGuid
   gEfiLoadedImageProtocolGuid
+  gEfiPciRootBridgeIoProtocolGuid
+  gEfiSimpleFileSystemProtocolGuid
   gEsrtManagementProtocolGuid
-  gPlatformSasNotifyProtocolGuid
+  gPlatformBootManagerProtocolGuid

edk2-platforms/Silicon/Rockchip/Library/ResetSystemLib/ResetSystemLib.inf

@@ -22,7 +22,7 @@
   ArmPkg/ArmPkg.dec
   MdeModulePkg/MdeModulePkg.dec
   MdePkg/MdePkg.dec
-  Platform/Radxa/ROCK5B/ROCK5B.dec
+  Silicon/Rockchip/RockchipPkg.dec
 
 [LibraryClasses]
   ArmSmcLib

edk2-platforms/Silicon/Rockchip/Library/RkMtlLib/RkMtlLib.inf

@@ -20,7 +20,7 @@
   ArmPkg/ArmPkg.dec
   ArmPlatformPkg/ArmPlatformPkg.dec
   MdePkg/MdePkg.dec
-  Platform/Radxa/ROCK5B/ROCK5B.dec
+  Silicon/Rockchip/RockchipPkg.dec
 
 [LibraryClasses]
   ArmLib
@@ -30,6 +30,6 @@
   UefiBootServicesTableLib
 
 [FixedPcd.common]
-  gROCK5BTokenSpaceGuid.PcdRkMtlMailBoxBase
-  gROCK5BTokenSpaceGuid.PcdRkMtlMailBoxSize
-  gROCK5BTokenSpaceGuid.PcdRkMtlMailBoxSmcId
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSmcId

edk2-platforms/Silicon/Rockchip/Library/SdramLib/SdramLib.c

@@ -0,0 +1,129 @@
+/** @file
+ *
+ *  SDRAM size detection for Rockchip SoCs
+ *
+ *  Copyright (c) 2022, Jared McNeill <jmcneill@invisible.ca>
+ *  Copyright (c) 2023, Gábor Stefanik <netrolller.3d@gmail.com>
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/SdramLib.h>
+
+// TODO convert these to PCDs
+#define SDRAM_OS_REG_BASE 0xFD58A208
+#define SDRAM_BANK_COUNT 2
+
+typedef enum {
+    SDRAM_DDR4 = 0,
+    SDRAM_DDR2 = 2,
+    SDRAM_DDR3 = 3,
+    SDRAM_LPDDR2 = 5,
+    SDRAM_LPDDR3 = 6,
+    SDRAM_LPDDR4 = 7,
+    SDRAM_LPDDR4X = 8,
+    SDRAM_LPDDR5 = 9,
+    SDRAM_DDR5 = 10
+} SDRAM_DDRTYPE;
+
+#define SYS_REG_DDRTYPE(x)              (((x) >> 13) & 0x7)
+#define SYS_REG_CHANNELNUM(x)           (((x) >> 12) & 0x1)
+#define SYS_REG_RANK_CH(x, c)           (((x) >> ((c) ? 27 : 11)) & 0x1)
+#define SYS_REG_COL_CH(x, c)            (((x) >> ((c) ? 25 : 9)) & 0x3)
+#define SYS_REG_BK_CH(x, c)             (((x) >> ((c) ? 24 : 8)) & 0x1)
+#define SYS_REG_CS0_ROW_CH_LO(x, c)     (((x) >> ((c) ? 22 : 6)) & 0x3)
+#define SYS_REG_CS1_ROW_CH_LO(x, c)     (((x) >> ((c) ? 20 : 4)) & 0x3)
+#define SYS_REG_BW_CH(x, c)             (((x) >> ((c) ? 18 : 2)) & 0x3)
+#define SYS_REG_ROW34_CH(x, c)          (((x) >> ((c) ? 31 : 30)) & 0x1)
+#define SYS_REG_DBW_CH(x, c)            (((x) >> ((c) ? 16 : 0)) & 0x3)
+
+#define SYS_REG1_VERSION(x)             (((x) >> 28) & 0xF)
+#define SYS_REG1_CS0_ROW_CH_HI(x, c)    (((x) >> ((c) ? 7 : 5)) & 0x1)
+#define SYS_REG1_CS1_ROW_CH_HI(x, c)    (((x) >> ((c) ? 6 : 4)) & 0x1)
+#define SYS_REG1_CS1_COL_CH(x, c)       (((x) >> ((c) ? 2 : 0)) & 0x3)
+
+UINT64
+SdramGetMemorySize (
+    VOID
+    )
+{
+    UINT32 OsReg;
+    UINT32 OsReg1;
+	INT32 Bank;
+    INT32 ChNum;
+    INT32 Ch;
+    INT32 Rank;
+    INT32 Cs0Col, Cs1Col;
+    INT32 Cs0Row, Cs1Row;
+    INT32 Bk;
+    INT32 Bw;
+    INT32 Row34;
+    INT32 Bg;
+    INT32 ChSizeMb;
+    INT32 SizeMb = 0;
+
+    for (Bank = 0; Bank < SDRAM_BANK_COUNT; Bank++) {
+
+        OsReg = MmioRead32 (SDRAM_OS_REG_BASE + 8 * Bank);
+        OsReg1 = MmioRead32 (SDRAM_OS_REG_BASE + 8 * Bank + 4);
+
+        ChNum = 1 + SYS_REG_CHANNELNUM(OsReg);
+
+        DEBUG ((DEBUG_INFO, "%a(): Bank #%d: %d channel(s), type 0x%X, version 0x%X\n",
+                __func__, Bank, ChNum, SYS_REG_DDRTYPE(OsReg), SYS_REG1_VERSION(OsReg1)));
+
+        for (Ch = 0; Ch < ChNum; Ch++) {
+            Rank = 1 + SYS_REG_RANK_CH(OsReg, Ch);
+            Cs0Col = 9 + SYS_REG_COL_CH(OsReg, Ch);
+            Cs1Col = Cs0Col;
+            Bk = 3 - SYS_REG_BK_CH(OsReg, Ch);
+            if (SYS_REG1_VERSION(OsReg1) >= 0x2) {
+                Cs1Col = 9 + SYS_REG1_CS1_COL_CH(OsReg1, Ch);
+                if (((SYS_REG1_CS0_ROW_CH_HI(OsReg1, Ch) << 2) +
+                      SYS_REG_CS0_ROW_CH_LO(OsReg, Ch)) == 7) {
+                    Cs0Row = 12;
+                } else {
+                    Cs0Row = 13 + (SYS_REG1_CS0_ROW_CH_HI(OsReg1, Ch) << 2) +
+                             SYS_REG_CS0_ROW_CH_LO(OsReg, Ch);
+                }
+                if (((SYS_REG1_CS1_ROW_CH_HI(OsReg1, Ch) << 2) +
+                      SYS_REG_CS1_ROW_CH_LO(OsReg, Ch)) == 7) {
+                    Cs1Row = 12;
+                } else {
+                    Cs1Row = 13 + (SYS_REG1_CS1_ROW_CH_HI(OsReg1, Ch) << 2) +
+                             SYS_REG_CS1_ROW_CH_LO(OsReg, Ch);
+                }
+            } else {
+                Cs0Row = 13 + SYS_REG_CS0_ROW_CH_LO(OsReg, Ch);
+                Cs1Row = 13 + SYS_REG_CS1_ROW_CH_LO(OsReg, Ch);
+            }
+            Bw = 2 >> SYS_REG_BW_CH(OsReg, Ch);
+            Row34 = SYS_REG_ROW34_CH(OsReg, Ch);
+            if (SYS_REG_DDRTYPE(OsReg) == SDRAM_DDR4 && SYS_REG1_VERSION(OsReg1) != 0x3) {
+                Bg = SYS_REG_DBW_CH(OsReg, Ch) == 2 ? 2 : 1;
+            } else {
+                Bg = 0;
+            }
+
+            ChSizeMb = 1 << (Cs0Row + Cs0Col + Bk + Bg + Bw - 20);
+            if (Rank > 1) {
+                ChSizeMb += ChSizeMb >> ((Cs0Row - Cs1Row) + (Cs0Col - Cs1Col));
+            }
+            if (Row34) {
+                ChSizeMb = ChSizeMb * 3 / 4;
+            }
+
+            DEBUG ((DEBUG_INFO, "%a(): Ch #%d: %u MB\n", __func__, Ch + Bank * 2, ChSizeMb));
+            SizeMb += ChSizeMb;
+        }
+	}
+
+    DEBUG ((DEBUG_INFO, "%a(): Detected %u MB RAM\n", __func__, SizeMb));
+
+    ASSERT (SizeMb != 0);
+
+    return (UINT64)SizeMb * 1024 * 1024;
+}

edk2-platforms/Silicon/Rockchip/Library/SdramLib/SdramLib.inf

@@ -0,0 +1,36 @@
+#/** @file
+#
+#  Rockchip SDRAM Library.
+#
+#  Copyright (c) 2022, Jared McNeill <jmcneill@invisible.ca>
+#  Copyright (c) 2023, Gábor Stefanik <netrolller.3d@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = SdramLib
+  FILE_GUID                      = F1722CDD-AB5E-4341-8E98-C04CA151D5FB
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = SdramLib
+
+[Sources]
+  SdramLib.c
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdePkg/MdePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  IoLib
+
+[FixedPcd]
+
+[Guids]

edk2-platforms/Silicon/Rockchip/RK3588/AcpiTables/Cpu.asl

@@ -0,0 +1,94 @@
+/** @file
+ *
+ *  RK3588 CPU devices.
+ *
+ *  Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ *  Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
+ *  Copyright (c) Microsoft Corporation. All rights reserved.
+ *  Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include "AcpiTables.h"
+
+Device (CPU0)
+{
+  Name (_HID, "ACPI0007")
+  Name (_UID, 0x0)
+  Method (_STA)
+  {
+    Return (0xf)
+  }
+}
+
+Device (CPU1)
+{
+  Name (_HID, "ACPI0007")
+  Name (_UID, 0x1)
+  Method (_STA)
+  {
+    Return (0xf)
+  }
+}
+
+Device (CPU2)
+{
+  Name (_HID, "ACPI0007")
+  Name (_UID, 0x2)
+  Method (_STA)
+  {
+    Return (0xf)
+  }
+}
+
+Device (CPU3)
+{
+  Name (_HID, "ACPI0007")
+  Name (_UID, 0x3)
+  Method (_STA)
+  {
+    Return (0xf)
+  }
+}
+
+Device (CPU4)
+{
+  Name (_HID, "ACPI0007")
+  Name (_UID, 0x4)
+  Method (_STA)
+  {
+    Return (0xf)
+  }
+}
+
+Device (CPU5)
+{
+  Name (_HID, "ACPI0007")
+  Name (_UID, 0x5)
+  Method (_STA)
+  {
+    Return (0xf)
+  }
+}
+
+Device (CPU6)
+{
+  Name (_HID, "ACPI0007")
+  Name (_UID, 0x6)
+  Method (_STA)
+  {
+    Return (0xf)
+  }
+}
+
+Device (CPU7)
+{
+  Name (_HID, "ACPI0007")
+  Name (_UID, 0x7)
+  Method (_STA)
+  {
+    Return (0xf)
+  }
+}

edk2-platforms/Silicon/Rockchip/RK3588/AcpiTables/RK3588PcieIort.aslc

@@ -117,7 +117,7 @@ ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort =
         1,  // NumIdMappings
         OFFSET_OF (ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE, RcIdMap)  // IdReference
       },
-      1,  // CacheCoherent
+      0,  // CacheCoherent
       0,  // AllocationHints
       0,  // Reserved
       0,  // MemoryAccessFlags

edk2-platforms/Silicon/Rockchip/RK3588/AcpiTables/Sdhc.asl

@@ -0,0 +1,31 @@
+/** @file
+ *
+ *  Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+#include "AcpiTables.h"
+
+
+  Device (SDHC)
+  {
+    Name (_HID, "RKCPFE2C")
+    Name (_UID, 0x1)
+    Name (_CCA, 0x0)
+    Name (_S1D, 0x1)
+    Name (_S2D, 0x1)
+    Name (_S3D, 0x1)
+    Name (_S4D, 0x1)
+    Method (_STA)
+    {
+      Return(0xf)
+    }
+    Method (_CRS, 0x0, Serialized) {
+      Name (RBUF, ResourceTemplate() {
+        Memory32Fixed (ReadWrite, 0xfe2c0000, 0x4000)
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 235 }
+      })
+      Return (RBUF)
+    }
+  } //SDHC

edk2-platforms/Silicon/Rockchip/RK3588/AcpiTables/Usb3Host0.asl

@@ -0,0 +1,23 @@
+/** @file
+*  DWC3 XHCI controller #0 in host mode.
+*
+*  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "AcpiTables.h"
+
+Device (XHC0) {
+    Name (_HID, "PNP0D10")
+    Name (_UID, Zero)
+    Name (_CCA, Zero)
+
+    Method (_CRS, 0x0, Serialized) {
+        Name (RBUF, ResourceTemplate() {
+            Memory32Fixed (ReadWrite, 0xfc000000, 0x400000)
+            Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 252 }
+        })
+        Return (RBUF)
+    }   
+}

edk2-platforms/Silicon/Rockchip/RK3588/AcpiTables/Usb3Host1.asl

@@ -0,0 +1,23 @@
+/** @file
+*  DWC3 XHCI controller #1 in host mode. (only exposed on full RK3588)
+*
+*  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "AcpiTables.h"
+
+Device (XHC1) {
+    Name (_HID, "PNP0D10")
+    Name (_UID, One)
+    Name (_CCA, Zero)
+
+    Method (_CRS, 0x0, Serialized) {
+        Name (RBUF, ResourceTemplate() {
+            Memory32Fixed (ReadWrite, 0xfc400000, 0x400000)
+            Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 253 }
+        })
+        Return (RBUF)
+    }   
+}

edk2-platforms/Silicon/Rockchip/RK3588/AcpiTables/Usb3Host2.asl

@@ -0,0 +1,26 @@
+/** @file
+*  DWC3 XHCI controller #2 in host mode.
+*
+*  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "AcpiTables.h"
+
+// This only supports USB 3.0 devices.
+// USB2 DP / DM are connected to one of the EHCI controllers instead (EHC1 usually).
+
+Device (XHC2) {
+    Name (_HID, "PNP0D10")
+    Name (_UID, 2)
+    Name (_CCA, Zero)
+
+    Method (_CRS, 0x0, Serialized) {
+        Name (RBUF, ResourceTemplate() {
+            Memory32Fixed (ReadWrite, 0xfcd00000, 0x400000)
+            Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 254 }
+        })
+        Return (RBUF)
+    }   
+}

edk2-platforms/Silicon/Rockchip/RK3588/Drivers/DwEmmcDxe/DwEmmc.h

@@ -0,0 +1,132 @@
+/** @file
+*
+*  WARNING:
+*  This driver fails to follow the UEFI driver model without a good
+*  reason, and only remains in the tree because it is still used by
+*  a small number of platforms. It will be removed when no longer used.
+*
+*  Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+
+#ifndef __DWEMMC_H__
+#define __DWEMMC_H__
+
+#include <Protocol/EmbeddedGpio.h>
+
+// DW MMC Registers
+#define DWEMMC_CTRL             ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x000)
+#define DWEMMC_PWREN            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x004)
+#define DWEMMC_CLKDIV           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x008)
+#define DWEMMC_CLKSRC           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x00c)
+#define DWEMMC_CLKENA           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x010)
+#define DWEMMC_TMOUT            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x014)
+#define DWEMMC_CTYPE            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x018)
+#define DWEMMC_BLKSIZ           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x01c)
+#define DWEMMC_BYTCNT           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x020)
+#define DWEMMC_INTMASK          ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x024)
+#define DWEMMC_CMDARG           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x028)
+#define DWEMMC_CMD              ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x02c)
+#define DWEMMC_RESP0            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x030)
+#define DWEMMC_RESP1            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x034)
+#define DWEMMC_RESP2            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x038)
+#define DWEMMC_RESP3            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x03c)
+#define DWEMMC_RINTSTS          ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x044)
+#define DWEMMC_STATUS           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x048)
+#define DWEMMC_FIFOTH           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x04c)
+#define DWEMMC_TCBCNT           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x05c)
+#define DWEMMC_TBBCNT           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x060)
+#define DWEMMC_DEBNCE           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x064)
+#define DWEMMC_HCON             ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x070)
+#define DWEMMC_UHSREG           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x074)
+#define DWEMMC_BMOD             ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x080)
+#define DWEMMC_DBADDR           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x088)
+#define DWEMMC_IDSTS            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x08c)
+#define DWEMMC_IDINTEN          ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x090)
+#define DWEMMC_DSCADDR          ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x094)
+#define DWEMMC_BUFADDR          ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x098)
+#define DWEMMC_CARDTHRCTL       ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0X100)
+#define DWEMMC_DATA             ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0X200)
+
+#define CMD_UPDATE_CLK                          0x80202000
+#define CMD_START_BIT                           (1 << 31)
+
+#define MMC_8BIT_MODE                           (1 << 16)
+
+#define BIT_CMD_RESPONSE_EXPECT                 (1 << 6)
+#define BIT_CMD_LONG_RESPONSE                   (1 << 7)
+#define BIT_CMD_CHECK_RESPONSE_CRC              (1 << 8)
+#define BIT_CMD_DATA_EXPECTED                   (1 << 9)
+#define BIT_CMD_READ                            (0 << 10)
+#define BIT_CMD_WRITE                           (1 << 10)
+#define BIT_CMD_BLOCK_TRANSFER                  (0 << 11)
+#define BIT_CMD_STREAM_TRANSFER                 (1 << 11)
+#define BIT_CMD_SEND_AUTO_STOP                  (1 << 12)
+#define BIT_CMD_WAIT_PRVDATA_COMPLETE           (1 << 13)
+#define BIT_CMD_STOP_ABORT_CMD                  (1 << 14)
+#define BIT_CMD_SEND_INIT                       (1 << 15)
+#define BIT_CMD_UPDATE_CLOCK_ONLY               (1 << 21)
+#define BIT_CMD_READ_CEATA_DEVICE               (1 << 22)
+#define BIT_CMD_CCS_EXPECTED                    (1 << 23)
+#define BIT_CMD_ENABLE_BOOT                     (1 << 24)
+#define BIT_CMD_EXPECT_BOOT_ACK                 (1 << 25)
+#define BIT_CMD_DISABLE_BOOT                    (1 << 26)
+#define BIT_CMD_MANDATORY_BOOT                  (0 << 27)
+#define BIT_CMD_ALTERNATE_BOOT                  (1 << 27)
+#define BIT_CMD_VOLT_SWITCH                     (1 << 28)
+#define BIT_CMD_USE_HOLD_REG                    (1 << 29)
+#define BIT_CMD_START                           (1 << 31)
+
+#define DWEMMC_INT_EBE                          (1 << 15)       /* End-bit Err */
+#define DWEMMC_INT_SBE                          (1 << 13)       /* Start-bit  Err */
+#define DWEMMC_INT_HLE                          (1 << 12)       /* Hardware-lock Err */
+#define DWEMMC_INT_FRUN                         (1 << 11)       /* FIFO UN/OV RUN */
+#define DWEMMC_INT_DRT                          (1 << 9)        /* Data timeout */
+#define DWEMMC_INT_RTO                          (1 << 8)        /* Response timeout */
+#define DWEMMC_INT_DCRC                         (1 << 7)        /* Data CRC err */
+#define DWEMMC_INT_RCRC                         (1 << 6)        /* Response CRC err */
+#define DWEMMC_INT_RXDR                         (1 << 5)
+#define DWEMMC_INT_TXDR                         (1 << 4)
+#define DWEMMC_INT_DTO                          (1 << 3)        /* Data trans over */
+#define DWEMMC_INT_CMD_DONE                     (1 << 2)
+#define DWEMMC_INT_RE                           (1 << 1)
+
+#define DWEMMC_IDMAC_DES0_DIC                   (1 << 1)
+#define DWEMMC_IDMAC_DES0_LD                    (1 << 2)
+#define DWEMMC_IDMAC_DES0_FS                    (1 << 3)
+#define DWEMMC_IDMAC_DES0_CH                    (1 << 4)
+#define DWEMMC_IDMAC_DES0_ER                    (1 << 5)
+#define DWEMMC_IDMAC_DES0_CES                   (1 << 30)
+#define DWEMMC_IDMAC_DES0_OWN                   (1 << 31)
+#define DWEMMC_IDMAC_DES1_BS1(x)                ((x) & 0x1fff)
+#define DWEMMC_IDMAC_DES2_BS2(x)                (((x) & 0x1fff) << 13)
+#define DWEMMC_IDMAC_SWRESET                    (1 << 0)
+#define DWEMMC_IDMAC_FB                         (1 << 1)
+#define DWEMMC_IDMAC_ENABLE                     (1 << 7)
+
+#define EMMC_FIX_RCA                            6
+
+/* bits in MMC0_CTRL */
+#define DWEMMC_CTRL_RESET                       (1 << 0)
+#define DWEMMC_CTRL_FIFO_RESET                  (1 << 1)
+#define DWEMMC_CTRL_DMA_RESET                   (1 << 2)
+#define DWEMMC_CTRL_INT_EN                      (1 << 4)
+#define DWEMMC_CTRL_DMA_EN                      (1 << 5)
+#define DWEMMC_CTRL_IDMAC_EN                    (1 << 25)
+#define DWEMMC_CTRL_RESET_ALL                   (DWEMMC_CTRL_RESET | DWEMMC_CTRL_FIFO_RESET | DWEMMC_CTRL_DMA_RESET)
+
+#define DWEMMC_STS_DATA_BUSY                    (1 << 9)
+
+#define DWEMMC_FIFO_TWMARK(x)                   (x & 0xfff)
+#define DWEMMC_FIFO_RWMARK(x)                   ((x & 0x1ff) << 16)
+#define DWEMMC_DMA_BURST_SIZE(x)                ((x & 0x7) << 28)
+
+#define DWEMMC_CARD_RD_THR(x)                   ((x & 0xfff) << 16)
+#define DWEMMC_CARD_RD_THR_EN                   (1 << 0)
+
+#define DWEMMC_GET_HDATA_WIDTH(x)               (((x) >> 7) & 0x7)
+
+#endif  // __DWEMMC_H__

edk2-platforms/Silicon/Rockchip/RK3588/Drivers/DwEmmcDxe/DwEmmcDxe.c

@@ -0,0 +1,763 @@
+/** @file
+  This file implement the MMC Host Protocol for the DesignWare eMMC.
+
+  WARNING:
+  This driver fails to follow the UEFI driver model without a good
+  reason, and only remains in the tree because it is still used by
+  a small number of platforms. It will be removed when no longer used.
+
+  Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/TimerLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+
+#include <Protocol/MmcHost.h>
+#include <Protocol/ArmScmi.h>
+#include <Protocol/ArmScmiClockProtocol.h>
+#include <Library/RockchipPlatformLib.h>
+#include "Include/Library/CruLib.h"
+#include "Soc.h"
+#include "DwEmmc.h"
+
+#define SCMI_CCLK_SD			9
+
+#define DW_DBG		DEBUG_BLKIO
+
+#define DWEMMC_DESC_PAGE                1
+#define DWEMMC_BLOCK_SIZE               512
+#define DWEMMC_DMA_BUF_SIZE             (512 * 8)
+#define DWEMMC_MAX_DESC_PAGES           512
+
+typedef struct {
+  UINT32                        Des0;
+  UINT32                        Des1;
+  UINT32                        Des2;
+  UINT32                        Des3;
+} DWEMMC_IDMAC_DESCRIPTOR;
+
+EFI_MMC_HOST_PROTOCOL     *gpMmcHost;
+DWEMMC_IDMAC_DESCRIPTOR   *gpIdmacDesc;
+EFI_GUID mDwEmmcDevicePathGuid = EFI_CALLER_ID_GUID;
+STATIC UINT32 mDwEmmcCommand;
+STATIC UINT32 mDwEmmcArgument;
+
+EFI_STATUS
+DwEmmcReadBlockData (
+  IN EFI_MMC_HOST_PROTOCOL     *This,
+  IN EFI_LBA                    Lba,
+  IN UINTN                      Length,
+  IN UINT32*                    Buffer
+  );
+
+BOOLEAN
+DwEmmcIsPowerOn (
+  VOID
+  )
+{
+    return TRUE;
+}
+
+EFI_STATUS
+DwEmmcInitialize (
+  VOID
+  )
+{
+    DEBUG ((DEBUG_BLKIO, "DwEmmcInitialize()"));
+    return EFI_SUCCESS;
+}
+
+BOOLEAN
+DwEmmcIsCardPresent (
+  IN EFI_MMC_HOST_PROTOCOL     *This
+  )
+{
+  /* check card present */
+  return TRUE;
+}
+
+BOOLEAN
+DwEmmcIsReadOnly (
+  IN EFI_MMC_HOST_PROTOCOL     *This
+  )
+{
+  return FALSE;
+}
+
+BOOLEAN
+DwEmmcIsDmaSupported (
+  IN EFI_MMC_HOST_PROTOCOL     *This
+  )
+{
+  return TRUE;
+}
+
+EFI_STATUS
+DwEmmcBuildDevicePath (
+  IN EFI_MMC_HOST_PROTOCOL      *This,
+  IN EFI_DEVICE_PATH_PROTOCOL   **DevicePath
+  )
+{
+  EFI_DEVICE_PATH_PROTOCOL *NewDevicePathNode;
+
+  NewDevicePathNode = CreateDeviceNode (HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH));
+  CopyGuid (& ((VENDOR_DEVICE_PATH*)NewDevicePathNode)->Guid, &mDwEmmcDevicePathGuid);
+
+  *DevicePath = NewDevicePathNode;
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+DwEmmcUpdateClock (
+  VOID
+  )
+{
+  UINT32 Data;
+
+  /* CMD_UPDATE_CLK */
+  Data = BIT_CMD_WAIT_PRVDATA_COMPLETE | BIT_CMD_UPDATE_CLOCK_ONLY |
+         BIT_CMD_START;
+  MmioWrite32 (DWEMMC_CMD, Data);
+  while (1) {
+    Data = MmioRead32 (DWEMMC_CMD);
+    if (!(Data & CMD_START_BIT)) {
+      break;
+    }
+    Data = MmioRead32 (DWEMMC_RINTSTS);
+    if (Data & DWEMMC_INT_HLE) {
+      Print (L"failed to update mmc clock frequency\n");
+      return EFI_DEVICE_ERROR;
+    }
+  }
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+DwEmmcSetClock (
+  IN UINTN                     ClockFreq
+  )
+{
+  UINT32 Data;
+  EFI_STATUS Status;
+  SCMI_CLOCK_PROTOCOL    *ClockProtocol;
+  EFI_GUID               ClockProtocolGuid = ARM_SCMI_CLOCK_PROTOCOL_GUID;
+
+  // Wait until MMC is idle
+  do {
+    Data = MmioRead32 (DWEMMC_STATUS);
+  } while (Data & DWEMMC_STS_DATA_BUSY);
+
+  // Disable MMC clock first
+  MmioWrite32 (DWEMMC_CLKENA, 0);
+  Status = DwEmmcUpdateClock ();
+  ASSERT (!EFI_ERROR (Status));
+  //HAL_CRU_ClkSetFreq(CLK_SDMMC0, ClockFreq);
+  //DEBUG ((DW_DBG, "%a():HAL_CRU_ClkGetFreq:%d\n", __func__, HAL_CRU_ClkGetFreq(CLK_SDMMC0)));
+  Status = gBS->LocateProtocol (
+                  &ClockProtocolGuid,
+                  NULL,
+                  (VOID**)&ClockProtocol
+                  );
+  ASSERT (!EFI_ERROR (Status));
+  MmioWrite32 (DWEMMC_CLKDIV, 1);
+  Status = DwEmmcUpdateClock ();
+  ASSERT (!EFI_ERROR (Status));
+  Status = ClockProtocol->RateSet (
+                            ClockProtocol,
+                            SCMI_CCLK_SD,
+                            ClockFreq
+                            );
+  ASSERT (!EFI_ERROR (Status));
+  // Enable MMC clock
+  MmioWrite32 (DWEMMC_CLKENA, 1);
+  MmioWrite32 (DWEMMC_CLKSRC, 0);
+  Status = DwEmmcUpdateClock ();
+  ASSERT (!EFI_ERROR (Status));
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+DwEmmcNotifyState (
+  IN EFI_MMC_HOST_PROTOCOL     *This,
+  IN MMC_STATE                 State
+  )
+{
+  UINT32      Data;
+  EFI_STATUS  Status;
+
+  switch (State) {
+  case MmcInvalidState:
+    return EFI_INVALID_PARAMETER;
+  case MmcHwInitializationState:
+    MmioWrite32 (DWEMMC_PWREN, 1);
+
+    // If device already turn on then restart it
+    Data = DWEMMC_CTRL_RESET_ALL;
+    MmioWrite32 (DWEMMC_CTRL, Data);
+    do {
+      // Wait until reset operation finished
+      Data = MmioRead32 (DWEMMC_CTRL);
+    } while (Data & DWEMMC_CTRL_RESET_ALL);
+
+    // Setup clock that could not be higher than 400KHz.
+    Status = DwEmmcSetClock (400000);
+    ASSERT (!EFI_ERROR (Status));
+    // Wait clock stable
+    MicroSecondDelay (100);
+
+    MmioWrite32 (DWEMMC_RINTSTS, ~0);
+    MmioWrite32 (DWEMMC_INTMASK, 0);
+    MmioWrite32 (DWEMMC_TMOUT, ~0);
+    MmioWrite32 (DWEMMC_IDINTEN, 0);
+    MmioWrite32 (DWEMMC_BMOD, DWEMMC_IDMAC_SWRESET);
+    MmioWrite32 (DWEMMC_CTYPE, 0);
+    MmioWrite32 (DWEMMC_BLKSIZ, DWEMMC_BLOCK_SIZE);
+    do {
+      Data = MmioRead32 (DWEMMC_BMOD);
+    } while (Data & DWEMMC_IDMAC_SWRESET);
+    break;
+  case MmcIdleState:
+    break;
+  case MmcReadyState:
+    break;
+  case MmcIdentificationState:
+    break;
+  case MmcStandByState:
+    break;
+  case MmcTransferState:
+    break;
+  case MmcSendingDataState:
+    break;
+  case MmcReceiveDataState:
+    break;
+  case MmcProgrammingState:
+    break;
+  case MmcDisconnectState:
+    break;
+  default:
+    return EFI_INVALID_PARAMETER;
+  }
+  return EFI_SUCCESS;
+}
+
+// Need to prepare DMA buffer first before sending commands to MMC card
+BOOLEAN
+IsPendingReadCommand (
+  IN MMC_CMD                    MmcCmd
+  )
+{
+  UINTN  Mask;
+
+  Mask = BIT_CMD_DATA_EXPECTED | BIT_CMD_READ;
+  if ((MmcCmd & Mask) == Mask) {
+    return TRUE;
+  }
+  return FALSE;
+}
+
+BOOLEAN
+IsPendingWriteCommand (
+  IN MMC_CMD                    MmcCmd
+  )
+{
+  UINTN  Mask;
+
+  Mask = BIT_CMD_DATA_EXPECTED | BIT_CMD_WRITE;
+  if ((MmcCmd & Mask) == Mask) {
+    return TRUE;
+  }
+  return FALSE;
+}
+
+EFI_STATUS
+SendCommand (
+  IN MMC_CMD                    MmcCmd,
+  IN UINT32                     Argument
+  )
+{
+  UINT32      Data, ErrMask;
+
+  // Wait until MMC is idle
+  do {
+    Data = MmioRead32 (DWEMMC_STATUS);
+  } while (Data & DWEMMC_STS_DATA_BUSY);
+
+  MmioWrite32 (DWEMMC_RINTSTS, ~0);
+  MmioWrite32 (DWEMMC_CMDARG, Argument);
+  MmioWrite32 (DWEMMC_CMD, MmcCmd);
+
+  ErrMask = DWEMMC_INT_EBE | DWEMMC_INT_HLE | DWEMMC_INT_RTO |
+            DWEMMC_INT_RCRC | DWEMMC_INT_RE;
+  ErrMask |= DWEMMC_INT_DCRC | DWEMMC_INT_DRT | DWEMMC_INT_SBE;
+  do {
+    MicroSecondDelay(500);
+    Data = MmioRead32 (DWEMMC_RINTSTS);
+
+    if (Data & ErrMask) {
+      return EFI_DEVICE_ERROR;
+    }
+    if (Data & DWEMMC_INT_DTO) {     // Transfer Done
+      break;
+    }
+  } while (!(Data & DWEMMC_INT_CMD_DONE));
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+DwEmmcSendCommand (
+  IN EFI_MMC_HOST_PROTOCOL     *This,
+  IN MMC_CMD                    MmcCmd,
+  IN UINT32                     Argument
+  )
+{
+  UINT32       Cmd = 0;
+  EFI_STATUS   Status = EFI_SUCCESS;
+
+  switch (MMC_GET_INDX(MmcCmd)) {
+  case MMC_INDX(0):
+    Cmd = BIT_CMD_SEND_INIT;
+    break;
+  case MMC_INDX(1):
+    Cmd = BIT_CMD_RESPONSE_EXPECT;
+    break;
+  case MMC_INDX(2):
+    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_LONG_RESPONSE |
+           BIT_CMD_CHECK_RESPONSE_CRC | BIT_CMD_SEND_INIT;
+    break;
+  case MMC_INDX(3):
+    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+           BIT_CMD_SEND_INIT;
+    break;
+  case MMC_INDX(6):
+      Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
+    break;
+  case MMC_INDX(7):
+    if (Argument)
+        Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
+    else
+        Cmd = 0;
+    break;
+  case MMC_INDX(8):
+    if (Argument)
+      Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+        BIT_CMD_WAIT_PRVDATA_COMPLETE;
+    else
+      Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+        BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
+        BIT_CMD_WAIT_PRVDATA_COMPLETE;
+    break;
+  case MMC_INDX(9):
+    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+           BIT_CMD_LONG_RESPONSE;
+    break;
+  case MMC_INDX(12):
+    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+           BIT_CMD_STOP_ABORT_CMD;
+    break;
+  case MMC_INDX(13):
+    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+           BIT_CMD_WAIT_PRVDATA_COMPLETE;
+    break;
+  case MMC_INDX(16):
+    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
+    break;
+  case MMC_INDX(17):
+  case MMC_INDX(18):
+    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+           BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
+           BIT_CMD_WAIT_PRVDATA_COMPLETE;
+    break;
+  case MMC_INDX(24):
+  case MMC_INDX(25):
+    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+           BIT_CMD_DATA_EXPECTED | BIT_CMD_WRITE |
+           BIT_CMD_WAIT_PRVDATA_COMPLETE;
+    break;
+  case MMC_INDX(30):
+    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+           BIT_CMD_DATA_EXPECTED;
+    break;
+  case MMC_INDX(41):  //MMC_CMD41
+    Cmd = BIT_CMD_RESPONSE_EXPECT;
+    break;
+  case MMC_INDX(51):
+    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+            BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
+            BIT_CMD_WAIT_PRVDATA_COMPLETE;
+    break;
+  default:
+    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
+    break;
+  }
+
+  Cmd |= MMC_GET_INDX(MmcCmd) | BIT_CMD_USE_HOLD_REG | BIT_CMD_START;
+  if (IsPendingReadCommand (Cmd) || IsPendingWriteCommand (Cmd)) {
+    mDwEmmcCommand = Cmd;
+    mDwEmmcArgument = Argument;
+  } else {
+    Status = SendCommand (Cmd, Argument);
+  }
+  return Status;
+}
+
+EFI_STATUS
+DwEmmcReceiveResponse (
+  IN EFI_MMC_HOST_PROTOCOL     *This,
+  IN MMC_RESPONSE_TYPE          Type,
+  IN UINT32*                    Buffer
+  )
+{
+  if (Buffer == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (   (Type == MMC_RESPONSE_TYPE_R1)
+      || (Type == MMC_RESPONSE_TYPE_R1b)
+      || (Type == MMC_RESPONSE_TYPE_R3)
+      || (Type == MMC_RESPONSE_TYPE_R6)
+      || (Type == MMC_RESPONSE_TYPE_R7))
+  {
+    Buffer[0] = MmioRead32 (DWEMMC_RESP0);
+  } else if (Type == MMC_RESPONSE_TYPE_R2) {
+    Buffer[0] = MmioRead32 (DWEMMC_RESP0);
+    Buffer[1] = MmioRead32 (DWEMMC_RESP1);
+    Buffer[2] = MmioRead32 (DWEMMC_RESP2);
+    Buffer[3] = MmioRead32 (DWEMMC_RESP3);
+  }
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PrepareDmaData (
+  IN DWEMMC_IDMAC_DESCRIPTOR*    IdmacDesc,
+  IN UINTN                      Length,
+  IN UINT32*                    Buffer
+  )
+{
+  UINTN  Cnt, Blks, Idx, LastIdx;
+
+  Cnt = (Length + DWEMMC_DMA_BUF_SIZE - 1) / DWEMMC_DMA_BUF_SIZE;
+  Blks = (Length + DWEMMC_BLOCK_SIZE - 1) / DWEMMC_BLOCK_SIZE;
+  Length = DWEMMC_BLOCK_SIZE * Blks;
+
+  for (Idx = 0; Idx < Cnt; Idx++) {
+    (IdmacDesc + Idx)->Des0 = DWEMMC_IDMAC_DES0_OWN | DWEMMC_IDMAC_DES0_CH |
+                              DWEMMC_IDMAC_DES0_DIC;
+    (IdmacDesc + Idx)->Des1 = DWEMMC_IDMAC_DES1_BS1(DWEMMC_DMA_BUF_SIZE);
+    /* Buffer Address */
+    (IdmacDesc + Idx)->Des2 = (UINT32)((UINTN)Buffer + DWEMMC_DMA_BUF_SIZE * Idx);
+    /* Next Descriptor Address */
+    (IdmacDesc + Idx)->Des3 = (UINT32)((UINTN)IdmacDesc +
+                                       (sizeof(DWEMMC_IDMAC_DESCRIPTOR) * (Idx + 1)));
+  }
+  /* First Descriptor */
+  IdmacDesc->Des0 |= DWEMMC_IDMAC_DES0_FS;
+  /* Last Descriptor */
+  LastIdx = Cnt - 1;
+  (IdmacDesc + LastIdx)->Des0 |= DWEMMC_IDMAC_DES0_LD;
+  (IdmacDesc + LastIdx)->Des0 &= ~(DWEMMC_IDMAC_DES0_DIC | DWEMMC_IDMAC_DES0_CH);
+  (IdmacDesc + LastIdx)->Des1 = DWEMMC_IDMAC_DES1_BS1(Length -
+                                                      (LastIdx * DWEMMC_DMA_BUF_SIZE));
+  /* Set the Next field of Last Descriptor */
+  (IdmacDesc + LastIdx)->Des3 = 0;
+  MmioWrite32 (DWEMMC_DBADDR, (UINT32)((UINTN)IdmacDesc));
+
+  return EFI_SUCCESS;
+}
+
+VOID
+StartDma (
+  UINTN    Length
+  )
+{
+  UINT32 Data;
+
+  Data = MmioRead32 (DWEMMC_CTRL);
+  Data |= DWEMMC_CTRL_INT_EN | DWEMMC_CTRL_DMA_EN | DWEMMC_CTRL_IDMAC_EN;
+  MmioWrite32 (DWEMMC_CTRL, Data);
+  Data = MmioRead32 (DWEMMC_BMOD);
+  Data |= DWEMMC_IDMAC_ENABLE | DWEMMC_IDMAC_FB;
+  MmioWrite32 (DWEMMC_BMOD, Data);
+
+  MmioWrite32 (DWEMMC_BLKSIZ, DWEMMC_BLOCK_SIZE);
+  MmioWrite32 (DWEMMC_BYTCNT, Length);
+}
+
+#define FIFO_RESET        (0x1<<1)	/* Reset FIFO */
+#define FIFO_EMPTY        (0x1<<2)
+#define FIFO_RESET        (0x1<<1)	/* Reset FIFO */
+#define DWEMMC_MSHCI_FIFO           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x200)
+
+EFI_STATUS
+DwEmmcReadBlockData (
+  IN EFI_MMC_HOST_PROTOCOL     *This,
+  IN EFI_LBA                    Lba,
+  IN UINTN                      Length,
+  IN UINT32*                   Buffer
+  )
+{
+  EFI_STATUS	Status;
+  UINT32		DataLen = Length>>2; //byte to word
+  EFI_STATUS	ret = EFI_SUCCESS;
+  UINT32		Data;
+  UINT32		TimeOut = 0;
+  UINT32		value = 0;
+
+  if (mDwEmmcCommand & BIT_CMD_WAIT_PRVDATA_COMPLETE) {
+    do {
+      Data = MmioRead32 (DWEMMC_STATUS);
+    } while (Data & DWEMMC_STS_DATA_BUSY);
+  }
+
+  if ((mDwEmmcCommand & BIT_CMD_STOP_ABORT_CMD) || (mDwEmmcCommand & BIT_CMD_DATA_EXPECTED)) {
+    if (!(MmioRead32 (DWEMMC_STATUS) & FIFO_EMPTY)) {
+      Data = MmioRead32 (DWEMMC_CTRL);
+      Data |= FIFO_RESET;
+      MmioWrite32 (DWEMMC_CTRL, Data);
+
+      TimeOut = 100000;
+      while (((value = MmioRead32 (DWEMMC_CTRL)) & (FIFO_RESET)) && (TimeOut > 0)) {
+        TimeOut--;
+      }
+      if (TimeOut == 0) {
+        DEBUG ((DEBUG_ERROR, "%a():  CMD=%d SDC_SDC_ERROR\n", __func__, mDwEmmcCommand&0x3f));
+        return EFI_DEVICE_ERROR;
+      }
+    }
+  }
+
+  MmioWrite32 (DWEMMC_BLKSIZ, 512);
+  MmioWrite32 (DWEMMC_BYTCNT, Length);
+
+  Status = SendCommand (mDwEmmcCommand, mDwEmmcArgument);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Failed to read data, mDwEmmcCommand:%x, mDwEmmcArgument:%x, Status:%r\n", mDwEmmcCommand, mDwEmmcArgument, Status));
+    return EFI_DEVICE_ERROR;
+  }
+
+  TimeOut = 1000000;
+  while (DataLen) {
+    if (MmioRead32(DWEMMC_RINTSTS) & (DWEMMC_INT_DRT | DWEMMC_INT_SBE | DWEMMC_INT_EBE | DWEMMC_INT_DCRC))  {
+      DEBUG ((DEBUG_ERROR, "%a(): EFI_DEVICE_ERROR DWEMMC_RINTSTS=0x%x DataLen=%d\n",
+        __func__, MmioRead32(DWEMMC_RINTSTS), DataLen));
+      return EFI_DEVICE_ERROR;
+    }
+
+    while((!(MmioRead32(DWEMMC_STATUS) & FIFO_EMPTY)) && DataLen) {
+      *Buffer++ = MmioRead32(DWEMMC_MSHCI_FIFO);
+      DataLen--;
+      TimeOut = 1000000;
+    }
+
+    if (!DataLen) {
+      ret = (MmioRead32(DWEMMC_RINTSTS) & (DWEMMC_INT_DRT | DWEMMC_INT_SBE | DWEMMC_INT_EBE | DWEMMC_INT_DCRC))? 
+        EFI_DEVICE_ERROR : EFI_SUCCESS;
+      DEBUG((DW_DBG, "%a(): DataLen end :%d\n", __func__, ret));
+      break;
+    }
+
+    NanoSecondDelay(1);
+    TimeOut--;
+    if (TimeOut == 0) {
+      ret = EFI_DEVICE_ERROR;
+      DEBUG ((DEBUG_ERROR, "%a(): TimeOut! DataLen=%d\n", __func__, DataLen));
+      break;
+    }
+  }
+
+  return ret;
+}
+
+#define MMC_GET_FCNT(x)		        (((x)>>17) & 0x1FF)
+#define INTMSK_HTO      (0x1<<10)
+
+/* Common flag combinations */
+#define MMC_DATA_ERROR_FLAGS (DWEMMC_INT_DRT | DWEMMC_INT_DCRC | DWEMMC_INT_FRUN | \
+	DWEMMC_INT_HLE | INTMSK_HTO | DWEMMC_INT_SBE  | \
+	DWEMMC_INT_EBE)
+
+EFI_STATUS
+DwEmmcWriteBlockData (
+  IN EFI_MMC_HOST_PROTOCOL     *This,
+  IN EFI_LBA                    Lba,
+  IN UINTN                      Length,
+  IN UINT32*                    Buffer
+  )
+{
+  UINT32 *DataBuffer = Buffer;
+  UINTN Count=0;
+  UINTN Size32 = Length / 4;
+  UINT32 Mask;
+  EFI_STATUS	Status;
+  UINT32		Data;
+  UINT32		TimeOut = 0;
+  UINT32		value = 0;
+
+  if (mDwEmmcCommand & BIT_CMD_WAIT_PRVDATA_COMPLETE) {
+    do {
+      Data = MmioRead32 (DWEMMC_STATUS);
+    } while (Data & DWEMMC_STS_DATA_BUSY);
+  }
+
+  if (!(((mDwEmmcCommand&0x3f) == 6) || ((mDwEmmcCommand&0x3f) == 51))) {
+    if ((mDwEmmcCommand & BIT_CMD_STOP_ABORT_CMD) || (mDwEmmcCommand & BIT_CMD_DATA_EXPECTED)) {
+      if (!(MmioRead32 (DWEMMC_STATUS) & FIFO_EMPTY)) {
+        Data = MmioRead32 (DWEMMC_CTRL);
+        Data |= FIFO_RESET;
+        MmioWrite32 (DWEMMC_CTRL, Data);
+
+        TimeOut = 100000;
+        while (((value = MmioRead32 (DWEMMC_CTRL)) & (FIFO_RESET)) && (TimeOut > 0)) {
+          TimeOut--;
+        }
+        if (TimeOut == 0) {
+          DEBUG ((DEBUG_ERROR, "%a():  CMD=%d SDC_SDC_ERROR\n", __func__, mDwEmmcCommand&0x3f));
+          return EFI_DEVICE_ERROR;
+        }
+      }
+    }
+  }
+
+  MmioWrite32 (DWEMMC_BLKSIZ, 512);
+  MmioWrite32 (DWEMMC_BYTCNT, Length);
+
+  Status = SendCommand (mDwEmmcCommand, mDwEmmcArgument);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Failed to write data, mDwEmmcCommand:%x, mDwEmmcArgument:%x, Status:%r\n", mDwEmmcCommand, mDwEmmcArgument, Status));
+    return EFI_DEVICE_ERROR;
+  }
+
+  for (Count = 0; Count < Size32; Count++) {
+    while(MMC_GET_FCNT(MmioRead32(DWEMMC_STATUS)) >32)
+    MicroSecondDelay(1);
+    MmioWrite32((DWEMMC_MSHCI_FIFO), *DataBuffer++);
+  }
+
+  do {
+    Mask = MmioRead32(DWEMMC_RINTSTS);
+    if (Mask & (MMC_DATA_ERROR_FLAGS)) {
+      DEBUG((DEBUG_ERROR, "SdmmcWriteData error, RINTSTS = 0x%08x\n", Mask));
+      return EFI_DEVICE_ERROR;
+    }	
+  } while (!(Mask & DWEMMC_INT_DTO));
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+DwEmmcSetIos (
+  IN EFI_MMC_HOST_PROTOCOL      *This,
+  IN  UINT32                    BusClockFreq,
+  IN  UINT32                    BusWidth,
+  IN  UINT32                    TimingMode
+  )
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+  UINT32    Data;
+
+  if ((PcdGet32 (PcdDwEmmcDxeMaxClockFreqInHz) != 0) &&
+      (BusClockFreq > PcdGet32 (PcdDwEmmcDxeMaxClockFreqInHz))) {
+    return EFI_UNSUPPORTED;
+  }
+  if (TimingMode != EMMCBACKWARD) {
+    Data = MmioRead32 (DWEMMC_UHSREG);
+    switch (TimingMode) {
+    case EMMCHS52DDR1V2:
+    case EMMCHS52DDR1V8:
+      Data |= 1 << 16;
+      break;
+    case EMMCHS52:
+    case EMMCHS26:
+      Data &= ~(1 << 16);
+      break;
+    default:
+      return EFI_UNSUPPORTED;
+    }
+    MmioWrite32 (DWEMMC_UHSREG, Data);
+  }
+
+  switch (BusWidth) {
+  case 1:
+    MmioWrite32 (DWEMMC_CTYPE, 0);
+    break;
+  case 4:
+    MmioWrite32 (DWEMMC_CTYPE, 1);
+    break;
+  case 8:
+    MmioWrite32 (DWEMMC_CTYPE, 1 << 16);
+    break;
+  default:
+    return EFI_UNSUPPORTED;
+  }
+  if (BusClockFreq) {
+    Status = DwEmmcSetClock (BusClockFreq);
+  }
+  return Status;
+}
+
+BOOLEAN
+DwEmmcIsMultiBlock (
+  IN EFI_MMC_HOST_PROTOCOL      *This
+  )
+{
+  return TRUE;
+}
+
+EFI_MMC_HOST_PROTOCOL gMciHost = {
+  MMC_HOST_PROTOCOL_REVISION,
+  DwEmmcIsCardPresent,
+  DwEmmcIsReadOnly,
+  DwEmmcBuildDevicePath,
+  DwEmmcNotifyState,
+  DwEmmcSendCommand,
+  DwEmmcReceiveResponse,
+  DwEmmcReadBlockData,
+  DwEmmcWriteBlockData,
+  DwEmmcSetIos,
+  DwEmmcIsMultiBlock
+};
+
+EFI_STATUS
+DwEmmcDxeInitialize (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  EFI_STATUS    Status;
+  EFI_HANDLE    Handle;
+
+  if (!FixedPcdGetBool (PcdDwPermitObsoleteDrivers)) {
+    ASSERT (FALSE);
+    return EFI_UNSUPPORTED;
+  }
+
+  Handle = NULL;
+  DwEmmcDxeIoMux ();
+  gpIdmacDesc = (DWEMMC_IDMAC_DESCRIPTOR *)AllocatePages (DWEMMC_MAX_DESC_PAGES);
+  if (gpIdmacDesc == NULL) {
+    return EFI_BUFFER_TOO_SMALL;
+  }
+
+  DEBUG ((DEBUG_BLKIO, "DwEmmcDxeInitialize()\n"));
+
+  //Publish Component Name, BlockIO protocol interfaces
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &Handle,
+                  &gEmbeddedMmcHostProtocolGuid,    &gMciHost,
+                  NULL
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  return EFI_SUCCESS;
+}

edk2-platforms/Silicon/Rockchip/RK3588/Drivers/DwEmmcDxe/DwEmmcDxe.dec

@@ -0,0 +1,48 @@
+#/** @file
+# Framework Module Development Environment Industry Standards
+#
+# This Package provides headers and libraries that conform to EFI/PI Industry standards.
+# Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2012-2014, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2015-2017, Linaro. All rights reserved.<BR>
+# Copyright (c) 2017, Rockchip Inc. All rights reserved.<BR>
+#
+#    This program and the accompanying materials are licensed and made available under
+#    the terms and conditions of the BSD License which accompanies this distribution.
+#    The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  DEC_SPECIFICATION              = 1.27
+  PACKAGE_NAME                   = DesignWarePkg
+  PACKAGE_GUID                   = 91eba445-28f3-47ce-9570-87bc701f336c
+  PACKAGE_VERSION                = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+#                   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+
+[Guids.common]
+  gDesignWareTokenSpaceGuid       = { 0x6fdd76a9, 0xf220, 0x4f1d,  { 0x9c, 0xcf, 0xbc, 0x2d, 0x68, 0x29, 0xab, 0x9c }}
+
+[PcdsFixedAtBuild.common]
+  #
+  # Permit the use of obsolete drivers in this package
+  #
+  gDesignWareTokenSpaceGuid.PcdDwPermitObsoleteDrivers|FALSE|BOOLEAN|0x00000001
+
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeBaseAddress|0x0|UINT32|0x00000002
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz|0x0|UINT32|0x00000003
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeMaxClockFreqInHz|0x0|UINT32|0x00000004
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeFifoDepth|0x0|UINT32|0x00000005

edk2-platforms/Silicon/Rockchip/RK3588/Drivers/DwEmmcDxe/DwEmmcDxe.dsc

@@ -0,0 +1,44 @@
+## @file
+#
+#  Copyright (c) 2011 - 2019, Intel Corporaton. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  PLATFORM_NAME                  = Synopsys
+  PLATFORM_GUID                  = 09b27b59-7195-4220-b81c-c1871c74d006
+  PLATFORM_VERSION               = 0.1
+  OUTPUT_DIRECTORY               = Build/Synopsys
+  SUPPORTED_ARCHITECTURES        = AARCH64|ARM
+  BUILD_TARGETS                  = DEBUG|RELEASE|NOOPT
+  SKUID_IDENTIFIER               = DEFAULT
+
+!include MdePkg/MdeLibs.dsc.inc
+
+[LibraryClasses]
+  ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+  CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+  DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
+  DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  NetLib|NetworkPkg/Library/DxeNetLib/DxeNetLib.inf
+  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+  NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+  TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+
+[Components]
+  Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf

edk2-platforms/Silicon/Rockchip/RK3588/Drivers/DwEmmcDxe/DwEmmcDxe.inf

@@ -0,0 +1,61 @@
+#/** @file
+#  INF file for the eMMC Host Protocol implementation for the DesignWare MMC.
+#
+#  WARNING:
+#  This driver fails to follow the UEFI driver model without a good
+#  reason, and only remains in the tree because it is still used by
+#  a small number of platforms. It will be removed when no longer used.
+#
+#  Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = DwEmmcDxe
+  FILE_GUID                      = 8500ef02-317d-11ec-95b4-f42a7dcb925d
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = DwEmmcDxeInitialize
+
+[Sources.common]
+  DwEmmcDxe.c
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Rockchip/Drivers/DwEmmcDxe/DwEmmcDxe.dec
+  Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  BaseLib
+  BaseMemoryLib
+  CacheMaintenanceLib
+  IoLib
+  MemoryAllocationLib
+  TimerLib
+  UefiDriverEntryPoint
+  UefiLib
+  RockchipPlatformLib
+  CruLib
+
+[Protocols]
+  gEfiCpuArchProtocolGuid
+  gEfiDevicePathProtocolGuid
+  gEmbeddedMmcHostProtocolGuid
+
+[Pcd]
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeBaseAddress
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeMaxClockFreqInHz
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeFifoDepth
+  gDesignWareTokenSpaceGuid.PcdDwPermitObsoleteDrivers
+
+[Depex]
+  TRUE

edk2-platforms/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.c

@@ -48,7 +48,7 @@
 
 STATIC
 EFI_STATUS
-BoardInitSetCpuSpeed (
+SetMaxCpuSpeed (
   VOID
   )
 {
@@ -65,6 +65,7 @@ BoardInitSetCpuSpeed (
   SCMI_CLOCK_RATE        *ClockRate;
   SCMI_CLOCK_RATE_FORMAT ClockRateFormat;
   UINT32                 ClockIds[3]= {SCMI_CLK_CPUL, SCMI_CLK_CPUB01, SCMI_CLK_CPUB23};
+  UINT32                 ClockIndex;
 
   Status = gBS->LocateProtocol (
                   &ClockProtocolGuid,
@@ -84,11 +85,9 @@ BoardInitSetCpuSpeed (
   DEBUG ((DEBUG_ERROR, "SCMI clock management protocol version = %x\n",
     ClockProtocolVersion));
 
-  ClockId = 0;
-
-  for (int i=0 ; i<3; i=i+1 )
+  for (ClockIndex = 0; ClockIndex < ARRAY_SIZE(ClockIds); ClockIndex++)
   {
-    ClockId = ClockIds[i];
+    ClockId = ClockIds[ClockIndex];
     Status = ClockProtocol->GetClockAttributes (
                               ClockProtocol,
                               ClockId,
@@ -154,6 +153,10 @@ BoardInitSetCpuSpeed (
     CpuRate = ClockRate[TotalRates - 1].DiscreteRate.Rate;
     FreePool (ClockRate);
 
+    // The maximum discrete rates returned are 63 Hz higher than supported,
+    // causing SCMI to ignore the setting.
+    CpuRate -= CpuRate % 100;
+
     DEBUG ((EFI_D_WARN, "SCMI: %a: New rate is %uHz\n", ClockName, CpuRate));
 
     Status = ClockProtocol->RateSet (
@@ -236,56 +239,6 @@ GmacIomuxInit (
   GmacIomux(0);
 }
 
-static struct regulator_init_data rk806_master[] = {
-	RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
-	RK8XX_VOLTAGE_INIT(MASTER_BUCK2, 750000),
-	RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
-	RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
-	RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 750000),
-	RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
-	RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
-	RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 750000),
-	RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1100000),
-
-	RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
-	RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 900000),
-	RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
-	RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 750000),
-	RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 850000),
-
-	RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
-	RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
-	RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1800000),
-	RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
-	RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 1800000),
-	RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
-};
-
-static struct regulator_init_data rk806_slaver[] = {
-	RK8XX_VOLTAGE_INIT(SLAVER_BUCK1, 750000),
-	RK8XX_VOLTAGE_INIT(SLAVER_BUCK2, 750000),
-	RK8XX_VOLTAGE_INIT(SLAVER_BUCK3, 750000),
-	RK8XX_VOLTAGE_INIT(SLAVER_BUCK4, 3300000),
-	RK8XX_VOLTAGE_INIT(SLAVER_BUCK5, 750000),
-	RK8XX_VOLTAGE_INIT(SLAVER_BUCK6, 750000),
-	RK8XX_VOLTAGE_INIT(SLAVER_BUCK7, 1800000),
-	RK8XX_VOLTAGE_INIT(SLAVER_BUCK8, 750000),
-	RK8XX_VOLTAGE_INIT(SLAVER_BUCK10, 850000),
-
-	RK8XX_VOLTAGE_INIT(SLAVER_NLDO1, 750000),
-	RK8XX_VOLTAGE_INIT(SLAVER_NLDO2, 850000),
-	RK8XX_VOLTAGE_INIT(SLAVER_NLDO3, 850000),
-	RK8XX_VOLTAGE_INIT(SLAVER_NLDO4, 1200000),
-	RK8XX_VOLTAGE_INIT(SLAVER_NLDO5, 1200000),
-
-	RK8XX_VOLTAGE_INIT(SLAVER_PLDO1, 1800000),
-	RK8XX_VOLTAGE_INIT(SLAVER_PLDO2, 1800000),
-	RK8XX_VOLTAGE_INIT(SLAVER_PLDO3, 1800000),
-	RK8XX_VOLTAGE_INIT(SLAVER_PLDO4, 3300000),
-	RK8XX_VOLTAGE_INIT(SLAVER_PLDO5, 2800000),
-	RK8XX_VOLTAGE_INIT(SLAVER_PLDO6, 1800000),
-};
-
 static UINTN ComPhyReg[3][2] = {
   {0xFEE00000, 0xFD5BC000},
   {0xFEE10000, 0xFD5C0000},
@@ -487,17 +440,19 @@ RK3588InitPeripherals (
   /* Set DETECT_J15_FASTBOOT (GPIO24) pin as GPIO function */
   //MmioWrite32 (IOCG_084_REG, 0);        /* configure GPIO24 as nopull */
   //MmioWrite32 (IOMG_080_REG, 0);        /* configure GPIO24 as GPIO */
-  // RK806Init();
 
-  // for (i = 0; i < ARRAY_SIZE(rk806_master); i++)
-  //   RK806RegulatorInit(rk806_master[i]);
-  // for (i = 0; i < ARRAY_SIZE(rk806_slaver); i++)
-  //   RK806RegulatorInit(rk806_slaver[i]);
+  Rk806Configure();
 
   ComboPhyInit();
 
-  // GmacIomuxInit();
-
+  GmacIomuxInit();
+  
+  /* Enable USB PHYs */
+  Usb2PhyResume (); 
+  UsbDpPhyEnable ();
+  
+  UsbPortPowerEnable ();
+  
   return EFI_SUCCESS;
 }
 
@@ -583,13 +538,15 @@ GetPlatformBootOptionsAndKeys (
   EFI_STATUS                             Status;
   UINTN                                  Size;
 
-  Size = sizeof (EFI_BOOT_MANAGER_LOAD_OPTION) * HIKEY_BOOT_OPTION_NUM;
+  *BootCount = 4;
+
+  Size = sizeof (EFI_BOOT_MANAGER_LOAD_OPTION) * *BootCount;
   *BootOptions = (EFI_BOOT_MANAGER_LOAD_OPTION *)AllocateZeroPool (Size);
   if (*BootOptions == NULL) {
     DEBUG ((DEBUG_ERROR, "Failed to allocate memory for BootOptions\n"));
     return EFI_OUT_OF_RESOURCES;
   }
-  Size = sizeof (EFI_INPUT_KEY) * HIKEY_BOOT_OPTION_NUM;
+  Size = sizeof (EFI_INPUT_KEY) * *BootCount;
   *BootKeys = (EFI_INPUT_KEY *)AllocateZeroPool (Size);
   if (*BootKeys == NULL) {
     DEBUG ((DEBUG_ERROR, "Failed to allocate memory for BootKeys\n"));
@@ -635,8 +592,6 @@ GetPlatformBootOptionsAndKeys (
   (*BootKeys)[3].ScanCode = SCAN_NULL;
   (*BootKeys)[3].UnicodeChar = 'f';
 
-  *BootCount = 4;
-
   return EFI_SUCCESS;
 Error:
   FreePool (*BootOptions);
@@ -833,11 +788,7 @@ RK3588EntryPoint (
 {
   EFI_STATUS            Status;
 
-  /* Update CPU speed */
-  // looks like the BL31 firmware in rk3588 isn't able to change frequency anymore
-  // You can get current CPU freq with it, and even set a new freq without error
-  // but it won't take effect.
-  // BoardInitSetCpuSpeed();
+  SetMaxCpuSpeed ();
   
   Status = RK3588InitPeripherals ();
   if (EFI_ERROR (Status)) {

edk2-platforms/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.h

@@ -6,8 +6,8 @@
 *
 **/
 
-#ifndef __HIKEYDXE_H__
-#define __HIKEYDXE_H__
+#ifndef __RK3588DXE_H__
+#define __RK3588DXE_H__
 
 #define DETECT_J15_FASTBOOT              24   // GPIO3_0
 
@@ -15,6 +15,4 @@
 #define ADB_REBOOT_BOOTLOADER            0x77665500
 #define ADB_REBOOT_NONE                  0x77665501
 
-#define HIKEY_BOOT_OPTION_NUM            4
-
-#endif /* __HIKEYDXE_H__ */
+#endif /* __RK3588DXE_H__ */

edk2-platforms/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf

@@ -24,7 +24,6 @@
   Platform/Rockchip/RK3588/RK3588.dec
   Silicon/Rockchip/RockchipPkg.dec
   ArmPlatformPkg/ArmPlatformPkg.dec
-  Platform/Radxa/ROCK5B/ROCK5B.dec
 
 [LibraryClasses]
   CacheMaintenanceLib

edk2-platforms/Silicon/Rockchip/RK3588/Library/GpioLib/GpioLib.inf

@@ -23,7 +23,7 @@
   ArmPkg/ArmPkg.dec
   MdePkg/MdePkg.dec
   EmbeddedPkg/EmbeddedPkg.dec
-  Platform/Radxa/ROCK5B/ROCK5B.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
 
 [LibraryClasses]
   BaseLib

edk2-platforms/Silicon/Rockchip/RK3588/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf

@@ -23,9 +23,7 @@
   EmbeddedPkg/EmbeddedPkg.dec
   ArmPkg/ArmPkg.dec
   ArmPlatformPkg/ArmPlatformPkg.dec
-  Platform/Rockchip/RK3588/RK3588.dec
   Silicon/Rockchip/RK3588/RK3588.dec
-  Platform/Radxa/ROCK5B/ROCK5B.dec
 
 [LibraryClasses]
   DebugLib

edk2-platforms/Silicon/Rockchip/RK3588/Library/OtpLib/OtpLib.c

@@ -0,0 +1,98 @@
+/** @file
+ *
+ *  RK3588 OTP Library.
+ * 
+ *  Copyright (c) 2022, Jared McNeill <jmcneill@invisible.ca>
+ *  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
+#include <Library/OtpLib.h>
+
+#define OTP_BASE                      0xfecc0000
+
+#define RK3588_OTPC_AUTO_CTRL         (OTP_BASE + 0x0004)
+#define  RK3588_ADDR_SHIFT            16
+#define  RK3588_BURST_SHIFT           8
+#define RK3588_OTPC_AUTO_EN           (OTP_BASE + 0x0008)
+#define  RK3588_AUTO_EN               BIT0
+#define RK3588_OTPC_DOUT0             (OTP_BASE + 0x0020)
+#define RK3588_OTPC_INT_ST            (OTP_BASE + 0x0084)
+#define  RK3588_RD_DONE               BIT1
+
+#define RK3588_BLOCK_SIZE             4
+#define RK3588_NO_SECURE_OFFSET       0x300
+
+VOID
+OtpRead (
+  IN UINT16 Offset,
+  IN UINT16 Length,
+  OUT UINT8 *Data
+  )
+{
+  UINT32 Addr;
+  UINT16 AddrOffset;
+  UINT16 BytesRemaining;
+  UINT32 Value;
+  UINTN Retry;
+
+  Addr = (Offset / RK3588_BLOCK_SIZE) + RK3588_NO_SECURE_OFFSET;
+  AddrOffset = Offset % RK3588_BLOCK_SIZE;
+  BytesRemaining = Length;
+  Retry = 100000;
+
+  while (BytesRemaining > 0) {
+    MmioWrite32 (RK3588_OTPC_AUTO_CTRL, Addr << RK3588_ADDR_SHIFT | 1 << RK3588_BURST_SHIFT);
+    MmioWrite32 (RK3588_OTPC_AUTO_EN, RK3588_AUTO_EN);
+    while ((MmioRead32 (RK3588_OTPC_INT_ST) & RK3588_RD_DONE) == 0) {
+      MicroSecondDelay (1);
+      if (--Retry == 0) {
+        DEBUG ((DEBUG_WARN, "OTP read timeout!\n"));
+        break;
+      }
+    }
+    MmioWrite32 (RK3588_OTPC_INT_ST, RK3588_RD_DONE);
+
+    Value = MmioRead32 (RK3588_OTPC_DOUT0);
+
+    while (AddrOffset < RK3588_BLOCK_SIZE && BytesRemaining > 0) {
+      *Data++ = (Value >> (8 * AddrOffset)) & 0xFF;
+      AddrOffset++;
+      BytesRemaining--;
+    }
+
+    AddrOffset = 0;
+    Addr++;
+  }
+}
+
+VOID
+OtpReadCpuCode (
+  OUT UINT16 *CpuCode
+  )
+{
+  OtpRead (0x02, 0x2, (UINT8*)CpuCode);
+}
+
+VOID
+OtpReadId (
+  OUT UINT8 Id[16]
+  )
+{
+  OtpRead (0x07, 0x10, Id);
+}
+
+VOID
+OtpReadCpuVersion (
+  OUT UINT8 *Version
+  )
+{
+  OtpRead (0x1c, 0x1, Version);
+}

edk2-platforms/Silicon/Rockchip/RK3588/Library/OtpLib/OtpLib.inf

@@ -0,0 +1,35 @@
+#/** @file
+#
+#  RK3588 OTP Library.
+#
+#  Copyright (c) 2022, Jared McNeill <jmcneill@invisible.ca>
+#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = OtpLib
+  FILE_GUID                      = 412C6116-58A9-4512-B98E-0EF837D1D622
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = OtpLib
+
+[Sources]
+  OtpLib.c
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdePkg/MdePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  IoLib
+  TimerLib
+
+[Guids]

edk2-platforms/Silicon/Rockchip/RK3588/Library/PlatformLib/PlatformLib.inf

@@ -23,9 +23,7 @@
   EmbeddedPkg/EmbeddedPkg.dec
   ArmPkg/ArmPkg.dec
   ArmPlatformPkg/ArmPlatformPkg.dec
-  Platform/Rockchip/RK3588/RK3588.dec
   Silicon/Rockchip/RK3588/RK3588.dec
-  Platform/Radxa/ROCK5B/ROCK5B.dec
 
 [LibraryClasses]
   ArmLib
@@ -34,6 +32,7 @@
   MemoryAllocationLib
   PcdLib
   PrintLib
+  SdramLib
 
 [Sources.common]
   Rk3588.c
@@ -52,7 +51,6 @@
   gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
   gArmTokenSpaceGuid.PcdArmPrimaryCore
   gArmTokenSpaceGuid.PcdFdSize
-  gRK3588TokenSpaceGuid.PcdTotalMemorySize
   
 [Pcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate

edk2-platforms/Silicon/Rockchip/RK3588/Library/PlatformLib/Rk3588Mem.c

@@ -15,6 +15,7 @@
 #include <Library/MemoryAllocationLib.h>
 #include <Library/PcdLib.h>
 #include <Library/Rk3588Mem.h>
+#include <Library/SdramLib.h>
 
 UINT64 mSystemMemoryBase = FixedPcdGet64 (PcdSystemMemoryBase);
 STATIC UINT64 mSystemMemorySize = FixedPcdGet64 (PcdSystemMemorySize);
@@ -45,8 +46,8 @@ ArmPlatformGetVirtualMemoryMap (
   UINTN                         Index = 0;
   ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;
 
-  mSystemMemorySize = PcdGet64 (PcdTotalMemorySize);
-  DEBUG ((DEBUG_INFO, "RAM: 0x%ll08X (FIXED Size 0x%ll08X)\n", mSystemMemoryBase, mSystemMemorySize));
+  mSystemMemorySize = SdramGetMemorySize ();
+  DEBUG ((DEBUG_INFO, "RAM: 0x%ll08X (Size 0x%ll08X)\n", mSystemMemoryBase, mSystemMemorySize));
 
   VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages
                        (EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) *
@@ -112,6 +113,24 @@ ArmPlatformGetVirtualMemoryMap (
   VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
   VirtualMemoryInfo[Index].Type             = RK3588_MEM_RESERVED_REGION;
   VirtualMemoryInfo[Index++].Name           = L"SCMI";
+
+  if (mSystemMemoryBase + mSystemMemorySize > 0x3fc000000UL) {
+    // Bad memory range 1
+    VirtualMemoryTable[Index].PhysicalBase    = 0x3fc000000;
+    VirtualMemoryTable[Index].VirtualBase     = VirtualMemoryTable[Index].PhysicalBase;
+    VirtualMemoryTable[Index].Length          = 0x500000;
+    VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+    VirtualMemoryInfo[Index].Type             = RK3588_MEM_RESERVED_REGION;
+    VirtualMemoryInfo[Index++].Name           = L"BAD1";
+
+    // Bad memory range 2
+    VirtualMemoryTable[Index].PhysicalBase    = 0x3fff00000;
+    VirtualMemoryTable[Index].VirtualBase     = VirtualMemoryTable[Index].PhysicalBase;
+    VirtualMemoryTable[Index].Length          = 0x100000;
+    VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+    VirtualMemoryInfo[Index].Type             = RK3588_MEM_RESERVED_REGION;
+    VirtualMemoryInfo[Index++].Name           = L"BAD2";
+  }
   
   // Firmware Volume
   // VirtualMemoryTable[Index].PhysicalBase    = FixedPcdGet64 (PcdFdBaseAddress);