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Merge pull request #11 from nalzok/master
Improvements on the PmodOLED example
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@@ -1,9 +1,9 @@
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# Courtesy of https://github.com/laanwj/yosys-ice-experiments
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- Display: Digilent PmodOLED 128x32 grid SSD1306 module
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- Connected to iCEstick evaluation board
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- Display: [Digilent PmodOLED 128x32 grid SSD1306 module](https://store.digilentinc.com/pmod-oled-128-x-32-pixel-monochromatic-oled-display/)
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- Connected to iCESugar on PMOD2
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- Using 4-wire SPI 10MHz max
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- iCE40HX-1k FPGA, programmed using open source FPGA toolchain Yosys + Arachne-pnr + IceStorm
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- iCE40UP5k FPGA, programmed using open source FPGA toolchain Yosys + nextpnr + IceStorm
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- Image generated using Python script, sent from PC through FTDI serial-over-USB 1000000 baud
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```
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@@ -13,6 +13,15 @@
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1M baud (pmod conn)
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```
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Set up
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--------------
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Connect PmodOLED to PMOD2 on iCESugar, and optionally, Pmod-LED to PMOD3.
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Note: you may need to change the function `detect_serial` in `util.py` to specify the serial interface.
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PmodOLED
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------------
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@@ -31,24 +40,3 @@ Pin | Signal | Description
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5, 11 | GND |
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6, 12 | VCC | Power Supply G
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Pins on FPGA
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--------------
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Connecting PMODoled: on module: when connector is to the left, pin 1 is at the top right.
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Pin 1 is clearly indicated on the iCEstick itself.
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Pin | Signal | Pkgpin
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-----|---------|---------
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1 | PIO1_02 | 78
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2 | PIO1_03 | 79
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3 | PIO1_04 | 80
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4 | PIO1_05 | 81
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5 | GND |
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6 | VCC |
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7 | PIO1_06 | 87
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8 | PIO1_07 | 88
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9 | PIO1_08 | 90
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10 | PIO1_09 | 91
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11 | GND |
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12 | VCC |
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@@ -24,9 +24,9 @@ class OledDisplay(BaseDisplay):
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if port is None:
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ports = detect_serial()
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if len(ports) == 0:
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raise IOError('No iCEStick devices detected')
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raise IOError('No iCESugar devices detected')
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if len(ports) > 1:
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raise IOError('Multiple possible iCEStick devices detected. Need to specify which one to use')
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raise IOError('Multiple possible iCESugar devices detected. Need to specify which one to use')
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port = ports[0]
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self.conn = serial.serial_for_url(port, 1000000,
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parity=serial.PARITY_NONE, rtscts=False, xonxoff=False, timeout=1)
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@@ -4,13 +4,13 @@ set_io clk 35
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set_io resetq 18
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# LEDs (PMOD 3)
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set_io LED0 27
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set_io LED1 25
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set_io LED2 21
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set_io LED0 32
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set_io LED1 28
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set_io LED2 26
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set_io LED3 23
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set_io LED4 26
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set_io LED4 34
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# PMOD OLED module connected
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# PMOD OLED module (PMOD 2)
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set_io PMOD_CS 46
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set_io PMOD_SDIN 44
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set_io PMOD_SCLK 37
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BIN
src/basic/verilog/pmodoled2/setup.jpg
Normal file
BIN
src/basic/verilog/pmodoled2/setup.jpg
Normal file
Binary file not shown.
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After Width: | Height: | Size: 2.9 MiB |
@@ -36,7 +36,7 @@ def tile_image(ingrid):
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return data
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def detect_serial():
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'''Detect serial port for iCEStick.
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'''Detect serial port for iCESugar.
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Based on 'findserial' in swapforth.
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'''
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import glob, subprocess
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