OpenWrt/xiaomi-ax3600
1
0
Fork 0
mirror of https://github.com/immortalwrt/immortalwrt.git synced 2025-08-07 22:06:25 +08:00
Code Issues Packages Projects Releases Wiki Activity

Merge Official Source

Browse Source 
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
2025-07-31 13:21:04 +08:00
parent 24d1e86d51 fd123d6d13
commit 2242ee631d
17 changed files with 655 additions and 49 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
include/target.mk
View File

@ -405,7 +405,7 @@ define BuildTargets/DumpCurrent
echo 'Default-Packages: $(DEFAULT_PACKAGES) $(call extra_packages,$(DEFAULT_PACKAGES))'; \
$(DUMPINFO)
$(if $(CUR_SUBTARGET),$(SUBMAKE) -r --no-print-directory -C image -s DUMP=1 SUBTARGET=$(CUR_SUBTARGET))
$(if $(SUBTARGET),,@$(foreach SUBTARGET,$(SUBTARGETS),$(SUBMAKE) -s DUMP=1 SUBTARGET=$(SUBTARGET); ))
$(if $(SUBTARGET),,@$(foreach SUBTARGET,$(SUBTARGETS),$(SUBMAKE) --no-print-directory -s DUMP=1 SUBTARGET=$(SUBTARGET); ))
endef
include $(INCLUDE_DIR)/kernel.mk

4
package/libs/gettext-full/Makefile
View File

@ -163,8 +163,8 @@ define Build/InstallDev
$(INSTALL_DIR) $(1)/usr/lib/libintl-full/lib
$(CP) $(PKG_INSTALL_DIR)/usr/lib/libintl.{a,so*} $(1)/usr/lib/libintl-full/lib/
$(INSTALL_DIR) $(1)/usr/share/aclocal
$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/share/aclocal/* $(1)/usr/share/aclocal/
$(INSTALL_DIR) $(1)/usr/share/gettext/m4
$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/share/gettext/m4/* $(1)/usr/share/gettext/m4/
$(SED) '/read dummy/d' $(STAGING_DIR_HOSTPKG)/bin/gettextize
endef

24
target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-gl-b3000.dts
View File

@ -9,7 +9,7 @@
/ {
model = "GL.iNet GL-B3000";
compatible ="glinet,gl-b3000", "qcom,ipq5018";
compatible = "glinet,gl-b3000", "qcom,ipq5018";
aliases {
ethernet1 = &dp2;
@ -31,7 +31,7 @@
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
button_reset {
button-reset {
label = "reset";
gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
@ -43,23 +43,20 @@
pinctrl-0 = <&leds_pins>;
pinctrl-names = "default";
led_system_blue: led_system_blue {
led_system_blue: system-blue {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_POWER;
function = LED_FUNCTION_STATUS;
gpio = <&tlmm 24 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
led_status_white: led_status_white {
led_status_white: status-white {
color = <LED_COLOR_ID_WHITE>;
function = LED_FUNCTION_POWER;
function = LED_FUNCTION_STATUS;
gpio = <&tlmm 23 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
reserved-memory {
q6_mem_regions: q6_mem_regions@4b000000 {
no-map;
reg = <0x0 0x4b000000 0x0 0x3000000>;
@ -72,7 +69,6 @@
switch_mac_mode = <MAC_MODE_SGMII_CHANNEL0>;
qcom,port_phyinfo {
// MAC0 -> GE Phy -> QCA8337 Phy2
port@0 {
port_id = <1>;
@ -189,9 +185,9 @@
};
&blsp1_uart1 {
status = "okay";
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&crypto {
@ -256,7 +252,6 @@
&tlmm {
mdio1_pins: mdio-state {
mdc-pins {
pins = "gpio36";
function = "mdc";
@ -287,7 +282,6 @@
};
qpic_pins: qpic-state {
clock-pins {
pins = "gpio9";
function = "qspi_clk";
@ -311,9 +305,7 @@
};
serial_0_pins: uart0-state {
pins =
"gpio20", // RX
"gpio21"; // TX
pins = "gpio20", "gpio21";
function = "blsp0_uart0";
drive-strength = <8>;
bias-disable;

18
target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-512m.dtsi
View File

@ -2,22 +2,6 @@
#include "ipq6018.dtsi"
&rpm_msg_ram {
reg = <0x0 0x00060000 0x0 0x6000>;
no-map;
};
&tz {
reg = <0x0 0x4a600000 0x0 0x00400000>;
no-map;
};
&smem_region {
reg = <0x0 0x4aa00000 0x0 0x00100000>;
no-map;
};
&q6_region {
reg = <0x0 0x4ab00000 0x0 0x03700000>;
no-map;
reg = <0x0 0x4ab00000 0x0 0x3700000>;
};

14
target/linux/realtek/dts/rtl930x.dtsi
View File

@ -59,7 +59,7 @@
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x18000000 0x10000>;
ranges = <0x0 0x18000000 0x20000>;
intc: interrupt-controller@3000 {
compatible = "realtek,rtl9300-intc", "realtek,rtl-intc";
@ -71,6 +71,18 @@
interrupts = <2>, <3>, <4>, <5>, <6>, <7>;
};
snand: spi@1a400 {
compatible = "realtek,rtl9301-snand";
reg = <0x1a400 0x44>;
interrupt-parent = <&intc>;
interrupts = <19 2>;
clocks = <&lx_clk>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi0: spi@1200 {
compatible = "realtek,rtl8380-spi";
reg = <0x1200 0x100>;

14
target/linux/realtek/dts/rtl931x.dtsi
View File

@ -95,7 +95,7 @@
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x18000000 0x10000>;
ranges = <0x0 0x18000000 0x20000>;
spi0: spi@1200 {
status = "okay";
@ -107,6 +107,18 @@
#size-cells = <0>;
};
snand: spi@1a400 {
compatible = "realtek,rtl9301-snand";
reg = <0x1a400 0x44>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&lx_clk>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
watchdog0: watchdog@3260 {
compatible = "realtek,rtl9310-wdt";
reg = <0x3260 0xc>;

10
target/linux/realtek/files-6.12/drivers/net/phy/rtl83xx-phy.c
View File

@ -120,7 +120,10 @@ static u64 disable_polling(int port)
sw_w32_mask(BIT(port), 0, RTL930X_SMI_POLL_CTRL);
break;
case RTL9310_FAMILY_ID:
pr_warn("%s not implemented for RTL931X\n", __func__);
saved_state = sw_r32(RTL931X_SMI_PORT_POLLING_CTRL + 4);
saved_state <<= 32;
saved_state |= sw_r32(RTL931X_SMI_PORT_POLLING_CTRL);
sw_w32_mask(BIT(port % 32), 0, RTL931X_SMI_PORT_POLLING_CTRL + ((port >> 5) << 2));
break;
}
@ -145,7 +148,8 @@ static int resume_polling(u64 saved_state)
sw_w32(saved_state, RTL930X_SMI_POLL_CTRL);
break;
case RTL9310_FAMILY_ID:
pr_warn("%s not implemented for RTL931X\n", __func__);
sw_w32(saved_state >> 32, RTL931X_SMI_PORT_POLLING_CTRL + 4);
sw_w32(saved_state, RTL931X_SMI_PORT_POLLING_CTRL);
break;
}
@ -3048,7 +3052,7 @@ static void rtl9310_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int sta
if (l < 32) {
u32 mask = BIT(l) - 1;
data = rtl930x_read_sds_phy(sds, page, reg);
data = rtl931x_read_sds_phy(sds, page, reg);
data &= ~(mask << start_bit);
data |= (v & mask) << start_bit;
}

481
target/linux/realtek/patches-6.12/001-v6.13-spi-mem-add-realtek-nand-controller.patch Normal file
View File

@ -0,0 +1,481 @@
From 42d20a6a61b8fccbb57d80df1ccde7dd82d5bbd6 Mon Sep 17 00:00:00 2001
From: Chris Packham <chris.packham@alliedtelesis.co.nz>
Date: Wed, 16 Oct 2024 11:54:34 +1300
Subject: [PATCH] spi: spi-mem: Add Realtek SPI-NAND controller
Add a driver for the SPI-NAND controller on the RTL9300 family of
devices.
The controller supports
* Serial/Dual/Quad data with
* PIO and DMA data read/write operation
* Configurable flash access timing
There is a separate ECC controller on the RTL9300 which isn't currently
supported (instead we rely on the on-die ECC supported by most SPI-NAND
chips).
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Link: https://patch.msgid.link/20241015225434.3970360-4-chris.packham@alliedtelesis.co.nz
Signed-off-by: Mark Brown <broonie@kernel.org>
---
MAINTAINERS | 6 +
drivers/spi/Kconfig | 11 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-realtek-rtl-snand.c | 405 ++++++++++++++++++++++++++++
4 files changed, 423 insertions(+)
create mode 100644 drivers/spi/spi-realtek-rtl-snand.c
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19494,6 +19494,12 @@ S: Maintained
F: Documentation/devicetree/bindings/net/dsa/realtek.yaml
F: drivers/net/dsa/realtek/*
+REALTEK SPI-NAND
+M: Chris Packham <chris.packham@alliedtelesis.co.nz>
+S: Maintained
+F: Documentation/devicetree/bindings/spi/realtek,rtl9301-snand.yaml
+F: drivers/spi/spi-realtek-rtl-snand.c
+
REALTEK WIRELESS DRIVER (rtlwifi family)
M: Ping-Ke Shih <pkshih@realtek.com>
L: linux-wireless@vger.kernel.org
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -843,6 +843,17 @@ config SPI_PXA2XX
config SPI_PXA2XX_PCI
def_tristate SPI_PXA2XX && PCI && COMMON_CLK
+config SPI_REALTEK_SNAND
+ tristate "Realtek SPI-NAND Flash Controller"
+ depends on MACH_REALTEK_RTL || COMPILE_TEST
+ select REGMAP
+ help
+ This enables support for the SPI-NAND Flash controller on
+ Realtek SoCs.
+
+ This driver does not support generic SPI. The implementation
+ only supports the spi-mem interface.
+
config SPI_ROCKCHIP
tristate "Rockchip SPI controller driver"
depends on ARCH_ROCKCHIP || COMPILE_TEST
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -120,6 +120,7 @@ obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockc
obj-$(CONFIG_SPI_ROCKCHIP_SFC) += spi-rockchip-sfc.o
obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
obj-$(CONFIG_MACH_REALTEK_RTL) += spi-realtek-rtl.o
+obj-$(CONFIG_SPI_REALTEK_SNAND) += spi-realtek-rtl-snand.o
obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o
obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
obj-$(CONFIG_SPI_RZV2M_CSI) += spi-rzv2m-csi.o
--- /dev/null
+++ b/drivers/spi/spi-realtek-rtl-snand.c
@@ -0,0 +1,405 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <linux/completion.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
+
+#define SNAFCFR 0x00
+#define SNAFCFR_DMA_IE BIT(20)
+#define SNAFCCR 0x04
+#define SNAFWCMR 0x08
+#define SNAFRCMR 0x0c
+#define SNAFRDR 0x10
+#define SNAFWDR 0x14
+#define SNAFDTR 0x18
+#define SNAFDRSAR 0x1c
+#define SNAFDIR 0x20
+#define SNAFDIR_DMA_IP BIT(0)
+#define SNAFDLR 0x24
+#define SNAFSR 0x40
+#define SNAFSR_NFCOS BIT(3)
+#define SNAFSR_NFDRS BIT(2)
+#define SNAFSR_NFDWS BIT(1)
+
+#define CMR_LEN(len) ((len) - 1)
+#define CMR_WID(width) (((width) >> 1) << 28)
+
+struct rtl_snand {
+ struct device *dev;
+ struct regmap *regmap;
+ struct completion comp;
+};
+
+static irqreturn_t rtl_snand_irq(int irq, void *data)
+{
+ struct rtl_snand *snand = data;
+ u32 val = 0;
+
+ regmap_read(snand->regmap, SNAFSR, &val);
+ if (val & (SNAFSR_NFCOS | SNAFSR_NFDRS | SNAFSR_NFDWS))
+ return IRQ_NONE;
+
+ regmap_write(snand->regmap, SNAFDIR, SNAFDIR_DMA_IP);
+ complete(&snand->comp);
+
+ return IRQ_HANDLED;
+}
+
+static bool rtl_snand_supports_op(struct spi_mem *mem,
+ const struct spi_mem_op *op)
+{
+ if (!spi_mem_default_supports_op(mem, op))
+ return false;
+ if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1)
+ return false;
+ return true;
+}
+
+static void rtl_snand_set_cs(struct rtl_snand *snand, int cs, bool active)
+{
+ u32 val;
+
+ if (active)
+ val = ~(1 << (4 * cs));
+ else
+ val = ~0;
+
+ regmap_write(snand->regmap, SNAFCCR, val);
+}
+
+static int rtl_snand_wait_ready(struct rtl_snand *snand)
+{
+ u32 val;
+
+ return regmap_read_poll_timeout(snand->regmap, SNAFSR, val, !(val & SNAFSR_NFCOS),
+ 0, 2 * USEC_PER_MSEC);
+}
+
+static int rtl_snand_xfer_head(struct rtl_snand *snand, int cs, const struct spi_mem_op *op)
+{
+ int ret;
+ u32 val, len = 0;
+
+ rtl_snand_set_cs(snand, cs, true);
+
+ val = op->cmd.opcode << 24;
+ len = 1;
+ if (op->addr.nbytes && op->addr.buswidth == 1) {
+ val |= op->addr.val << ((3 - op->addr.nbytes) * 8);
+ len += op->addr.nbytes;
+ }
+
+ ret = rtl_snand_wait_ready(snand);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(snand->regmap, SNAFWCMR, CMR_LEN(len));
+ if (ret)
+ return ret;
+
+ ret = regmap_write(snand->regmap, SNAFWDR, val);
+ if (ret)
+ return ret;
+
+ ret = rtl_snand_wait_ready(snand);
+ if (ret)
+ return ret;
+
+ if (op->addr.buswidth > 1) {
+ val = op->addr.val << ((3 - op->addr.nbytes) * 8);
+ len = op->addr.nbytes;
+
+ ret = regmap_write(snand->regmap, SNAFWCMR,
+ CMR_WID(op->addr.buswidth) | CMR_LEN(len));
+ if (ret)
+ return ret;
+
+ ret = regmap_write(snand->regmap, SNAFWDR, val);
+ if (ret)
+ return ret;
+
+ ret = rtl_snand_wait_ready(snand);
+ if (ret)
+ return ret;
+ }
+
+ if (op->dummy.nbytes) {
+ val = 0;
+
+ ret = regmap_write(snand->regmap, SNAFWCMR,
+ CMR_WID(op->dummy.buswidth) | CMR_LEN(op->dummy.nbytes));
+ if (ret)
+ return ret;
+
+ ret = regmap_write(snand->regmap, SNAFWDR, val);
+ if (ret)
+ return ret;
+
+ ret = rtl_snand_wait_ready(snand);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static void rtl_snand_xfer_tail(struct rtl_snand *snand, int cs)
+{
+ rtl_snand_set_cs(snand, cs, false);
+}
+
+static int rtl_snand_xfer(struct rtl_snand *snand, int cs, const struct spi_mem_op *op)
+{
+ unsigned int pos, nbytes;
+ int ret;
+ u32 val, len = 0;
+
+ ret = rtl_snand_xfer_head(snand, cs, op);
+ if (ret)
+ goto out_deselect;
+
+ if (op->data.dir == SPI_MEM_DATA_IN) {
+ pos = 0;
+ len = op->data.nbytes;
+
+ while (pos < len) {
+ nbytes = len - pos;
+ if (nbytes > 4)
+ nbytes = 4;
+
+ ret = rtl_snand_wait_ready(snand);
+ if (ret)
+ goto out_deselect;
+
+ ret = regmap_write(snand->regmap, SNAFRCMR,
+ CMR_WID(op->data.buswidth) | CMR_LEN(nbytes));
+ if (ret)
+ goto out_deselect;
+
+ ret = rtl_snand_wait_ready(snand);
+ if (ret)
+ goto out_deselect;
+
+ ret = regmap_read(snand->regmap, SNAFRDR, &val);
+ if (ret)
+ goto out_deselect;
+
+ memcpy(op->data.buf.in + pos, &val, nbytes);
+
+ pos += nbytes;
+ }
+ } else if (op->data.dir == SPI_MEM_DATA_OUT) {
+ pos = 0;
+ len = op->data.nbytes;
+
+ while (pos < len) {
+ nbytes = len - pos;
+ if (nbytes > 4)
+ nbytes = 4;
+
+ memcpy(&val, op->data.buf.out + pos, nbytes);
+
+ pos += nbytes;
+
+ ret = regmap_write(snand->regmap, SNAFWCMR, CMR_LEN(nbytes));
+ if (ret)
+ goto out_deselect;
+
+ ret = regmap_write(snand->regmap, SNAFWDR, val);
+ if (ret)
+ goto out_deselect;
+
+ ret = rtl_snand_wait_ready(snand);
+ if (ret)
+ goto out_deselect;
+ }
+ }
+
+out_deselect:
+ rtl_snand_xfer_tail(snand, cs);
+
+ if (ret)
+ dev_err(snand->dev, "transfer failed %d\n", ret);
+
+ return ret;
+}
+
+static int rtl_snand_dma_xfer(struct rtl_snand *snand, int cs, const struct spi_mem_op *op)
+{
+ int ret;
+ dma_addr_t buf_dma;
+ enum dma_data_direction dir;
+ u32 trig;
+
+ ret = rtl_snand_xfer_head(snand, cs, op);
+ if (ret)
+ goto out_deselect;
+
+ if (op->data.dir == SPI_MEM_DATA_IN) {
+ dir = DMA_FROM_DEVICE;
+ trig = 0;
+ } else if (op->data.dir == SPI_MEM_DATA_OUT) {
+ dir = DMA_TO_DEVICE;
+ trig = 1;
+ } else {
+ ret = -EOPNOTSUPP;
+ goto out_deselect;
+ }
+
+ buf_dma = dma_map_single(snand->dev, op->data.buf.in, op->data.nbytes, dir);
+ ret = dma_mapping_error(snand->dev, buf_dma);
+ if (ret)
+ goto out_deselect;
+
+ ret = regmap_write(snand->regmap, SNAFDIR, SNAFDIR_DMA_IP);
+ if (ret)
+ goto out_unmap;
+
+ ret = regmap_update_bits(snand->regmap, SNAFCFR, SNAFCFR_DMA_IE, SNAFCFR_DMA_IE);
+ if (ret)
+ goto out_unmap;
+
+ reinit_completion(&snand->comp);
+
+ ret = regmap_write(snand->regmap, SNAFDRSAR, buf_dma);
+ if (ret)
+ goto out_disable_int;
+
+ ret = regmap_write(snand->regmap, SNAFDLR,
+ CMR_WID(op->data.buswidth) | (op->data.nbytes & 0xffff));
+ if (ret)
+ goto out_disable_int;
+
+ ret = regmap_write(snand->regmap, SNAFDTR, trig);
+ if (ret)
+ goto out_disable_int;
+
+ if (!wait_for_completion_timeout(&snand->comp, usecs_to_jiffies(20000)))
+ ret = -ETIMEDOUT;
+
+ if (ret)
+ goto out_disable_int;
+
+out_disable_int:
+ regmap_update_bits(snand->regmap, SNAFCFR, SNAFCFR_DMA_IE, 0);
+out_unmap:
+ dma_unmap_single(snand->dev, buf_dma, op->data.nbytes, dir);
+out_deselect:
+ rtl_snand_xfer_tail(snand, cs);
+
+ if (ret)
+ dev_err(snand->dev, "transfer failed %d\n", ret);
+
+ return ret;
+}
+
+static bool rtl_snand_dma_op(const struct spi_mem_op *op)
+{
+ switch (op->data.dir) {
+ case SPI_MEM_DATA_IN:
+ case SPI_MEM_DATA_OUT:
+ return op->data.nbytes > 32;
+ default:
+ return false;
+ }
+}
+
+static int rtl_snand_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
+{
+ struct rtl_snand *snand = spi_controller_get_devdata(mem->spi->controller);
+ int cs = spi_get_chipselect(mem->spi, 0);
+
+ dev_dbg(snand->dev, "cs %d op cmd %02x %d:%d, dummy %d:%d, addr %08llx@%d:%d, data %d:%d\n",
+ cs, op->cmd.opcode,
+ op->cmd.buswidth, op->cmd.nbytes, op->dummy.buswidth,
+ op->dummy.nbytes, op->addr.val, op->addr.buswidth,
+ op->addr.nbytes, op->data.buswidth, op->data.nbytes);
+
+ if (rtl_snand_dma_op(op))
+ return rtl_snand_dma_xfer(snand, cs, op);
+ else
+ return rtl_snand_xfer(snand, cs, op);
+}
+
+static const struct spi_controller_mem_ops rtl_snand_mem_ops = {
+ .supports_op = rtl_snand_supports_op,
+ .exec_op = rtl_snand_exec_op,
+};
+
+static const struct of_device_id rtl_snand_match[] = {
+ { .compatible = "realtek,rtl9301-snand" },
+ { .compatible = "realtek,rtl9302b-snand" },
+ { .compatible = "realtek,rtl9302c-snand" },
+ { .compatible = "realtek,rtl9303-snand" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, rtl_snand_match);
+
+static int rtl_snand_probe(struct platform_device *pdev)
+{
+ struct rtl_snand *snand;
+ struct device *dev = &pdev->dev;
+ struct spi_controller *ctrl;
+ void __iomem *base;
+ const struct regmap_config rc = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .cache_type = REGCACHE_NONE,
+ };
+ int irq, ret;
+
+ ctrl = devm_spi_alloc_host(dev, sizeof(*snand));
+ if (!ctrl)
+ return -ENOMEM;
+
+ snand = spi_controller_get_devdata(ctrl);
+ snand->dev = dev;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ snand->regmap = devm_regmap_init_mmio(dev, base, &rc);
+ if (IS_ERR(snand->regmap))
+ return PTR_ERR(snand->regmap);
+
+ init_completion(&snand->comp);
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return irq;
+
+ ret = dma_set_mask(snand->dev, DMA_BIT_MASK(32));
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to set DMA mask\n");
+
+ ret = devm_request_irq(dev, irq, rtl_snand_irq, 0, "rtl-snand", snand);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to request irq\n");
+
+ ctrl->num_chipselect = 2;
+ ctrl->mem_ops = &rtl_snand_mem_ops;
+ ctrl->bits_per_word_mask = SPI_BPW_MASK(8);
+ ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
+ device_set_node(&ctrl->dev, dev_fwnode(dev));
+
+ return devm_spi_register_controller(dev, ctrl);
+}
+
+static struct platform_driver rtl_snand_driver = {
+ .driver = {
+ .name = "realtek-rtl-snand",
+ .of_match_table = rtl_snand_match,
+ },
+ .probe = rtl_snand_probe,
+};
+module_platform_driver(rtl_snand_driver);
+
+MODULE_DESCRIPTION("Realtek SPI-NAND Flash Controller Driver");
+MODULE_LICENSE("GPL");

96
target/linux/realtek/patches-6.12/002-v6.13-spi-mem-rtl-snand-correctly-handle-dma-transfers.patch Normal file
View File

@ -0,0 +1,96 @@
From 25d284715845a465a1a3693a09cf8b6ab8bd9caf Mon Sep 17 00:00:00 2001
From: Chris Packham <chris.packham@alliedtelesis.co.nz>
Date: Thu, 31 Oct 2024 08:49:20 +1300
Subject: [PATCH] spi: spi-mem: rtl-snand: Correctly handle DMA transfers
The RTL9300 has some limitations on the maximum DMA transfers possible.
For reads this is 2080 bytes (520*4) for writes this is 520 bytes. Deal
with this by splitting transfers into appropriately sized parts.
Fixes: 42d20a6a61b8 ("spi: spi-mem: Add Realtek SPI-NAND controller")
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Link: https://patch.msgid.link/20241030194920.3202282-1-chris.packham@alliedtelesis.co.nz
Signed-off-by: Mark Brown <broonie@kernel.org>
---
drivers/spi/spi-realtek-rtl-snand.c | 46 +++++++++++++++++++----------
1 file changed, 30 insertions(+), 16 deletions(-)
--- a/drivers/spi/spi-realtek-rtl-snand.c
+++ b/drivers/spi/spi-realtek-rtl-snand.c
@@ -231,19 +231,22 @@ out_deselect:
static int rtl_snand_dma_xfer(struct rtl_snand *snand, int cs, const struct spi_mem_op *op)
{
+ unsigned int pos, nbytes;
int ret;
dma_addr_t buf_dma;
enum dma_data_direction dir;
- u32 trig;
+ u32 trig, len, maxlen;
ret = rtl_snand_xfer_head(snand, cs, op);
if (ret)
goto out_deselect;
if (op->data.dir == SPI_MEM_DATA_IN) {
+ maxlen = 2080;
dir = DMA_FROM_DEVICE;
trig = 0;
} else if (op->data.dir == SPI_MEM_DATA_OUT) {
+ maxlen = 520;
dir = DMA_TO_DEVICE;
trig = 1;
} else {
@@ -264,26 +267,37 @@ static int rtl_snand_dma_xfer(struct rtl
if (ret)
goto out_unmap;
- reinit_completion(&snand->comp);
+ pos = 0;
+ len = op->data.nbytes;
- ret = regmap_write(snand->regmap, SNAFDRSAR, buf_dma);
- if (ret)
- goto out_disable_int;
+ while (pos < len) {
+ nbytes = len - pos;
+ if (nbytes > maxlen)
+ nbytes = maxlen;
- ret = regmap_write(snand->regmap, SNAFDLR,
- CMR_WID(op->data.buswidth) | (op->data.nbytes & 0xffff));
- if (ret)
- goto out_disable_int;
+ reinit_completion(&snand->comp);
- ret = regmap_write(snand->regmap, SNAFDTR, trig);
- if (ret)
- goto out_disable_int;
+ ret = regmap_write(snand->regmap, SNAFDRSAR, buf_dma + pos);
+ if (ret)
+ goto out_disable_int;
- if (!wait_for_completion_timeout(&snand->comp, usecs_to_jiffies(20000)))
- ret = -ETIMEDOUT;
+ pos += nbytes;
- if (ret)
- goto out_disable_int;
+ ret = regmap_write(snand->regmap, SNAFDLR,
+ CMR_WID(op->data.buswidth) | nbytes);
+ if (ret)
+ goto out_disable_int;
+
+ ret = regmap_write(snand->regmap, SNAFDTR, trig);
+ if (ret)
+ goto out_disable_int;
+
+ if (!wait_for_completion_timeout(&snand->comp, usecs_to_jiffies(20000)))
+ ret = -ETIMEDOUT;
+
+ if (ret)
+ goto out_disable_int;
+ }
out_disable_int:
regmap_update_bits(snand->regmap, SNAFCFR, SNAFCFR_DMA_IE, 0);

24
target/linux/realtek/patches-6.12/308-tune-switch-4kec.patch Normal file
View File

@ -0,0 +1,24 @@
From: Markus Stockhausen <markus.stockhausen@gmx.de>
Date: Fri, 13 Jun 2025 20:25:37 +0100
Subject: [PATCH] realtek: set mtune 4kec for RTL838x targets
Generic patches will always force the gcc kernel tuning to 34kc. With RTL838x
being only 4kec this does not harm but is not right. Match the tuning properly.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
---
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -164,6 +164,11 @@ cflags-$(CONFIG_CPU_R4X00) += $(call cc-
cflags-$(CONFIG_CPU_TX49XX) += $(call cc-option,-march=r4600,-march=mips3) -Wa,--trap
cflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -mtune=34kc -Wa,--trap
+
+#ifdef CONFIG_RTL838X
+cflags-$(CONFIG_CPU_MIPS32_R2) := $(subst 34kc,4kec,$(cflags-$(CONFIG_CPU_MIPS32_R2)))
+#endif
+
cflags-$(CONFIG_CPU_MIPS32_R5) += -march=mips32r5 -Wa,--trap -modd-spreg
cflags-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,--trap -modd-spreg
cflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,--trap

1
target/linux/realtek/rtl838x/config-6.12
View File

@ -226,6 +226,7 @@ CONFIG_SFP=y
CONFIG_SPI=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
# CONFIG_SPI_REALTEK_SNAND is not set
CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
CONFIG_SRAM=y
CONFIG_SWPHY=y

2
target/linux/realtek/rtl838x/target.mk
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
ARCH:=mips
SUBTARGET:=rtl838x
CPU_TYPE:=4kec
CPU_TYPE:=24kc
BOARD:=realtek
BOARDNAME:=Realtek MIPS RTL838X

1
target/linux/realtek/rtl839x/config-6.12
View File

@ -239,6 +239,7 @@ CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SPI=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
# CONFIG_SPI_REALTEK_SNAND is not set
CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
CONFIG_SRAM=y
CONFIG_SWPHY=y

2
target/linux/realtek/rtl930x/config-6.12
View File

@ -137,6 +137,7 @@ CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_BRNIMAGE_FW=y
CONFIG_MTD_SPLIT_EVA_FW=y
@ -206,6 +207,7 @@ CONFIG_SFP=y
CONFIG_SPI=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_REALTEK_SNAND=y
CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
CONFIG_SWPHY=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y

2
target/linux/realtek/rtl931x/config-6.12
View File

@ -153,6 +153,7 @@ CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_BRNIMAGE_FW=y
CONFIG_MTD_SPLIT_EVA_FW=y
@ -227,6 +228,7 @@ CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SPI=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_REALTEK_SNAND=y
CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
CONFIG_SWPHY=y
CONFIG_SYNC_R4K=y

4
tools/bison/Makefile
View File

@ -21,13 +21,13 @@ include $(INCLUDE_DIR)/host-build.mk
HOST_CONFIGURE_ARGS += --enable-threads=posix --disable-nls
define Host/Install
$(call Host/Install/Default)
$(call Host/Compile/Default,install aclocal_DATA=) # Macro provided by gnulib
$(INSTALL_BIN) ./scripts/yacc $(STAGING_DIR_HOST)/bin/yacc
endef
define Host/Uninstall
rm -f $(STAGING_DIR_HOST)/bin/yacc
-$(call Host/Compile/Default,uninstall)
-$(call Host/Compile/Default,uninstall aclocal_DATA=) # Macro provided by gnulib
endef
$(eval $(call HostBuild))

5
tools/util-linux/patches/110-move-libpthread-to-libs.patch
View File

@ -12,8 +12,6 @@ Signed-off-by: Rosen Penev <rosenp@gmail.com>
libuuid/uuid.pc.in | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/libuuid/uuid.pc.in b/libuuid/uuid.pc.in
index 51929fe80d72..9fe908b61f12 100644
--- a/libuuid/uuid.pc.in
+++ b/libuuid/uuid.pc.in
@@ -7,5 +7,4 @@ Name: uuid
@ -23,6 +21,3 @@ index 51929fe80d72..9fe908b61f12 100644
-Libs.private: @SOCKET_LIBS@ -lpthread
-Libs: -L${libdir} -luuid
+Libs: -L${libdir} -luuid @SOCKET_LIBS@ -lpthread
--
2.50.1