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capstone/arch/ARM/ARMInstPrinter.c

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initial import
2013-11-27 12:11:31 +08:00
//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This class prints an ARM MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
enable arch code from source with CAPSTONE_HAS_* for MSVC to pick up
2014-05-14 11:26:41 +08:00
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifdef CAPSTONE_HAS_ARM
initial import
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#include <stdio.h> // DEBUG
#include <stdlib.h>
#include <string.h>
#include <inttypes.h>
#include "ARMInstPrinter.h"
#include "ARMAddressingModes.h"
#include "ARMBaseInfo.h"
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
#include "ARMDisassembler.h"
initial import
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#include "../../MCInst.h"
#include "../../SStream.h"
#include "../../MCRegisterInfo.h"
#include "../../utils.h"
rename mapping.c, mapping.h, module.c to have arch prefix. suggested by Alex Ionescu
2014-01-20 09:47:21 +08:00
#include "ARMMapping.h"
initial import
2013-11-27 12:11:31 +08:00
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
#define GET_SUBTARGETINFO_ENUM
#include "ARMGenSubtargetInfo.inc"
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
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static void printRegName(cs_struct *h, SStream *OS, unsigned RegNo);
initial import
2013-11-27 12:11:31 +08:00
// Autogenerated by tblgen.
static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printAddrModeTBB(MCInst *MI, unsigned OpNum, SStream *O);
static void printAddrModeTBH(MCInst *MI, unsigned OpNum, SStream *O);
static void printAddrMode2Operand(MCInst *MI, unsigned OpNum, SStream *O);
static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned OpNum, SStream *O);
static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printAddrMode3Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0);
static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printAM3PostIndexOp(MCInst *MI, unsigned Op, SStream *O);
static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O, bool AlwaysPrintImm0);
static void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O);
static void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O);
static void printAddrMode5Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0);
static void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O);
static void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O);
static void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O);
static void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O);
static void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O);
static void printAdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned);
static void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O);
static void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O);
static void printThumbAddrModeRROperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned Scale);
static void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned OpNum, SStream *O);
static void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned OpNum, SStream *O);
static void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned OpNum, SStream *O);
static void printThumbAddrModeSPOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0);
static void printT2AddrModeImm8Operand(MCInst *MI, unsigned OpNum, SStream *O, bool);
static void printT2AddrModeImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O, bool);
static void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, SStream *O);
static void printT2AddrModeImm8OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printT2AddrModeImm8s4OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printT2AddrModeSoRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O);
static void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O);
static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O);
static void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O);
static void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O);
static void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O);
static void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O);
static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printNEONModImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O, MCRegisterInfo *MRI);
static void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O);
static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O);
static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O);
static void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O);
static void printVectorListTwo(MCInst *MI, unsigned OpNum, SStream *O, MCRegisterInfo *MRI);
static void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, SStream *O, MCRegisterInfo *RI);
static void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O);
static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O);
static void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
static void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, SStream *O, MCRegisterInfo *RI);
static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
static void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O, MCRegisterInfo *MRI);
static void printVectorListThreeSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
static void printVectorListFourSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
static void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O);
static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O);
static void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O);
static void set_mem_access(MCInst *MI, bool status)
{
initial support for PPC
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if (MI->csh->detail != CS_OPT_ON)
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
return;
moving static doing_mem variable into cs_struct to guarantee thread-safe when handling memory operands
2013-12-31 22:40:04 +08:00
MI->csh->doing_mem = status;
if (status) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_INVALID;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0;
initial import
2013-11-27 12:11:31 +08:00
} else {
// done, create the next operand slot
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.op_count++;
initial import
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}
}
arm: some special instructions need to have numerical operand added manually in printInstruction()
2014-06-17 13:56:01 +08:00
static void op_addImm(MCInst *MI, int v)
{
arm: op_addImm() is called only when detail mode is ON
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if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = v;
MI->flat_insn->detail->arm.op_count++;
}
arm: some special instructions need to have numerical operand added manually in printInstruction()
2014-06-17 13:56:01 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
#define GET_INSTRINFO_ENUM
#include "ARMGenInstrInfo.inc"
//#define PRINT_ALIAS_INSTR
#include "ARMGenAsmWriter.inc"
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
void ARM_getRegName(cs_struct *handle, int value)
{
if (value == CS_OPT_SYNTAX_NOREGNAME)
handle->get_regname = getRegisterName2;
else
handle->get_regname = getRegisterName;
}
initial import
2013-11-27 12:11:31 +08:00
/// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
///
/// getSORegOffset returns an integer from 0-31, representing '32' as 0.
static unsigned translateShiftImm(unsigned imm)
{
// lsr #32 and asr #32 exist, but should be encoded as a 0.
//assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
if (imm == 0)
return 32;
return imm;
}
/// Prints the shift value with an immediate value.
arm: do not use markup
2014-06-10 01:39:06 +08:00
static void printRegImmShift(MCInst *MI, SStream *O, ARM_AM_ShiftOpc ShOpc, unsigned ShImm)
initial import
2013-11-27 12:11:31 +08:00
{
if (ShOpc == ARM_AM_no_shift || (ShOpc == ARM_AM_lsl && !ShImm))
return;
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
initial import
2013-11-27 12:11:31 +08:00
//assert (!(ShOpc == ARM_AM_ror && !ShImm) && "Cannot have ror #0");
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc));
arm: shift info associates with the right op in LDR instruction. bug reported by Daniel Colascione
2014-06-01 12:35:34 +08:00
if (MI->csh->detail) {
fix indentation introduced by the latest merge. also move test_arm_regression.c into suite/arm/ and add Makefile for it
2014-07-31 18:24:51 +08:00
if (MI->csh->doing_mem)
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)ShOpc;
else
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = (arm_shifter)ShOpc;
arm: shift info associates with the right op in LDR instruction. bug reported by Daniel Colascione
2014-06-01 12:35:34 +08:00
}
initial import
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if (ShOpc != ARM_AM_rrx) {
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, " ");
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
SStream_concat(O, "#%u", translateShiftImm(ShImm));
arm: shift info associates with the right op in LDR instruction. bug reported by Daniel Colascione
2014-06-01 12:35:34 +08:00
if (MI->csh->detail) {
if (MI->csh->doing_mem)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = translateShiftImm(ShImm);
arm: shift info associates with the right op in LDR instruction. bug reported by Daniel Colascione
2014-06-01 12:35:34 +08:00
else
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = translateShiftImm(ShImm);
arm: shift info associates with the right op in LDR instruction. bug reported by Daniel Colascione
2014-06-01 12:35:34 +08:00
}
initial import
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}
}
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
static void printRegName(cs_struct *h, SStream *OS, unsigned RegNo)
initial import
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{
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
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#ifndef CAPSTONE_DIET
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
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SStream_concat0(OS, h->get_regname(RegNo));
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
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#endif
initial import
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}
static name_map insn_update_flgs[] = {
{ ARM_INS_CMN, "cmn" },
{ ARM_INS_CMP, "cmp" },
{ ARM_INS_TEQ, "teq" },
{ ARM_INS_TST, "tst" },
{ ARM_INS_ADC, "adcs" },
{ ARM_INS_ADD, "adds" },
{ ARM_INS_AND, "ands" },
{ ARM_INS_ASR, "asrs" },
{ ARM_INS_BIC, "bics" },
{ ARM_INS_EOR, "eors" },
{ ARM_INS_LSL, "lsls" },
{ ARM_INS_LSR, "lsrs" },
{ ARM_INS_MLA, "mlas" },
{ ARM_INS_MOV, "movs" },
{ ARM_INS_MUL, "muls" },
{ ARM_INS_MVN, "mvns" },
{ ARM_INS_ORN, "orns" },
{ ARM_INS_ORR, "orrs" },
{ ARM_INS_ROR, "rors" },
{ ARM_INS_RRX, "rrxs" },
{ ARM_INS_RSB, "rsbs" },
{ ARM_INS_RSC, "rscs" },
{ ARM_INS_SBC, "sbcs" },
{ ARM_INS_SMLAL, "smlals" },
{ ARM_INS_SMULL, "smulls" },
{ ARM_INS_SUB, "subs" },
{ ARM_INS_UMLAL, "umlals" },
{ ARM_INS_UMULL, "umulls" },
};
x86: add immediate operand (1) for SHL/SHR/ROR/ROL/SAR/SAL in detail mode & Intel syntax
2014-05-19 16:46:31 +08:00
void ARM_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
initial import
2013-11-27 12:11:31 +08:00
{
arm64 & arm: do not update details when detail option is off. bug reported by Pancake.
2014-01-04 10:41:17 +08:00
if (((cs_struct *)ud)->detail != CS_OPT_ON)
return;
initial import
2013-11-27 12:11:31 +08:00
// check if this insn requests write-back
if (strrchr(insn_asm, '!') != NULL) {
change API cs_disasm_dyn(): break cs_insn into 2 structures, and put all details into new structure cs_detail. this break API compatibility
2013-12-24 16:49:36 +08:00
insn->detail->arm.writeback = true;
initial import
2013-11-27 12:11:31 +08:00
}
// check if this insn requests update flags
change API cs_disasm_dyn(): break cs_insn into 2 structures, and put all details into new structure cs_detail. this break API compatibility
2013-12-24 16:49:36 +08:00
if (insn->detail->arm.update_flags == false) {
initial import
2013-11-27 12:11:31 +08:00
// some insn still update flags, regardless of tabgen info
core: fix some warnings
2014-03-12 12:50:54 +08:00
unsigned int i, j;
initial import
2013-11-27 12:11:31 +08:00
for (i = 0; i < ARR_SIZE(insn_update_flgs); i++) {
change API cs_disasm_dyn(): break cs_insn into 2 structures, and put all details into new structure cs_detail. this break API compatibility
2013-12-24 16:49:36 +08:00
if (insn->id == insn_update_flgs[i].id &&
initial import
2013-11-27 12:11:31 +08:00
!strncmp(insn_asm, insn_update_flgs[i].name,
strlen(insn_update_flgs[i].name))) {
change API cs_disasm_dyn(): break cs_insn into 2 structures, and put all details into new structure cs_detail. this break API compatibility
2013-12-24 16:49:36 +08:00
insn->detail->arm.update_flags = true;
initial import
2013-11-27 12:11:31 +08:00
// we have to update regs_write array as well
change API cs_disasm_dyn(): break cs_insn into 2 structures, and put all details into new structure cs_detail. this break API compatibility
2013-12-24 16:49:36 +08:00
for (j = 0; j < ARR_SIZE(insn->detail->regs_write); j++) {
if (insn->detail->regs_write[j] == 0) {
insn->detail->regs_write[j] = ARM_REG_CPSR;
initial import
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break;
}
}
break;
}
}
}
arm: CC_AL is the default code condition for instructions without CC. bug reported by Daniel Colascione
2014-06-01 10:45:19 +08:00
// instruction should not have invalid CC
if (insn->detail->arm.cc == ARM_CC_INVALID) {
insn->detail->arm.cc = ARM_CC_AL;
}
arm: add operand details for 'mov pc, lr'. bug reported by Daniel Colascione
2014-06-01 11:03:14 +08:00
// manual fix for some special instructions
// printf(">>> id: %u, mcid: %u\n", insn->id, mci->Opcode);
switch(mci->Opcode) {
default:
break;
case ARM_MOVPCLR:
insn->detail->arm.operands[0].type = ARM_OP_REG;
insn->detail->arm.operands[0].reg = ARM_REG_PC;
insn->detail->arm.operands[1].type = ARM_OP_REG;
insn->detail->arm.operands[1].reg = ARM_REG_LR;
insn->detail->arm.op_count = 2;
break;
}
initial import
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}
void ARM_printInst(MCInst *MI, SStream *O, void *Info)
{
MCRegisterInfo *MRI = (MCRegisterInfo *)Info;
do not initialize some local vars unnecessarily. this problem was introduced when we fixed C89 issues for MSVC
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unsigned Opcode = MCInst_getOpcode(MI), tmp, i;
initial import
2013-11-27 12:11:31 +08:00
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
switch(Opcode) {
// Check for HINT instructions w/ canonical names.
case ARM_HINT:
case ARM_tHINT:
case ARM_t2HINT:
switch (MCOperand_getImm(MCInst_getOperand(MI, 0))) {
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
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case 0: SStream_concat0(O, "nop"); break;
case 1: SStream_concat0(O, "yield"); break;
case 2: SStream_concat0(O, "wfe"); break;
case 3: SStream_concat0(O, "wfi"); break;
case 4: SStream_concat0(O, "sev"); break;
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
case 5:
arm,arm64,mips,x86: rename PPC_getFeatureBits() to getFeatureBits()
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// FIXME: HasV80Ops becomes a mode
//if ((ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops)) {
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
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// SStream_concat0(O, "sevl");
arm,arm64,mips,x86: rename PPC_getFeatureBits() to getFeatureBits()
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// break;
//}
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
// Fallthrough for non-v8
arm,arm64,mips,x86: rename PPC_getFeatureBits() to getFeatureBits()
2013-12-31 18:15:12 +08:00
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "sevl");
arm,arm64,mips,x86: rename PPC_getFeatureBits() to getFeatureBits()
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break;
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
default:
// Anything else should just print normally.
printInstruction(MI, O, MRI);
return;
}
printPredicateOperand(MI, 1, O);
if (Opcode == ARM_t2HINT)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ".w"); // FIXME: expose this in register-size of insn?
initial import
2013-11-27 12:11:31 +08:00
return;
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
// Check for MOVs and print canonical forms, instead.
case ARM_MOVsr: {
// FIXME: Thumb variants?
MCOperand *Dst = MCInst_getOperand(MI, 0);
MCOperand *MO1 = MCInst_getOperand(MI, 1);
MCOperand *MO2 = MCInst_getOperand(MI, 2);
MCOperand *MO3 = MCInst_getOperand(MI, 3);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ARM_AM_getShiftOpcStr(ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3))));
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
printSBitModifierOperand(MI, 6, O);
printPredicateOperand(MI, 4, O);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "\t");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(Dst));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst);
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO1));
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO2));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO2);
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
//assert(ARM_AM_getSORegOffset(MO3.getImm()) == 0);
return;
}
case ARM_MOVsi: {
// FIXME: Thumb variants?
MCOperand *Dst = MCInst_getOperand(MI, 0);
MCOperand *MO1 = MCInst_getOperand(MI, 1);
MCOperand *MO2 = MCInst_getOperand(MI, 2);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ARM_AM_getShiftOpcStr(ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2))));
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
printSBitModifierOperand(MI, 5, O);
printPredicateOperand(MI, 3, O);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "\t");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(Dst));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst);
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO1));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
if (ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)) == ARM_AM_rrx) {
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
//printAnnotation(O, Annot);
return;
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
first changes to get a successfully compiled version of capstone on VS2012
2014-05-09 06:44:49 +08:00
tmp = translateShiftImm(getSORegOffset((unsigned int)MCOperand_getImm(MO2)));
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", tmp);
else
SStream_concat(O, "#%u", tmp);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type =
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
(arm_shifter)ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2));
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = tmp;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
return;
}
// A8.6.123 PUSH
case ARM_STMDB_UPD:
case ARM_t2STMDB_UPD:
if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP &&
MCInst_getNumOperands(MI) > 5) {
// Should only print PUSH if there are at least two registers in the list.
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "push");
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
printPredicateOperand(MI, 2, O);
if (Opcode == ARM_t2STMDB_UPD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ".w");
SStream_concat0(O, "\t");
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
printRegisterList(MI, 4, O);
return;
}
break;
initial import
2013-11-27 12:11:31 +08:00
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
case ARM_STR_PRE_IMM:
if (MCOperand_getReg(MCInst_getOperand(MI, 2)) == ARM_SP &&
MCOperand_getImm(MCInst_getOperand(MI, 3)) == -4) {
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "push");
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
printPredicateOperand(MI, 4, O);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "\t{");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 1)));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 1));
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "}");
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
return;
}
break;
initial import
2013-11-27 12:11:31 +08:00
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
// A8.6.122 POP
case ARM_LDMIA_UPD:
case ARM_t2LDMIA_UPD:
if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP &&
MCInst_getNumOperands(MI) > 5) {
// Should only print POP if there are at least two registers in the list.
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "pop");
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
printPredicateOperand(MI, 2, O);
if (Opcode == ARM_t2LDMIA_UPD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ".w");
SStream_concat0(O, "\t");
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
printRegisterList(MI, 4, O);
return;
}
break;
initial import
2013-11-27 12:11:31 +08:00
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
case ARM_LDR_POST_IMM:
if (MCOperand_getReg(MCInst_getOperand(MI, 2)) == ARM_SP &&
MCOperand_getImm(MCInst_getOperand(MI, 4)) == 4) {
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "pop");
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
printPredicateOperand(MI, 5, O);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "\t{");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 0)));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0));
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "}");
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
return;
}
break;
initial import
2013-11-27 12:11:31 +08:00
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
// A8.6.355 VPUSH
case ARM_VSTMSDB_UPD:
case ARM_VSTMDDB_UPD:
if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) {
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "vpush");
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
printPredicateOperand(MI, 2, O);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "\t");
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
printRegisterList(MI, 4, O);
return;
}
break;
initial import
2013-11-27 12:11:31 +08:00
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
// A8.6.354 VPOP
case ARM_VLDMSIA_UPD:
case ARM_VLDMDIA_UPD:
if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) {
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "vpop");
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
printPredicateOperand(MI, 2, O);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "\t");
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
printRegisterList(MI, 4, O);
return;
}
break;
initial import
2013-11-27 12:11:31 +08:00
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
case ARM_tLDMIA: {
bool Writeback = true; // FIXME: expose this
unsigned BaseReg = MCOperand_getReg(MCInst_getOperand(MI, 0));
unsigned i;
for (i = 3; i < MCInst_getNumOperands(MI); ++i) {
if (MCOperand_getReg(MCInst_getOperand(MI, i)) == BaseReg)
Writeback = false;
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "ldm");
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
printPredicateOperand(MI, 1, O);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "\t");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, BaseReg);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = BaseReg;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
if (Writeback)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "!");
SStream_concat0(O, ", ");
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
printRegisterList(MI, 3, O);
return;
}
// Combine 2 GPRs from disassember into a GPRPair to match with instr def.
// ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
// a single GPRPair reg operand is used in the .td file to replace the two
// GPRs. However, when decoding them, the two GRPs cannot be automatically
// expressed as a GPRPair, so we have to manually merge them.
// FIXME: We would really like to be able to tablegen'erate this.
case ARM_LDREXD:
case ARM_STREXD:
case ARM_LDAEXD:
case ARM_STLEXD: {
fix indentation introduced by the latest merge. also move test_arm_regression.c into suite/arm/ and add Makefile for it
2014-07-31 18:24:51 +08:00
MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI, ARM_GPRRegClassID);
bool isStore = Opcode == ARM_STREXD || Opcode == ARM_STLEXD;
more fixes on C coding style
2014-01-23 22:29:04 +08:00
fix indentation introduced by the latest merge. also move test_arm_regression.c into suite/arm/ and add Makefile for it
2014-07-31 18:24:51 +08:00
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, isStore ? 1 : 0));
if (MCRegisterClass_contains(MRC, Reg)) {
MCInst NewMI;
arm: convert MCOperand_CreateReg() to MCOperand_CreateReg0() to avoid malloc/free
2014-06-10 14:59:55 +08:00
fix indentation introduced by the latest merge. also move test_arm_regression.c into suite/arm/ and add Makefile for it
2014-07-31 18:24:51 +08:00
MCInst_Init(&NewMI);
MCInst_setOpcode(&NewMI, Opcode);
arm: convert MCOperand_CreateReg() to MCOperand_CreateReg0() to avoid malloc/free
2014-06-10 14:59:55 +08:00
fix indentation introduced by the latest merge. also move test_arm_regression.c into suite/arm/ and add Makefile for it
2014-07-31 18:24:51 +08:00
if (isStore)
MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, 0));
arm: convert MCOperand_CreateReg() to MCOperand_CreateReg0() to avoid malloc/free
2014-06-10 14:59:55 +08:00
fix indentation introduced by the latest merge. also move test_arm_regression.c into suite/arm/ and add Makefile for it
2014-07-31 18:24:51 +08:00
MCOperand_CreateReg0(&NewMI, MCRegisterInfo_getMatchingSuperReg(MRI, Reg, ARM_gsub_0,
MCRegisterInfo_getRegClass(MRI, ARM_GPRPairRegClassID)));
arm: convert MCOperand_CreateReg() to MCOperand_CreateReg0() to avoid malloc/free
2014-06-10 14:59:55 +08:00
fix indentation introduced by the latest merge. also move test_arm_regression.c into suite/arm/ and add Makefile for it
2014-07-31 18:24:51 +08:00
// Copy the rest operands into NewMI.
for(i = isStore ? 3 : 2; i < MCInst_getNumOperands(MI); ++i)
MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i));
arm: convert MCOperand_CreateReg() to MCOperand_CreateReg0() to avoid malloc/free
2014-06-10 14:59:55 +08:00
fix indentation introduced by the latest merge. also move test_arm_regression.c into suite/arm/ and add Makefile for it
2014-07-31 18:24:51 +08:00
printInstruction(&NewMI, O, MRI);
return;
arm: upgrade core engine
2013-12-01 22:19:27 +08:00
}
fix indentation introduced by the latest merge. also move test_arm_regression.c into suite/arm/ and add Makefile for it
2014-07-31 18:24:51 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
//if (printAliasInstr(MI, O, MRI))
// printInstruction(MI, O, MRI);
printInstruction(MI, O, MRI);
}
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
do not initialize some local vars unnecessarily. this problem was introduced when we fixed C89 issues for MSVC
2014-05-12 13:41:49 +08:00
int32_t imm;
initial import
2013-11-27 12:11:31 +08:00
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
unsigned Reg = MCOperand_getReg(Op);
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, Reg);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
moving static doing_mem variable into cs_struct to guarantee thread-safe when handling memory operands
2013-12-31 22:40:04 +08:00
if (MI->csh->doing_mem) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
if (MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base == ARM_REG_INVALID)
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = Reg;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
else
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = Reg;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
} else {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
} else if (MCOperand_isImm(Op)) {
arm: some simple improvements & cleanups
2014-07-31 21:16:54 +08:00
unsigned int opc = MCInst_getOpcode(MI);
* added a test file to suite for testing invalid and valid instruction sequences * fixed and added a test for a thumb-2 invalid sequence that was incorrectly allowed before these changes (pop.w with sp argument included) * fixed and added a test for a blx from thumb to ARM that had its immediate argument incorrect (misaligned) * eliminated some warnings by explicitly casting so I could turn on treat warnings as errors locally General notes: * probably worth turning on treat all warnings as errors in the msvc project files, had a subtle bug that resulted from a missing declaration causing differences in dll and static compilation modes ( code was working incorrectly in dll form because of missing declaration in arch/ARM/ARMMapping.h for new function ARM_blx_to_arm_mode. Something about the linking was confusing ld when making the dll, and the resulting offsets were wonky (e.g. the added ble test would show up as #0x1fc instead of #0x1fe like it should have ) * the invalid pop was being treated as a soft fail which then gets coerced to a success because it is != MCDisassembler_Fail in Thumb_getInstruction what are the semantics of a soft fail? Maybe we should be able to set up whether or not we want a soft fail to be a real fail in the csh struct?
2014-06-30 13:45:40 +08:00
first changes to get a successfully compiled version of capstone on VS2012
2014-05-09 06:44:49 +08:00
imm = (int32_t)MCOperand_getImm(Op);
arm: update target branch having relative offset. issue reported by Giovanni Condello
2014-05-07 14:12:50 +08:00
// relative branch only has relative offset, so we have to update it
// to reflect absolute address.
// Note: in ARM, PC is always 2 instructions ahead, so we have to
// add 8 in ARM mode, or 4 in Thumb mode
arm: fix some more Thumb relative branch instructions. bug reported by Giovanni Nanomad Condello
2014-05-09 17:31:41 +08:00
// printf(">> opcode: %u\n", MCInst_getOpcode(MI));
* added a test file to suite for testing invalid and valid instruction sequences * fixed and added a test for a thumb-2 invalid sequence that was incorrectly allowed before these changes (pop.w with sp argument included) * fixed and added a test for a blx from thumb to ARM that had its immediate argument incorrect (misaligned) * eliminated some warnings by explicitly casting so I could turn on treat warnings as errors locally General notes: * probably worth turning on treat all warnings as errors in the msvc project files, had a subtle bug that resulted from a missing declaration causing differences in dll and static compilation modes ( code was working incorrectly in dll form because of missing declaration in arch/ARM/ARMMapping.h for new function ARM_blx_to_arm_mode. Something about the linking was confusing ld when making the dll, and the resulting offsets were wonky (e.g. the added ble test would show up as #0x1fc instead of #0x1fe like it should have ) * the invalid pop was being treated as a soft fail which then gets coerced to a success because it is != MCDisassembler_Fail in Thumb_getInstruction what are the semantics of a soft fail? Maybe we should be able to set up whether or not we want a soft fail to be a real fail in the csh struct?
2014-06-30 13:45:40 +08:00
if (ARM_rel_branch(MI->csh, opc)) {
arm: update target branch having relative offset. issue reported by Giovanni Condello
2014-05-07 14:12:50 +08:00
// only do this for relative branch
* added a test file to suite for testing invalid and valid instruction sequences * fixed and added a test for a thumb-2 invalid sequence that was incorrectly allowed before these changes (pop.w with sp argument included) * fixed and added a test for a blx from thumb to ARM that had its immediate argument incorrect (misaligned) * eliminated some warnings by explicitly casting so I could turn on treat warnings as errors locally General notes: * probably worth turning on treat all warnings as errors in the msvc project files, had a subtle bug that resulted from a missing declaration causing differences in dll and static compilation modes ( code was working incorrectly in dll form because of missing declaration in arch/ARM/ARMMapping.h for new function ARM_blx_to_arm_mode. Something about the linking was confusing ld when making the dll, and the resulting offsets were wonky (e.g. the added ble test would show up as #0x1fc instead of #0x1fe like it should have ) * the invalid pop was being treated as a soft fail which then gets coerced to a success because it is != MCDisassembler_Fail in Thumb_getInstruction what are the semantics of a soft fail? Maybe we should be able to set up whether or not we want a soft fail to be a real fail in the csh struct?
2014-06-30 13:45:40 +08:00
if (MI->csh->mode & CS_MODE_THUMB) {
arm: update target branch having relative offset. issue reported by Giovanni Condello
2014-05-07 14:12:50 +08:00
imm += (int32_t)MI->address + 4;
fix indentation introduced by the latest merge. also move test_arm_regression.c into suite/arm/ and add Makefile for it
2014-07-31 18:24:51 +08:00
if (ARM_blx_to_arm_mode(MI->csh, opc)) {
arm: some simple improvements & cleanups
2014-07-31 21:16:54 +08:00
// here need to align down to the nearest 4-byte address
* added a test file to suite for testing invalid and valid instruction sequences * fixed and added a test for a thumb-2 invalid sequence that was incorrectly allowed before these changes (pop.w with sp argument included) * fixed and added a test for a blx from thumb to ARM that had its immediate argument incorrect (misaligned) * eliminated some warnings by explicitly casting so I could turn on treat warnings as errors locally General notes: * probably worth turning on treat all warnings as errors in the msvc project files, had a subtle bug that resulted from a missing declaration causing differences in dll and static compilation modes ( code was working incorrectly in dll form because of missing declaration in arch/ARM/ARMMapping.h for new function ARM_blx_to_arm_mode. Something about the linking was confusing ld when making the dll, and the resulting offsets were wonky (e.g. the added ble test would show up as #0x1fc instead of #0x1fe like it should have ) * the invalid pop was being treated as a soft fail which then gets coerced to a success because it is != MCDisassembler_Fail in Thumb_getInstruction what are the semantics of a soft fail? Maybe we should be able to set up whether or not we want a soft fail to be a real fail in the csh struct?
2014-06-30 13:45:40 +08:00
#define _ALIGN_DOWN(v, align_width) ((v/align_width)*align_width)
fix indentation introduced by the latest merge. also move test_arm_regression.c into suite/arm/ and add Makefile for it
2014-07-31 18:24:51 +08:00
imm = _ALIGN_DOWN(imm, 4);
* added a test file to suite for testing invalid and valid instruction sequences * fixed and added a test for a thumb-2 invalid sequence that was incorrectly allowed before these changes (pop.w with sp argument included) * fixed and added a test for a blx from thumb to ARM that had its immediate argument incorrect (misaligned) * eliminated some warnings by explicitly casting so I could turn on treat warnings as errors locally General notes: * probably worth turning on treat all warnings as errors in the msvc project files, had a subtle bug that resulted from a missing declaration causing differences in dll and static compilation modes ( code was working incorrectly in dll form because of missing declaration in arch/ARM/ARMMapping.h for new function ARM_blx_to_arm_mode. Something about the linking was confusing ld when making the dll, and the resulting offsets were wonky (e.g. the added ble test would show up as #0x1fc instead of #0x1fe like it should have ) * the invalid pop was being treated as a soft fail which then gets coerced to a success because it is != MCDisassembler_Fail in Thumb_getInstruction what are the semantics of a soft fail? Maybe we should be able to set up whether or not we want a soft fail to be a real fail in the csh struct?
2014-06-30 13:45:40 +08:00
#undef _ALIGN_DOWN
fix indentation introduced by the latest merge. also move test_arm_regression.c into suite/arm/ and add Makefile for it
2014-07-31 18:24:51 +08:00
}
} else {
arm: update target branch having relative offset. issue reported by Giovanni Condello
2014-05-07 14:12:50 +08:00
imm += (int32_t)MI->address + 8;
fix indentation introduced by the latest merge. also move test_arm_regression.c into suite/arm/ and add Makefile for it
2014-07-31 18:24:51 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
arm: update target branch having relative offset. issue reported by Giovanni Condello
2014-05-07 14:12:50 +08:00
if (imm >= 0) {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", imm);
else
SStream_concat(O, "#%u", imm);
} else {
if (imm < -HEX_THRESHOLD)
SStream_concat(O, "#-0x%x", -imm);
else
SStream_concat(O, "#-%u", -imm);
}
} else if (imm >= 0) {
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (imm > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", imm);
else
SStream_concat(O, "#%u", imm);
arm: more fix to print negative numbers in more friendly way
2014-03-26 16:21:31 +08:00
} else {
if (imm < -HEX_THRESHOLD)
SStream_concat(O, "#-0x%x", -imm);
else
SStream_concat(O, "#-%u", -imm);
}
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
moving static doing_mem variable into cs_struct to guarantee thread-safe when handling memory operands
2013-12-31 22:40:04 +08:00
if (MI->csh->doing_mem)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = imm;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
else {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
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}
}
}
static void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
do not initialize some local vars unnecessarily. this problem was introduced when we fixed C89 issues for MSVC
2014-05-12 13:41:49 +08:00
int32_t OffImm;
indentation with tab
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bool isSub;
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[pc, ");
initial import
2013-11-27 12:11:31 +08:00
first changes to get a successfully compiled version of capstone on VS2012
2014-05-09 06:44:49 +08:00
OffImm = (int32_t)MCOperand_getImm(MO1);
isSub = OffImm < 0;
initial import
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// Special value for #-0. All others are normal.
if (OffImm == INT32_MIN)
OffImm = 0;
if (isSub) {
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#-0x%x", -OffImm);
initial import
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} else {
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (OffImm > HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#0x%x", OffImm);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#%u", OffImm);
initial import
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}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "]");
arm: add missing operand info for Thumb instruction LDR involving label. bug reported by Daniel Colascione
2014-06-01 11:14:31 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_PC;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
MI->flat_insn->detail->arm.op_count++;
arm: add missing operand info for Thumb instruction LDR involving label. bug reported by Daniel Colascione
2014-06-01 11:14:31 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
// so_reg is a 4-operand unit corresponding to register forms of the A5.1
// "Addressing Mode 1 - Data-processing operands" forms. This includes:
// REG 0 0 - e.g. R5
// REG REG 0,SH_OPC - e.g. R5, ROR R3
// REG 0 IMM,SH_OPC - e.g. R5, LSL #3
static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
MCOperand *MO3 = MCInst_getOperand(MI, OpNum+2);
indentation with tab
2014-05-09 07:33:35 +08:00
ARM_AM_ShiftOpc ShOpc;
initial import
2013-11-27 12:11:31 +08:00
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO1));
initial import
2013-11-27 12:11:31 +08:00
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
initial import
2013-11-27 12:11:31 +08:00
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (MCOperand_getImm(MO3) & 7) + ARM_SFT_ASR_REG - 1;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
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// Print the shift opc.
first changes to get a successfully compiled version of capstone on VS2012
2014-05-09 06:44:49 +08:00
ShOpc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3));
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc));
initial import
2013-11-27 12:11:31 +08:00
if (ShOpc == ARM_AM_rrx)
return;
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, " ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO2));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = MCOperand_getReg(MO2);
initial import
2013-11-27 12:11:31 +08:00
//assert(ARM_AM_getSORegOffset(MO3.getImm()) == 0);
}
static void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO1));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = MCOperand_getImm(MO2) & 7;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = (unsigned int)MCOperand_getImm(MO2) >> 3;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
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// Print the shift opc.
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)),
arm: do not use markup
2014-06-10 01:39:06 +08:00
getSORegOffset((unsigned int)MCOperand_getImm(MO2)));
initial import
2013-11-27 12:11:31 +08:00
}
//===--------------------------------------------------------------------===//
// Addressing Mode #2
//===--------------------------------------------------------------------===//
static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O)
{
MCOperand *MO1 = MCInst_getOperand(MI, Op);
MCOperand *MO2 = MCInst_getOperand(MI, Op + 1);
MCOperand *MO3 = MCInst_getOperand(MI, Op + 2);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, true);
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO1));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
if (!MCOperand_getReg(MO2)) {
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
unsigned tmp = getAM2Offset((unsigned int)MCOperand_getImm(MO3));
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (tmp) { // Don't print +0.
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (tmp > HEX_THRESHOLD)
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(getAM2Op((unsigned int)MCOperand_getImm(MO3))), tmp);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
else
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(getAM2Op((unsigned int)MCOperand_getImm(MO3))), tmp);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)getAM2Op((unsigned int)MCOperand_getImm(MO3));
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = tmp;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "]");
initial import
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set_mem_access(MI, false);
return;
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
SStream_concat0(O, ARM_AM_getAddrOpcStr(getAM2Op((unsigned int)MCOperand_getImm(MO3))));
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO2));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
printRegImmShift(MI, O, getAM2ShiftOpc((unsigned int)MCOperand_getImm(MO3)),
arm: do not use markup
2014-06-10 01:39:06 +08:00
getAM2Offset((unsigned int)MCOperand_getImm(MO3)));
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "]");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, false);
}
static void printAddrModeTBB(MCInst *MI, unsigned Op, SStream *O)
{
MCOperand *MO1 = MCInst_getOperand(MI, Op);
MCOperand *MO2 = MCInst_getOperand(MI, Op+1);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, true);
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO1));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO2));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "]");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, false);
}
static void printAddrModeTBH(MCInst *MI, unsigned Op, SStream *O)
{
MCOperand *MO1 = MCInst_getOperand(MI, Op);
MCOperand *MO2 = MCInst_getOperand(MI, Op+1);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, true);
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO1));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO2));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", lsl #1]");
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = ARM_SFT_LSL;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = 1;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, false);
}
static void printAddrMode2Operand(MCInst *MI, unsigned Op, SStream *O)
{
MCOperand *MO1 = MCInst_getOperand(MI, Op);
if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right.
printOperand(MI, Op, O);
return;
}
printAM2PreOrOffsetIndexOp(MI, Op, O);
}
static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
if (!MCOperand_getReg(MO1)) {
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
unsigned ImmOffs = getAM2Offset((unsigned int)MCOperand_getImm(MO2));
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (ImmOffs > HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#%s0x%x",
ARM_AM_getAddrOpcStr(getAM2Op((unsigned int)MCOperand_getImm(MO2))), ImmOffs);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#%s%u",
ARM_AM_getAddrOpcStr(getAM2Op((unsigned int)MCOperand_getImm(MO2))), ImmOffs);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
return;
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ARM_AM_getAddrOpcStr(getAM2Op((unsigned int)MCOperand_getImm(MO2))));
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO1));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
printRegImmShift(MI, O, getAM2ShiftOpc((unsigned int)MCOperand_getImm(MO2)),
arm: do not use markup
2014-06-10 01:39:06 +08:00
getAM2Offset((unsigned int)MCOperand_getImm(MO2)));
initial import
2013-11-27 12:11:31 +08:00
}
//===--------------------------------------------------------------------===//
// Addressing Mode #3
//===--------------------------------------------------------------------===//
static void printAM3PostIndexOp(MCInst *MI, unsigned Op, SStream *O)
{
MCOperand *MO1 = MCInst_getOperand(MI, Op);
MCOperand *MO2 = MCInst_getOperand(MI, Op+1);
MCOperand *MO3 = MCInst_getOperand(MI, Op+2);
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
ARM_AM_AddrOpc op = getAM3Op((unsigned int)MCOperand_getImm(MO3));
do not initialize some local vars unnecessarily. this problem was introduced when we fixed C89 issues for MSVC
2014-05-12 13:41:49 +08:00
unsigned ImmOffs;
initial import
2013-11-27 12:11:31 +08:00
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, true);
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO1));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "], ");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, false);
if (MCOperand_getReg(MO2)) {
arm: fix a wrong calculation on sign of .disp value in mem reference
2013-12-08 22:20:35 +08:00
SStream_concat(O, "%c", (char)op);
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO2));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO2);
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
return;
}
first changes to get a successfully compiled version of capstone on VS2012
2014-05-09 06:44:49 +08:00
ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO3));
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (ImmOffs > HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(op), ImmOffs);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(op), ImmOffs);
arm: fix a wrong calculation on sign of .disp value in mem reference
2013-12-08 22:20:35 +08:00
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
arm: fix a wrong calculation on sign of .disp value in mem reference
2013-12-08 22:20:35 +08:00
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
if (op)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
else
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = -(int)ImmOffs;
arm: fix a wrong calculation on sign of .disp value in mem reference
2013-12-08 22:20:35 +08:00
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O,
bool AlwaysPrintImm0)
{
MCOperand *MO1 = MCInst_getOperand(MI, Op);
MCOperand *MO2 = MCInst_getOperand(MI, Op+1);
MCOperand *MO3 = MCInst_getOperand(MI, Op+2);
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
ARM_AM_AddrOpc op = getAM3Op((unsigned int)MCOperand_getImm(MO3));
do not initialize some local vars unnecessarily. this problem was introduced when we fixed C89 issues for MSVC
2014-05-12 13:41:49 +08:00
unsigned ImmOffs;
initial import
2013-11-27 12:11:31 +08:00
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, true);
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO1));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
initial import
2013-11-27 12:11:31 +08:00
if (MCOperand_getReg(MO2)) {
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
SStream_concat0(O, ARM_AM_getAddrOpcStr(op));
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO2));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
if (op)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = -1;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "]");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, false);
return;
}
//If the op is sub we have to print the immediate even if it is 0
first changes to get a successfully compiled version of capstone on VS2012
2014-05-09 06:44:49 +08:00
ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO3));
initial import
2013-11-27 12:11:31 +08:00
if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM_sub)) {
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (ImmOffs > HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, ", #%s0x%x", ARM_AM_getAddrOpcStr(op), ImmOffs);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, ", #%s%u", ARM_AM_getAddrOpcStr(op), ImmOffs);
initial import
2013-11-27 12:11:31 +08:00
}
arm: fix a wrong calculation on sign of .disp value in mem reference
2013-12-08 22:20:35 +08:00
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
if (op)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = (int)MCOperand_getImm(MO3);
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
else
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = (int)-MCOperand_getImm(MO3);
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: fix a wrong calculation on sign of .disp value in mem reference
2013-12-08 22:20:35 +08:00
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "]");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, false);
}
static void printAddrMode3Operand(MCInst *MI, unsigned Op, SStream *O,
bool AlwaysPrintImm0)
{
do not initialize some local vars unnecessarily. this problem was introduced when we fixed C89 issues for MSVC
2014-05-12 13:41:49 +08:00
unsigned IdxMode;
MCOperand *MO3;
initial import
2013-11-27 12:11:31 +08:00
MCOperand *MO1 = MCInst_getOperand(MI, Op);
if (!MCOperand_isReg(MO1)) { // For label symbolic references.
printOperand(MI, Op, O);
return;
}
first changes to get a successfully compiled version of capstone on VS2012
2014-05-09 06:44:49 +08:00
MO3 = MCInst_getOperand(MI, Op+2);
IdxMode = getAM3IdxMode((unsigned int)MCOperand_getImm(MO3));
initial import
2013-11-27 12:11:31 +08:00
if (IdxMode == ARMII_IndexModePost) {
printAM3PostIndexOp(MI, Op, O);
return;
}
arm: fix a wrong calculation on sign of .disp value in mem reference
2013-12-08 22:20:35 +08:00
initial import
2013-11-27 12:11:31 +08:00
printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
}
static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
ARM_AM_AddrOpc op = getAM3Op((unsigned int)MCOperand_getImm(MO2));
do not initialize some local vars unnecessarily. this problem was introduced when we fixed C89 issues for MSVC
2014-05-12 13:41:49 +08:00
unsigned ImmOffs;
initial import
2013-11-27 12:11:31 +08:00
if (MCOperand_getReg(MO1)) {
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ARM_AM_getAddrOpcStr(op));
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO1));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
arm: correct operand setup for REG type in printAddrMode3OffsetOperand()
2014-06-17 13:28:33 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
return;
}
first changes to get a successfully compiled version of capstone on VS2012
2014-05-09 06:44:49 +08:00
ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO2));
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (ImmOffs > HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(op), ImmOffs);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(op), ImmOffs);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
arm: fix a wrong calculation on sign of .disp value in mem reference
2013-12-08 22:20:35 +08:00
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
if (op)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
else
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = -(int)ImmOffs;
arm: fix a wrong calculation on sign of .disp value in mem reference
2013-12-08 22:20:35 +08:00
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
static void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
unsigned Imm = (unsigned int)MCOperand_getImm(MO);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if ((Imm & 0xff) > HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), (Imm & 0xff));
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), (Imm & 0xff));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm & 0xff;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
static void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, (MCOperand_getImm(MO2) ? "" : "-"));
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO1));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
static void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
unsigned Imm = (unsigned int)MCOperand_getImm(MO);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (((Imm & 0xff) << 2) > HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2));
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2));
initial import
2013-11-27 12:11:31 +08:00
}
static void printAddrMode5Operand(MCInst *MI, unsigned OpNum, SStream *O,
bool AlwaysPrintImm0)
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
do not initialize some local vars unnecessarily. this problem was introduced when we fixed C89 issues for MSVC
2014-05-12 13:41:49 +08:00
unsigned ImmOffs, Op;
initial import
2013-11-27 12:11:31 +08:00
if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right.
printOperand(MI, OpNum, O);
return;
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO1));
initial import
2013-11-27 12:11:31 +08:00
arm: add missing operand info for Thumb instruction vldr. bug reported by Daniel Colascione
2014-06-01 11:48:55 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0;
arm: add missing operand info for Thumb instruction vldr. bug reported by Daniel Colascione
2014-06-01 11:48:55 +08:00
}
first changes to get a successfully compiled version of capstone on VS2012
2014-05-09 06:44:49 +08:00
ImmOffs = ARM_AM_getAM5Offset((unsigned int)MCOperand_getImm(MO2));
Op = ARM_AM_getAM5Op((unsigned int)MCOperand_getImm(MO2));
initial import
2013-11-27 12:11:31 +08:00
if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM_sub) {
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (ImmOffs * 4 > HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, ", #%s0x%x",
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
ARM_AM_getAddrOpcStr(ARM_AM_getAM5Op((unsigned int)MCOperand_getImm(MO2))),
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
ImmOffs * 4);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, ", #%s%u",
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
ARM_AM_getAddrOpcStr(ARM_AM_getAM5Op((unsigned int)MCOperand_getImm(MO2))),
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
ImmOffs * 4);
arm: add missing the check for detail mode in the last commit
2014-06-01 11:52:01 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = ImmOffs * 4;
arm: add missing the check for detail mode in the last commit
2014-06-01 11:52:01 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "]");
arm: add missing operand info for Thumb instruction vldr. bug reported by Daniel Colascione
2014-06-01 11:48:55 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.op_count++;
arm: add missing operand info for Thumb instruction vldr. bug reported by Daniel Colascione
2014-06-01 11:48:55 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
static void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
do not initialize some local vars unnecessarily. this problem was introduced when we fixed C89 issues for MSVC
2014-05-12 13:41:49 +08:00
unsigned tmp;
initial import
2013-11-27 12:11:31 +08:00
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, true);
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO1));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
first changes to get a successfully compiled version of capstone on VS2012
2014-05-09 06:44:49 +08:00
tmp = (unsigned int)MCOperand_getImm(MO2);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (tmp) {
if (tmp << 3 > HEX_THRESHOLD)
SStream_concat(O, ":0x%x", (tmp << 3));
else
SStream_concat(O, ":%u", (tmp << 3));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp << 3;
initial import
2013-11-27 12:11:31 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "]");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, false);
}
static void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, true);
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO1));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "]");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, false);
}
static void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_getReg(MO) == 0)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "!");
initial import
2013-11-27 12:11:31 +08:00
else {
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO);
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
}
static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
uint32_t v = ~(uint32_t)MCOperand_getImm(MO);
initial import
2013-11-27 12:11:31 +08:00
int32_t lsb = CountTrailingZeros_32(v);
int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
initial import
2013-11-27 12:11:31 +08:00
//assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (lsb > HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#0x%x", lsb);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#%u", lsb);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (width > HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, ", #0x%x", width);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, ", #%u", width);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = lsb;
MI->flat_insn->detail->arm.op_count++;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = width;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O)
{
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
arm,arm64,mips,x86: rename PPC_getFeatureBits() to getFeatureBits()
2013-12-31 18:15:12 +08:00
// FIXME: HasV80Ops becomes a mode
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
// SStream_concat0(O, ARM_MB_MemBOptToString(val,
fix some warnings reported by MSVC
2014-05-12 15:15:32 +08:00
// ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops));
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ARM_MB_MemBOptToString(val, true));
initial import
2013-11-27 12:11:31 +08:00
}
void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O)
{
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ARM_ISB_InstSyncBOptToString(val));
initial import
2013-11-27 12:11:31 +08:00
}
static void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
unsigned ShiftOp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
initial import
2013-11-27 12:11:31 +08:00
bool isASR = (ShiftOp & (1 << 5)) != 0;
unsigned Amt = ShiftOp & 0x1f;
if (isASR) {
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
unsigned tmp = Amt == 0 ? 32 : Amt;
if (tmp > HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, ", asr #0x%x", tmp);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, ", asr #%u", tmp);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ASR;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = tmp;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
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} else if (Amt) {
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (Amt > HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
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SStream_concat(O, ", lsl #0x%x", Amt);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
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SStream_concat(O, ", lsl #%u", Amt);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Amt;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
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}
}
static void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O)
{
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
initial import
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if (Imm == 0)
return;
//assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (Imm > HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
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SStream_concat(O, ", lsl #0x%x", Imm);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
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SStream_concat(O, ", lsl #%u", Imm);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
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}
static void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O)
{
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
initial import
2013-11-27 12:11:31 +08:00
// A shift amount of 32 is encoded as 0.
if (Imm == 0)
Imm = 32;
//assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (Imm > HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, ", asr #0x%x", Imm);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, ", asr #%u", Imm);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ASR;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
// FIXME: push {r1, r2, r3, ...} can exceed the number of operands in MCInst struct
static void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O)
{
indentation with tab
2014-05-09 07:33:35 +08:00
unsigned i, e;
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "{");
initial import
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for (i = OpNum, e = MCInst_getNumOperands(MI); i != e; ++i) {
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
if (i != OpNum) SStream_concat0(O, ", ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, i)));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, i));
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
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}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "}");
initial import
2013-11-27 12:11:31 +08:00
}
static void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O,
MCRegisterInfo *MRI)
{
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_0));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_0);
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_1));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_1);
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
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}
// SETEND BE/LE
static void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNum);
if (MCOperand_getImm(Op))
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "be");
initial import
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else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "le");
initial import
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}
static void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNum);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ARM_PROC_IModToString((unsigned int)MCOperand_getImm(Op)));
initial import
2013-11-27 12:11:31 +08:00
}
static void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNum);
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
unsigned IFlags = (unsigned int)MCOperand_getImm(Op);
initial import
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int i;
for (i=2; i >= 0; --i)
if (IFlags & (1 << i))
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ARM_PROC_IFlagsToString(1 << i));
initial import
2013-11-27 12:11:31 +08:00
if (IFlags == 0)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "none");
initial import
2013-11-27 12:11:31 +08:00
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = IFlags;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
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}
static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNum);
arm: update core. this added a new instruction UDF. also updated Python+Java bindings accordingly
2014-08-13 22:38:15 +08:00
unsigned SpecRegRBit = MCOperand_getImm(Op) >> 4;
unsigned Mask = MCOperand_getImm(Op) & 0xf;
initial import
2013-11-27 12:11:31 +08:00
arm: update core. this added a new instruction UDF. also updated Python+Java bindings accordingly
2014-08-13 22:38:15 +08:00
if (ARM_getFeatureBits(MI->csh->mode) & ARM_FeatureMClass) {
unsigned SYSm = MCOperand_getImm(Op);
initial import
2013-11-27 12:11:31 +08:00
unsigned Opcode = MCInst_getOpcode(MI);
// For reads of the special registers ignore the "mask encoding" bits
// which are only for writes.
if (Opcode == ARM_t2MRS_M)
SYSm &= 0xff;
switch (SYSm) {
arm: update core. this added a new instruction UDF. also updated Python+Java bindings accordingly
2014-08-13 22:38:15 +08:00
default: //llvm_unreachable("Unexpected mask value!");
initial import
2013-11-27 12:11:31 +08:00
case 0:
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
case 0x800: SStream_concat0(O, "apsr"); return; // with _nzcvq bits is an alias for aspr
case 0x400: SStream_concat0(O, "apsr_g"); return;
case 0xc00: SStream_concat0(O, "apsr_nzcvqg"); return;
initial import
2013-11-27 12:11:31 +08:00
case 1:
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
case 0x801: SStream_concat0(O, "iapsr"); return; // with _nzcvq bits is an alias for iapsr
case 0x401: SStream_concat0(O, "iapsr_g"); return;
case 0xc01: SStream_concat0(O, "iapsr_nzcvqg"); return;
initial import
2013-11-27 12:11:31 +08:00
case 2:
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
case 0x802: SStream_concat0(O, "eapsr"); return; // with _nzcvq bits is an alias for eapsr
case 0x402: SStream_concat0(O, "eapsr_g"); return;
case 0xc02: SStream_concat0(O, "eapsr_nzcvqg"); return;
initial import
2013-11-27 12:11:31 +08:00
case 3:
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
case 0x803: SStream_concat0(O, "xpsr"); return; // with _nzcvq bits is an alias for xpsr
case 0x403: SStream_concat0(O, "xpsr_g"); return;
case 0xc03: SStream_concat0(O, "xpsr_nzcvqg"); return;
initial import
2013-11-27 12:11:31 +08:00
case 5:
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
case 0x805: SStream_concat0(O, "ipsr"); return;
initial import
2013-11-27 12:11:31 +08:00
case 6:
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
case 0x806: SStream_concat0(O, "epsr"); return;
initial import
2013-11-27 12:11:31 +08:00
case 7:
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
case 0x807: SStream_concat0(O, "iepsr"); return;
initial import
2013-11-27 12:11:31 +08:00
case 8:
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
case 0x808: SStream_concat0(O, "msp"); return;
initial import
2013-11-27 12:11:31 +08:00
case 9:
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
case 0x809: SStream_concat0(O, "psp"); return;
initial import
2013-11-27 12:11:31 +08:00
case 0x10:
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
case 0x810: SStream_concat0(O, "primask"); return;
initial import
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case 0x11:
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
case 0x811: SStream_concat0(O, "basepri"); return;
initial import
2013-11-27 12:11:31 +08:00
case 0x12:
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
case 0x812: SStream_concat0(O, "basepri_max"); return;
initial import
2013-11-27 12:11:31 +08:00
case 0x13:
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
case 0x813: SStream_concat0(O, "faultmask"); return;
initial import
2013-11-27 12:11:31 +08:00
case 0x14:
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
case 0x814: SStream_concat0(O, "control"); return;
initial import
2013-11-27 12:11:31 +08:00
}
}
arm: update core. this added a new instruction UDF. also updated Python+Java bindings accordingly
2014-08-13 22:38:15 +08:00
initial import
2013-11-27 12:11:31 +08:00
// As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
// APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
arm: update core. this added a new instruction UDF. also updated Python+Java bindings accordingly
2014-08-13 22:38:15 +08:00
SStream_concat0(O, "APSR_");
initial import
2013-11-27 12:11:31 +08:00
switch (Mask) {
arm: update core. this added a new instruction UDF. also updated Python+Java bindings accordingly
2014-08-13 22:38:15 +08:00
default: // llvm_unreachable("Unexpected mask value!");
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
case 4: SStream_concat0(O, "g"); return;
case 8: SStream_concat0(O, "nzcvq"); return;
case 12: SStream_concat0(O, "nzcvqg"); return;
initial import
2013-11-27 12:11:31 +08:00
}
}
if (SpecRegRBit)
arm: update core. this added a new instruction UDF. also updated Python+Java bindings accordingly
2014-08-13 22:38:15 +08:00
SStream_concat0(O, "SPSR");
initial import
2013-11-27 12:11:31 +08:00
else
arm: update core. this added a new instruction UDF. also updated Python+Java bindings accordingly
2014-08-13 22:38:15 +08:00
SStream_concat0(O, "CPSR");
initial import
2013-11-27 12:11:31 +08:00
if (Mask) {
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "_");
if (Mask & 8) SStream_concat0(O, "f");
if (Mask & 4) SStream_concat0(O, "s");
if (Mask & 2) SStream_concat0(O, "x");
if (Mask & 1) SStream_concat0(O, "c");
initial import
2013-11-27 12:11:31 +08:00
}
}
static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
// Handle the undefined 15 CC value here for printing so we don't abort().
if ((unsigned)CC == 15) {
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "<und>");
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.cc = ARM_CC_INVALID;
initial import
2013-11-27 12:11:31 +08:00
} else {
if (CC != ARMCC_AL) {
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ARMCC_ARMCondCodeToString(CC));
initial import
2013-11-27 12:11:31 +08:00
}
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.cc = CC + 1;
initial import
2013-11-27 12:11:31 +08:00
}
}
// TODO: test this
static void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ARMCC_ARMCondCodeToString(CC));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.cc = CC + 1;
initial import
2013-11-27 12:11:31 +08:00
}
static void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
if (MCOperand_getReg(MCInst_getOperand(MI, OpNum))) {
//assert(MCOperand_getReg(MCInst_getOperand(MI, OpNum)) == ARM_CPSR &&
// "Expect ARM CPSR register!");
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.update_flags = true;
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "s");
initial import
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}
}
static void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O)
{
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "0x%x", tmp);
else
SStream_concat(O, "%u", tmp);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
moving static doing_mem variable into cs_struct to guarantee thread-safe when handling memory operands
2013-12-31 22:40:04 +08:00
if (MI->csh->doing_mem) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
} else {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
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}
}
static void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O)
{
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
SStream_concat(O, "p%u", MCOperand_getImm(MCInst_getOperand(MI, OpNum)));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_PIMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
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}
static void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O)
{
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
SStream_concat(O, "c%u", MCOperand_getImm(MCInst_getOperand(MI, OpNum)));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_CIMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
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}
static void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O)
{
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "{0x%x}", tmp);
else
SStream_concat(O, "{%u}", tmp);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
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}
static void printAdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned scale)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
int32_t OffImm = (int32_t)MCOperand_getImm(MO) << scale;
if (OffImm == INT32_MIN) {
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "#-0");
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
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} else {
if (OffImm < 0)
arm: print immediate as 32bit rather than 64bit number. fix the bug reported by LongLD
2013-11-28 16:02:08 +08:00
SStream_concat(O, "#-0x%x", -OffImm);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
else {
if (OffImm > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", OffImm);
else
SStream_concat(O, "#%u", OffImm);
}
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
}
static void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)) * 4;
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (tmp > HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#0x%x", tmp);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#%u", tmp);
more fixes on C coding style
2014-01-23 22:29:04 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
MI->flat_insn->detail->arm.op_count++;
more fixes on C coding style
2014-01-23 22:29:04 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
static void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O)
{
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
unsigned tmp = Imm == 0 ? 32 : Imm;
if (tmp > HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#0x%x", tmp);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#%u", tmp);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
// TODO
static void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O)
{
// (3 - the number of trailing zeros) is the number of then / else.
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
unsigned Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum-1));
initial import
2013-11-27 12:11:31 +08:00
unsigned CondBit0 = Firstcond & 1;
unsigned NumTZ = CountTrailingZeros_32(Mask);
//assert(NumTZ <= 3 && "Invalid IT mask!");
unsigned Pos, e;
for (Pos = 3, e = NumTZ; Pos > e; --Pos) {
bool T = ((Mask >> Pos) & 1) == CondBit0;
if (T)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "t");
initial import
2013-11-27 12:11:31 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "e");
initial import
2013-11-27 12:11:31 +08:00
}
}
static void printThumbAddrModeRROperand(MCInst *MI, unsigned Op, SStream *O)
{
MCOperand *MO1 = MCInst_getOperand(MI, Op);
MCOperand *MO2 = MCInst_getOperand(MI, Op + 1);
do not initialize some local vars unnecessarily. this problem was introduced when we fixed C89 issues for MSVC
2014-05-12 13:41:49 +08:00
unsigned RegNum;
initial import
2013-11-27 12:11:31 +08:00
if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right.
printOperand(MI, Op, O);
return;
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, true);
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO1));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
first changes to get a successfully compiled version of capstone on VS2012
2014-05-09 06:44:49 +08:00
RegNum = MCOperand_getReg(MO2);
initial import
2013-11-27 12:11:31 +08:00
if (RegNum) {
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, RegNum);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = RegNum;
initial import
2013-11-27 12:11:31 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "]");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, false);
}
static void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned Op, SStream *O,
unsigned Scale)
{
MCOperand *MO1 = MCInst_getOperand(MI, Op);
MCOperand *MO2 = MCInst_getOperand(MI, Op + 1);
do not initialize some local vars unnecessarily. this problem was introduced when we fixed C89 issues for MSVC
2014-05-12 13:41:49 +08:00
unsigned ImmOffs, tmp;
initial import
2013-11-27 12:11:31 +08:00
if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right.
printOperand(MI, Op, O);
return;
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, true);
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO1));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
first changes to get a successfully compiled version of capstone on VS2012
2014-05-09 06:44:49 +08:00
ImmOffs = (unsigned int)MCOperand_getImm(MO2);
initial import
2013-11-27 12:11:31 +08:00
if (ImmOffs) {
first changes to get a successfully compiled version of capstone on VS2012
2014-05-09 06:44:49 +08:00
tmp = ImmOffs * Scale;
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", tmp);
else
SStream_concat(O, "#%u", tmp);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp;
initial import
2013-11-27 12:11:31 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "]");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, false);
}
static void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned Op, SStream *O)
{
printThumbAddrModeImm5SOperand(MI, Op, O, 1);
}
static void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned Op, SStream *O)
{
printThumbAddrModeImm5SOperand(MI, Op, O, 2);
}
static void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned Op, SStream *O)
{
printThumbAddrModeImm5SOperand(MI, Op, O, 4);
}
static void printThumbAddrModeSPOperand(MCInst *MI, unsigned Op, SStream *O)
{
printThumbAddrModeImm5SOperand(MI, Op, O, 4);
}
// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
// register with shift forms.
// REG 0 0 - e.g. R5
// REG IMM, SH_OPC - e.g. R5, LSL #3
static void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
unsigned Reg = MCOperand_getReg(MO1);
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, Reg);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
// Print the shift opc.
//assert(MO2.isImm() && "Not a valid t2_so_reg value!");
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)),
arm: do not use markup
2014-06-10 01:39:06 +08:00
getSORegOffset((unsigned int)MCOperand_getImm(MO2)));
initial import
2013-11-27 12:11:31 +08:00
}
static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum,
SStream *O, bool AlwaysPrintImm0)
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
more fixes on C coding style
2014-01-23 22:29:04 +08:00
int32_t OffImm;
bool isSub;
initial import
2013-11-27 12:11:31 +08:00
if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right.
printOperand(MI, OpNum, O);
return;
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, true);
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO1));
initial import
2013-11-27 12:11:31 +08:00
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
initial import
2013-11-27 12:11:31 +08:00
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
OffImm = (int32_t)MCOperand_getImm(MO2);
isSub = OffImm < 0;
initial import
2013-11-27 12:11:31 +08:00
// Special value for #-0. All others are normal.
if (OffImm == INT32_MIN)
OffImm = 0;
if (isSub) {
arm: print address Imm without prefix 0x for Imm >= -9
2014-04-12 00:19:42 +08:00
if (OffImm < -HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, ", #-0x%x", -OffImm);
arm: print address Imm without prefix 0x for Imm >= -9
2014-04-12 00:19:42 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, ", #-%u", -OffImm);
initial import
2013-11-27 12:11:31 +08:00
} else if (AlwaysPrintImm0 || OffImm > 0) {
arm: more fix to print negative numbers in more friendly way
2014-03-26 16:21:31 +08:00
if (OffImm >= 0) {
if (OffImm > HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, ", #0x%x", OffImm);
arm: more fix to print negative numbers in more friendly way
2014-03-26 16:21:31 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, ", #%u", OffImm);
arm: more fix to print negative numbers in more friendly way
2014-03-26 16:21:31 +08:00
} else {
if (OffImm < -HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, ", #-0x%x", -OffImm);
arm: more fix to print negative numbers in more friendly way
2014-03-26 16:21:31 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, ", #-%u", -OffImm);
arm: more fix to print negative numbers in more friendly way
2014-03-26 16:21:31 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "]");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, false);
}
static void printT2AddrModeImm8Operand(MCInst *MI, unsigned OpNum, SStream *O,
bool AlwaysPrintImm0)
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
more fixes on C coding style
2014-01-23 22:29:04 +08:00
int32_t OffImm;
bool isSub;
initial import
2013-11-27 12:11:31 +08:00
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, true);
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO1));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
initial import
2013-11-27 12:11:31 +08:00
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
OffImm = (int32_t)MCOperand_getImm(MO2);
isSub = OffImm < 0;
initial import
2013-11-27 12:11:31 +08:00
// Don't print +0.
if (OffImm == INT32_MIN)
OffImm = 0;
if (isSub)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, ", #-0x%x", -OffImm);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
else if (AlwaysPrintImm0 || OffImm > 0) {
if (OffImm > HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, ", #0x%x", OffImm);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, ", #%u", OffImm);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "]");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, false);
}
static void printT2AddrModeImm8s4Operand(MCInst *MI,
unsigned OpNum, SStream *O, bool AlwaysPrintImm0)
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
more fixes on C coding style
2014-01-23 22:29:04 +08:00
int32_t OffImm;
bool isSub;
initial import
2013-11-27 12:11:31 +08:00
if (!MCOperand_isReg(MO1)) { // For label symbolic references.
printOperand(MI, OpNum, O);
return;
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, true);
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO1));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
initial import
2013-11-27 12:11:31 +08:00
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
OffImm = (int32_t)MCOperand_getImm(MO2);
isSub = OffImm < 0;
initial import
2013-11-27 12:11:31 +08:00
//assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
// Don't print +0.
if (OffImm == INT32_MIN)
OffImm = 0;
if (isSub) {
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, ", #-0x%x", -OffImm);
initial import
2013-11-27 12:11:31 +08:00
} else if (AlwaysPrintImm0 || OffImm > 0) {
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (OffImm > HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, ", #0x%x", OffImm);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, ", #%u", OffImm);
initial import
2013-11-27 12:11:31 +08:00
}
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
initial import
2013-11-27 12:11:31 +08:00
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "]");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, false);
}
static void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
do not initialize some local vars unnecessarily. this problem was introduced when we fixed C89 issues for MSVC
2014-05-12 13:41:49 +08:00
unsigned tmp;
initial import
2013-11-27 12:11:31 +08:00
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, true);
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO1));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
initial import
2013-11-27 12:11:31 +08:00
if (MCOperand_getImm(MO2)) {
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
first changes to get a successfully compiled version of capstone on VS2012
2014-05-09 06:44:49 +08:00
tmp = (unsigned int)MCOperand_getImm(MO2) * 4;
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", tmp);
else
SStream_concat(O, "#%u", tmp);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp;
initial import
2013-11-27 12:11:31 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "]");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, false);
}
static void printT2AddrModeImm8OffsetOperand(MCInst *MI,
unsigned OpNum, SStream *O)
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
int32_t OffImm = (int32_t)MCOperand_getImm(MO1);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
initial import
2013-11-27 12:11:31 +08:00
if (OffImm == INT32_MIN) {
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "#-0");
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
} else {
arm: more fix to print negative numbers in more friendly way
2014-03-26 16:21:31 +08:00
if (OffImm < 0) {
if (OffImm < -HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#-0x%x", -OffImm);
arm: more fix to print negative numbers in more friendly way
2014-03-26 16:21:31 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#-%u", -OffImm);
arm: more fix to print negative numbers in more friendly way
2014-03-26 16:21:31 +08:00
} else {
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (OffImm > HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#0x%x", OffImm);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#%u", OffImm);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
}
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
}
static void printT2AddrModeImm8s4OffsetOperand(MCInst *MI,
unsigned OpNum, SStream *O)
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
int32_t OffImm = (int32_t)MCOperand_getImm(MO1);
//assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
initial import
2013-11-27 12:11:31 +08:00
if (OffImm == INT32_MIN) {
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "#-0");
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
} else {
arm: more fix to print negative numbers in more friendly way
2014-03-26 16:21:31 +08:00
if (OffImm < 0) {
if (OffImm < -HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#-0x%x", -OffImm);
arm: more fix to print negative numbers in more friendly way
2014-03-26 16:21:31 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#-%u", -OffImm);
arm: more fix to print negative numbers in more friendly way
2014-03-26 16:21:31 +08:00
} else {
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (OffImm > HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#0x%x", OffImm);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#%u", OffImm);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
}
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
}
static void printT2AddrModeSoRegOperand(MCInst *MI,
unsigned OpNum, SStream *O)
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
MCOperand *MO3 = MCInst_getOperand(MI, OpNum+2);
do not initialize some local vars unnecessarily. this problem was introduced when we fixed C89 issues for MSVC
2014-05-12 13:41:49 +08:00
unsigned ShAmt;
initial import
2013-11-27 12:11:31 +08:00
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, true);
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO1));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
initial import
2013-11-27 12:11:31 +08:00
//assert(MCOperand_getReg(MO2.getReg() && "Invalid so_reg load / store address!");
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MO2));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail)
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
initial import
2013-11-27 12:11:31 +08:00
first changes to get a successfully compiled version of capstone on VS2012
2014-05-09 06:44:49 +08:00
ShAmt = (unsigned int)MCOperand_getImm(MO3);
initial import
2013-11-27 12:11:31 +08:00
if (ShAmt) {
//assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", lsl ");
initial import
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SStream_concat(O, "#%d", ShAmt);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = ShAmt;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "]");
initial import
2013-11-27 12:11:31 +08:00
set_mem_access(MI, false);
}
static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#%f", getFPImmFloat((unsigned int)MCOperand_getImm(MO)));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_FP;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].fp = getFPImmFloat((unsigned int)MCOperand_getImm(MO));
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
static void printNEONModImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
unsigned EncodedImm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
initial import
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unsigned EltBits;
uint64_t Val = ARM_AM_decodeNEONModImm(EncodedImm, &EltBits);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (Val > HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#0x%"PRIx64, Val);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#%"PRIu64, Val);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = (unsigned int)Val;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
static void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (Imm + 1 > HEX_THRESHOLD)
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#0x%x", Imm + 1);
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
else
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat(O, "#%u", Imm + 1);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm + 1;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
initial import
2013-11-27 12:11:31 +08:00
if (Imm == 0)
return;
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ror #");
initial import
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switch (Imm) {
default: //assert (0 && "illegal ror immediate!");
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
case 1: SStream_concat0(O, "8"); break;
case 2: SStream_concat0(O, "16"); break;
case 3: SStream_concat0(O, "24"); break;
initial import
2013-11-27 12:11:31 +08:00
}
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ROR;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm * 8;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O)
{
do not initialize some local vars unnecessarily. this problem was introduced when we fixed C89 issues for MSVC
2014-05-12 13:41:49 +08:00
unsigned tmp;
first changes to get a successfully compiled version of capstone on VS2012
2014-05-09 06:44:49 +08:00
tmp = 16 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", tmp);
else
SStream_concat(O, "#%u", tmp);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O)
{
do not initialize some local vars unnecessarily. this problem was introduced when we fixed C89 issues for MSVC
2014-05-12 13:41:49 +08:00
unsigned tmp;
first changes to get a successfully compiled version of capstone on VS2012
2014-05-09 06:44:49 +08:00
tmp = 32 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", tmp);
else
SStream_concat(O, "#%u", tmp);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O)
{
Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
2014-01-23 01:45:00 +08:00
unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
ARM: Fix bunch of issues - Bugs - start switching to more friendly asm: for number under 10, print without hex in front
2013-12-11 17:35:27 +08:00
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "[0x%x]",tmp);
else
SStream_concat(O, "[%u]",tmp);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
initial import
2013-11-27 12:11:31 +08:00
}
static void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O)
{
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "{");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "}");
initial import
2013-11-27 12:11:31 +08:00
}
static void printVectorListTwo(MCInst *MI, unsigned OpNum,
SStream *O, MCRegisterInfo *MRI)
{
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0);
unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_1);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "{");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, Reg0);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, Reg1);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "}");
initial import
2013-11-27 12:11:31 +08:00
}
static void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum,
SStream *O, MCRegisterInfo *MRI)
{
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0);
unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_2);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "{");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, Reg0);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, Reg1);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "}");
initial import
2013-11-27 12:11:31 +08:00
}
static void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O)
{
// Normally, it's not safe to use register enum values directly with
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "{");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "}");
initial import
2013-11-27 12:11:31 +08:00
}
static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O)
{
// Normally, it's not safe to use register enum values directly with
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "{");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "}");
initial import
2013-11-27 12:11:31 +08:00
}
static void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
{
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "{");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[]}");
initial import
2013-11-27 12:11:31 +08:00
}
static void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum,
SStream *O, MCRegisterInfo *MRI)
{
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0);
unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_1);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "{");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, Reg0);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[], ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, Reg1);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[]}");
initial import
2013-11-27 12:11:31 +08:00
}
static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
{
// Normally, it's not safe to use register enum values directly with
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "{");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[], ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[], ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[]}");
initial import
2013-11-27 12:11:31 +08:00
}
static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
{
// Normally, it's not safe to use register enum values directly with
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "{");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[], ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[], ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[], ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[]}");
initial import
2013-11-27 12:11:31 +08:00
}
static void printVectorListTwoSpacedAllLanes(MCInst *MI,
unsigned OpNum, SStream *O, MCRegisterInfo *MRI)
{
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0);
unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_2);
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "{");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, Reg0);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[], ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, Reg1);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[]}");
initial import
2013-11-27 12:11:31 +08:00
}
static void printVectorListThreeSpacedAllLanes(MCInst *MI,
unsigned OpNum, SStream *O)
{
// Normally, it's not safe to use register enum values directly with
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "{");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[], ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[], ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[]}");
initial import
2013-11-27 12:11:31 +08:00
}
static void printVectorListFourSpacedAllLanes(MCInst *MI,
unsigned OpNum, SStream *O)
{
// Normally, it's not safe to use register enum values directly with
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "{");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[], ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[], ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[], ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "[]}");
initial import
2013-11-27 12:11:31 +08:00
}
static void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O)
{
// Normally, it's not safe to use register enum values directly with
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "{");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "}");
initial import
2013-11-27 12:11:31 +08:00
}
static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O)
{
// Normally, it's not safe to use register enum values directly with
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "{");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, ", ");
arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
2014-03-11 00:18:50 +08:00
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6);
initial support for PPC
2013-12-30 00:15:25 +08:00
if (MI->csh->detail) {
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 09:00:18 +08:00
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6;
MI->flat_insn->detail->arm.op_count++;
support to turn on/off building instruction details
2013-12-14 00:23:41 +08:00
}
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 01:37:53 +08:00
SStream_concat0(O, "}");
initial import
2013-11-27 12:11:31 +08:00
}
enable arch code from source with CAPSTONE_HAS_* for MSVC to pick up
2014-05-14 11:26:41 +08:00
#endif