Virtualization
/
capstone
mirror of https://gitlab.com/qemu-project/capstone.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
1,234 Commits 18 Branches 46 Tags 73 MiB
Commit Graph

1234 Commits

Author SHA1 Message Date
Nguyen Anh Quynh 112556d9f9 msvc: rename test_arm.vcxproj to test_xcore.vcxproj 2014-05-27 23:57:52 +08:00
Nguyen Anh Quynh c54b7ac907 python: add test_xcore.py 2014-05-27 23:37:33 +08:00
Nguyen Anh Quynh cfc7ca6ace python & java: update constants for Xcore after the last change in the core 2014-05-27 23:34:41 +08:00
Nguyen Anh Quynh be2b788dc1 xcore: handle details for some special tricky instructions 2014-05-27 23:34:03 +08:00
Nguyen Anh Quynh 8c1c36f0fc update TODO 2014-05-27 16:17:26 +08:00
Nguyen Anh Quynh 4d00986c6b java: add Xcore support 2014-05-27 14:54:28 +08:00
Nguyen Anh Quynh 2eff6a377c msvc: support XCore 2014-05-27 11:41:46 +08:00
Nguyen Anh Quynh f721e3124d Disassembler -> Disassembly 2014-05-27 10:45:58 +08:00
Nguyen Anh Quynh 8f50ba894c Merge branch 'next' into xcore 2014-05-27 10:39:11 +08:00
Nguyen Anh Quynh 04f2ec6d0f cleanup redundant headers included 2014-05-27 10:39:04 +08:00
Nguyen Anh Quynh 2cf9c524da x86: MOV64rr belongs to GRP_MODE64 group. bug reported by Jason Oster 2014-05-27 07:23:53 +08:00
Nguyen Anh Quynh d0f3e15d90 python: fix Xcore bug 2014-05-27 00:05:16 +08:00
Nguyen Anh Quynh 553bb488d7 python: support XCore 2014-05-26 23:47:45 +08:00
Nguyen Anh Quynh 52a8d2afa2 enable disabled archs 2014-05-26 23:24:11 +08:00
Nguyen Anh Quynh c80d840ffc add XCore architecture 2014-05-26 23:02:48 +08:00
Nguyen Anh Quynh 3dc080c2b6 systemz: cleanup SystemZGenDisassemblerTables.inc 2014-05-26 15:54:16 +08:00
Nguyen Anh Quynh 5a5d8a71cd python & java: fix Sparc's CC constants after the last change in the core 2014-05-25 13:49:12 +08:00
Nguyen Anh Quynh 5d6383e335 sparc: SPARC_CC_ICC_N should not have the same value as SPARC_CC_INVALID. bug reported by Jason Oster 2014-05-25 13:48:06 +08:00
Nguyen Anh Quynh 708d151fb6 Merge pull request #127 from parasyte/bug/SystemZ/r0l-reg 
Add `r0l` register to SystemZMapping.c
 2014-05-25 12:31:43 +08:00
Jason Oster 6380446222 Add `r0l` register to SystemZMapping.c 2014-05-24 21:26:12 -07:00
Nguyen Anh Quynh 0ebbf1e49c python: ArmOpValue.imm uses int32 type after the last change in the core 2014-05-24 13:33:14 +08:00
Nguyen Anh Quynh eddf47c712 Merge pull request #125 from parasyte/ticket-124 
ARM: Make `imm` detail field signed.
 2014-05-24 13:29:07 +08:00
Jason Oster aa60b8cd1b [#124] ARM: Make `imm` detail field signed. 2014-05-23 21:55:04 -07:00
Nguyen Anh Quynh e96e34df9a python: test_x86.py print prefixes with a space between consecutive bytes 2014-05-22 12:33:29 +08:00
Nguyen Anh Quynh 4ebd062ee3 x86: cleanup unused code 2014-05-22 12:11:35 +08:00
Nguyen Anh Quynh fed098f9a7 x86: eliminate irrelevant prefixes in x86.prefix[] - such as f2/f3 prefixed irrelevant instructions 2014-05-22 12:10:21 +08:00
Nguyen Anh Quynh 1e93adf5c3 x86: add CL operand into details for 'SHL *, CL' instruction 2014-05-21 17:10:10 +08:00
Nguyen Anh Quynh 7a65ad7e4b x86: detail operands for 'fstpnce st(0), st(0)' & 'fstpst(7), st(0)' 2014-05-21 16:18:56 +08:00
Nguyen Anh Quynh b6e3f01bb8 x86: handle REP MOVSD/CMPSD/SCASD/LODSD/STOSD properly (due to confused 128bit media instructions having the same mnemonics) 2014-05-21 15:11:58 +08:00
Nguyen Anh Quynh 3a86d92e7c x86: correct instructions related to REP prefix 2014-05-21 14:12:24 +08:00
Nguyen Anh Quynh 1d6f7ee50e x86: prefix REP/REPNE are only relevant for MOVS/CMPS/SCAS/LDOS/STOS/INS/OUTS instructions 2014-05-21 12:38:10 +08:00
Nguyen Anh Quynh 7a75baa679 Merge pull request #122 from parasyte/next 
MIPS: Add HI, LO, and PC registers to MipsMapping.c
 2014-05-20 14:22:06 +08:00
Jason Oster 984ed7e9e8 MIPS: Add HI, LO, and PC registers to MipsMapping.c 
- Using MIPS_REG_HI, MIPS_REG_LO, and MIPS_REG_PC with cs_reg_name() caused out-of-bounds reads
 2014-05-19 22:56:19 -07:00
Nguyen Anh Quynh 2c61656d99 tests: correct the prototype of mycallback() in test_skipdata 2014-05-20 10:30:33 +08:00
danghvu 50fdc6c463 Merge with upstream 2014-05-19 21:21:03 -05:00
danghvu 69a7c2d580 Make test_skipdata performs tests by default 2014-05-19 20:52:25 -05:00
Nguyen Anh Quynh 7b91574257 TODO: remove Python3 & MSVC from wanted features 2014-05-19 21:15:17 +08:00
Nguyen Anh Quynh 6f9b113009 update COMPILE_MSVC.TXT 2014-05-19 17:06:44 +08:00
Nguyen Anh Quynh 6456481508 x86: add immediate operand (1) for SHL/SHR/ROR/ROL/SAR/SAL in detail mode & Intel syntax 2014-05-19 16:46:31 +08:00
Nguyen Anh Quynh f338657f17 x86: set syntax variable when changing syntax with cs_option() 2014-05-19 16:34:54 +08:00
Nguyen Anh Quynh f260c2023e fix some conflicts when merging msvc2 into next 2014-05-19 11:32:55 +08:00
Nguyen Anh Quynh 1922b2f74b arm64: clean reg_name_maps[] 2014-05-18 10:30:09 +08:00
Nguyen Anh Quynh 61882e56d5 msvc: update documentation for VS2010 2014-05-18 00:39:49 +08:00
Nguyen Anh Quynh 96934501fd arm64: do not consider WZR & XZR alias registers 2014-05-18 00:07:24 +08:00
Nguyen Anh Quynh cb2c4f90bf test_x86: output sib_base, sib_index, sib_scale separately 2014-05-17 13:12:29 +08:00
Nguyen Anh Quynh 688efe3018 python: properly handle SIB's registers on irrelevant cases (zero value) of test_x86.py 2014-05-17 11:08:08 +08:00
Nguyen Anh Quynh 1aa60d0921 python: handle invalid argument (zero) for reg_name() & insn_name() of class CsInsn 2014-05-17 11:06:44 +08:00
Nguyen Anh Quynh 1098329f40 python: refactor tests, so it is possible to reuse print_insn_detail() of all archs 2014-05-17 09:51:15 +08:00
Nguyen Anh Quynh fc3636a0b8 python: update test_all.py 2014-05-17 09:45:23 +08:00
Nguyen Anh Quynh 7dcb1dd177 Merge branch 'test' into msvc2 2014-05-16 16:55:31 +08:00