19ee2d10b3
inttypes.h fix
2015-03-29 21:16:38 +08:00
e0329ddde3
arm: printModImmOperand() should print Imm as unsigned number in some special cases
2015-03-08 00:29:20 +08:00
b8b83482b7
arm: print immediate in hex format when suitable for printModImmOperand()
2015-03-07 00:26:24 +08:00
bfcaba5851
2015
2015-03-04 17:45:23 +08:00
7e25609ad3
arm: fix bugs in the last commit
2015-03-03 18:28:10 +08:00
d1fc2bd3b9
arm: update core
2015-03-03 16:26:32 +08:00
4b68d9505e
arm: fix some warnings reported by MSVC
2015-02-25 18:02:19 +08:00
ced9a6ed92
Correct printAM3PreOrOffsetIndexOp disp value
2015-02-15 22:41:20 +08:00
58fbf2f627
arm: add few more post-indexed instructions doing writeback
2015-01-21 12:25:36 +08:00
5719eb5a9d
arm: fix a bug in the last commit
2015-01-21 12:16:15 +08:00
03e5e106b0
arm: some load/store instructions writeback without bang letter. bug reported by @jabba2989
2015-01-21 12:15:14 +08:00
706b808af3
arm: add lshift field to arm_op_mem to provide left-shift value for index register in some memory op. issue reported by @jabba2989
2015-01-12 15:27:29 +08:00
3caf837c9a
arm: alias LDR instruction with operands '[sp], 4' to POP. suggested by Pancake
2014-11-27 14:34:40 +08:00
a2934a7b6a
arm: print immediate op of MVN instruction in positive hexadecimal form. issue reported by Pancake
2014-11-25 21:02:18 +08:00
1ffc1b2201
arm: fix printMemBOption() that was wrongly fixed in 51888c3e08
2014-11-12 13:33:15 +08:00
51888c3e08
arm: fix some bugs reported by VS2010. thanks Axel for testing
2014-11-11 23:59:23 +08:00
8cdafda551
arm: add new field mem_barrier to cs_arm struct. this requires changes in bindings
2014-11-11 22:30:30 +08:00
278e7270d9
arm: print immediate in positive form for AND/ORR/EOR/BIC instructions
2014-11-11 12:50:43 +08:00
2ac5d79353
arm: print floating point number in %e format
2014-11-10 21:46:34 +08:00
6acaaa5e44
arm: printAddrMode5Operand() is wrong on calculating subtracted variable
2014-11-10 17:41:05 +08:00
d865f39a68
arm: use lowercase for special registers
2014-11-10 16:38:17 +08:00
2593e22932
arm: support V8 as a mode for A32 encodings
2014-11-10 16:35:38 +08:00
8bf5fa60ad
arm: remove dead code
2014-10-07 07:56:01 +08:00
b0cc71da59
bindings: update java/ocaml/python after the last change in Arm's core
2014-10-06 21:01:32 +08:00
8fb2eab459
arm: some operands can get subtracted from base register, thus have '-' sign associated. this adds subtracted field into cs_arm_op to provide this info. issue reported by Yegor Derevenets
2014-10-06 20:27:25 +08:00
4e87675c54
arm: relative branch should not be negative. bug reported by @acez
2014-09-23 16:49:12 +08:00
ced9d24e35
Workaround missing <inttypes.h> on MSVC 2010
2014-09-21 17:27:11 +02:00
04d9f8ee17
arm: update core with a lot more details provided in detail mode now. update Python & Java bindings to reflect the core's changes
2014-09-01 23:27:24 +08:00
07c92ec20a
fix warnings reported by MSVC
2014-08-26 15:35:11 +08:00
b52f11f636
arm: update core. this added a new instruction UDF. also updated Python+Java bindings accordingly
2014-08-13 22:38:15 +08:00
0c235e15ab
arm: some simple improvements & cleanups
2014-07-31 21:16:54 +08:00
26dfbc6677
fix indentation introduced by the latest merge. also move test_arm_regression.c into suite/arm/ and add Makefile for it
2014-07-31 18:24:51 +08:00
298d413bbc
* added a test file to suite for testing invalid and valid instruction sequences
...
* fixed and added a test for a thumb-2 invalid sequence that was incorrectly allowed before these changes (pop.w with sp argument included)
* fixed and added a test for a blx from thumb to ARM that had its immediate argument incorrect (misaligned)
* eliminated some warnings by explicitly casting so I could turn on
treat warnings as errors locally
General notes:
* probably worth turning on treat all warnings as errors in the msvc project files, had a subtle bug that resulted from a missing declaration causing differences in dll and static compilation modes
( code was working incorrectly in dll form because of missing declaration in arch/ARM/ARMMapping.h for new function ARM_blx_to_arm_mode. Something about the linking was confusing ld when making the dll, and the resulting offsets were wonky (e.g. the added ble test would show up as #0x1fc instead of #0x1fe like it should have )
* the invalid pop was being treated as a soft fail which then gets coerced
to a success because it is != MCDisassembler_Fail in Thumb_getInstruction
what are the semantics of a soft fail? Maybe we should be able to set up
whether or not we want a soft fail to be a real fail in the csh struct?
2014-07-15 04:33:40 -04:00
73eb5d5486
arm: op_addImm() is called only when detail mode is ON
2014-06-17 18:08:29 +08:00
ebe2443b9b
arm: some special instructions need to have numerical operand added manually in printInstruction()
2014-06-17 13:56:01 +08:00
8693fcdc99
arm: correct operand setup for REG type in printAddrMode3OffsetOperand()
2014-06-17 13:28:33 +08:00
495295ecd4
MCInst_Init() is arch-independent
2014-06-16 15:54:32 +08:00
9678705d57
arm: convert MCOperand_CreateReg() to MCOperand_CreateReg0() to avoid malloc/free
2014-06-10 13:59:55 +07:00
8c1104b567
arm: do not use markup
2014-06-10 00:39:06 +07:00
dd9225b930
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 00:37:53 +07:00
29fd0f6405
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd4
2014-06-09 08:00:18 +07:00
30c065998b
optimize memset() of MCInst_Init()
2014-06-07 13:30:59 +08:00
c70442edc6
arm: shift info associates with the right op in LDR instruction. bug reported by Daniel Colascione
2014-06-01 11:35:34 +07:00
a04ee4feb8
arm: add missing the check for detail mode in the last commit
2014-06-01 10:52:01 +07:00
b79d915a38
arm: add missing operand info for Thumb instruction vldr. bug reported by Daniel Colascione
2014-06-01 10:48:55 +07:00
bb71c13098
arm: add missing operand info for Thumb instruction LDR involving label. bug reported by Daniel Colascione
2014-06-01 10:14:31 +07:00
6eb55cf52e
arm: add operand details for 'mov pc, lr'. bug reported by Daniel Colascione
2014-06-01 10:03:14 +07:00
48b6cb4ce5
arm: CC_AL is the default code condition for instructions without CC. bug reported by Daniel Colascione
2014-06-01 09:45:19 +07:00
5e2e660be7
fix some warnings reported by Coverity
2014-05-30 17:43:36 +08:00
6456481508
x86: add immediate operand (1) for SHL/SHR/ROR/ROL/SAR/SAL in detail mode & Intel syntax
2014-05-19 16:46:31 +08:00
Cr4sh