capstone/arch/ARM
Nguyen Anh Quynh 5b92f8c1da arm: POP {reg} read/write SP register. this fixes #913 2017-05-04 17:21:41 +08:00
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ARMAddressingModes.h arm: use SStream_concat0() for SStream_concat() whereever possible for better performance 2014-06-10 00:37:53 +07:00
ARMBaseInfo.h arm: add new field mem_barrier to cs_arm struct. this requires changes in bindings 2014-11-11 22:30:30 +08:00
ARMDisassembler.c Use the correct mapping for 32-bit Thumb Big-Endian insns 2016-11-13 23:18:13 -05:00
ARMDisassembler.h arm: add new mode CS_MODE_MCLASS for Cortex-M series. updated Python & Java bindings accordingly 2014-08-13 23:08:40 +08:00
ARMGenAsmWriter.inc arm: lowercase for apsr_nzcv 2014-11-10 17:02:32 +08:00
ARMGenDisassemblerTables.inc arm: update core. this added a new instruction UDF. also updated Python+Java bindings accordingly 2014-08-13 22:38:15 +08:00
ARMGenInstrInfo.inc arm: more optimization on MCInstrDesc struct to reduce the library size by further 20KB 2015-03-10 17:30:26 +08:00
ARMGenRegisterInfo.inc arm: update core. this added a new instruction UDF. also updated Python+Java bindings accordingly 2014-08-13 22:38:15 +08:00
ARMGenSubtargetInfo.inc arm: update core. this added a new instruction UDF. also updated Python+Java bindings accordingly 2014-08-13 22:38:15 +08:00
ARMInstPrinter.c arm: POP {reg} read/write SP register. this fixes #913 2017-05-04 17:21:41 +08:00
ARMInstPrinter.h arm: update core with a lot more details provided in detail mode now. update Python & Java bindings to reflect the core's changes 2014-09-01 23:27:24 +08:00
ARMMapping.c Patch for issue #842 2017-01-18 17:35:42 +00:00
ARMMapping.h arm: update core with a lot more details provided in detail mode now. update Python & Java bindings to reflect the core's changes 2014-09-01 23:27:24 +08:00
ARMModule.c switch endian mode with cs_option() for Arm/Arm64/Mips/Sparc. fix issue #849 2017-02-01 11:17:13 +08:00