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dcbdbd92b92e1051cb8141da8ac281d9bb53b521
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1164 Commits

Author SHA1 Message Date
Pawel Wilma
dcbdbd92b9 Wait for paging frence after calling makeResident() on mapGpuVa 
Change-Id: I289c4be891b2d7c1b50a0100cbdde8688f3068d5
Signed-off-by: Pawel Wilma <pawel.wilma@intel.com>
 2019-01-17 10:41:28 +01:00
Zdunowski, Piotr
75a635fdc5 [1/n] Log allocation placement. 
Change-Id: I9ab61e10dcb0fcbbaf859c077a64ce7a4f2c213c
 2019-01-16 16:46:50 +01:00
Pawel Wilma
9036882d11 Refactoring of additional MMIO registers in AubDump 
Change-Id: I97c0cc25aa24c6abcff4ba7469d6a6e3f0c12b86
 2019-01-16 11:16:54 +01:00
Zdanowicz, Zbigniew
f18f9a5f88 Use queue command buffer to program media sampler at submit 
Change-Id: I7cc410a7432564b5f15dbb6943f48b577dfa6936
 2019-01-15 15:45:44 +01:00
Dunajski, Bartosz
1de0bda212 Initialize HardwareContext with valid deviceIndex and engineIndex 
Change-Id: I8848936340e8f4b33ac5ed5d0ae85d9f580171ca
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-01-15 15:33:42 +01:00
Mrozek, Michal
7470246376 Add new flag to dispatch info. 
Change-Id: I0d78658529f3e80f1694b14ff05425ecceafd340
 2019-01-15 12:21:18 +01:00
Mateusz Jablonski
06600f169b Define GPGPU engines per gen 
Change-Id: Ie0e565d11184c5355b5bf09f5b10a567deb5c106
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2019-01-15 12:05:19 +01:00
Zdanowicz, Zbigniew
84d35c8951 Add media programming call at the end of command buffer 
Change-Id: Ie60bc384c9385071aa77d2516e1d3649298a1233
 2019-01-15 11:35:58 +01:00
Stefanowski, Adam
1001f76085 Add logic for Events in multi-thread scenario 
- inc refCount when enqueue is blocked and dec after flushing

Change-Id: I9e8f8d226897124a7e51f2473939d53868bef7a2
 2019-01-14 19:45:26 +01:00
Mrozek, Michal
9cbfa3892d Remove debug flag. 
Change-Id: I013e1f27477d67fd33ba6c559dffb26d06a0db8b
 2019-01-14 15:19:57 +01:00
Filip Hazubski
ec03210687 Update clEnqueueVerifyMemory 
- return success also for non aub CSRs

Change-Id: Iac7fdcd58e4b76a325ef67fd266f183d779ca956
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2019-01-14 14:37:09 +01:00
Mrozek, Michal
6c902faf0b Cleanup around Walker programming. 
- remove redundant methods.
- remove redundant parameters.
- Simplify the logic of programWalker

Change-Id: I6112bb19fd0008530f5e5510238bf42e669379b7
 2019-01-14 10:12:38 +01:00
Mrozek, Michal
15bfdc101f Refactor programWalker. 
- Pass variables computed in upper layers via args.
- declare variables prior to functions.
- Change some names for better verbosity.

Change-Id: I603b9ada1f62a08de5ac0fce177ccd840f2ce98c
 2019-01-14 09:02:14 +01:00
Dunajski, Bartosz
8ae7de7b0e Create HardwareContext only when osContext is available 
Change-Id: I8bcf2cb20f0e1e6b9da98b477f5be206407a7a57
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-01-13 15:12:07 +01:00
Artur Harasimiuk
c38ba275d6 remove unused files 
file is not used at all - removing it

Change-Id: I6be19c61688ac400cde278305ab77b19f3dbf5bf
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
 2019-01-11 23:13:34 +01:00
Pawel Wilma
14e8fdd8f8 Fix for incorrect timestamp offset calculation in event profiling info 
Change-Id: I634c29daf4734b24e4075542dc6550c531977f0a
Signed-off-by: Pawel Wilma <pawel.wilma@intel.com>
 2019-01-11 16:39:05 +01:00
Dunajski, Bartosz
23b7b9a8a8 Make local copy of EventsWaitlist for CommandComputeKernel 
Change-Id: Ibbdfc6732fc254e73407605ebb26f88e5552c0e8
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-01-11 15:05:42 +01:00
Piotr Fusik
30dd15144c Add debug variable to disable host ptr tracking. 
Change-Id: Ifc866e06a4519e7590d40d8ad136147ecc80225d
 2019-01-11 12:06:52 +01:00
Hoppe, Mateusz
64ff9d30b7 Fixes for misaligned hostPtr enqueueReadWrite 
- use getGpuAddress for BuiltinOpParams
- fix read/writeImage

Change-Id: I2e6e9a1d91871fa9f22851f31eb5a7b337b5aecc
 2019-01-11 09:14:47 +01:00
Kowalczuk, Jakub
3c59bae5a4 Set NoGfxMemory in Gmm Constructor 
Change-Id: Iee36e6de82db12c84970e68e1c940b67ec957eab
 2019-01-11 08:11:22 +01:00
Mrozek, Michal
ef73bb8c11 Move Walker specific code to dedicated method. 
- move cache flushes after the Walker.

Change-Id: I58c5e76bad22ac42da2c466ef008ef5bf96df077
 2019-01-10 16:36:56 +01:00
Mateusz Jablonski
ec18d7fee6 Add debug break in case of no synchronization between devices 
Change-Id: If10ed848725b1101d67dbbac318f0aa283db1e2f
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2019-01-10 13:23:06 +01:00
Dunajski, Bartosz
6ea2d8c2a9 Extract creating aub file name to separate function 
Change-Id: Ie0506f1847684cc3aabd8bee153c944b2f49bdb8
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-01-09 20:45:04 +01:00
Hoppe, Mateusz
3381dc258b Fix for ReadWriteBufferRect with misaligned hostPtr 
Change-Id: I026f3512e6501b7e3a4cd5b9b6e9010a0b3b8a72
 2019-01-09 14:57:25 +01:00
Kamil Diedrich
8feab5e570 Remove commandStreamReceiver lock in clSetUserEventStatus 
Change-Id: I9a095e2b34aef33f8c8fb210445727dec3aefbfa
 2019-01-09 12:46:45 +01:00
Mrozek, Michal
a58a897bf3 Move unrecoverable prior to pointer deference. 
Change-Id: I35c33de88fd4c2286a678f250df3ff9b3b495097
 2019-01-09 10:24:18 +01:00
Hoppe, Mateusz
cbc4d349a8 Do not align down pointer passed to hostPtr allocation 
- do not align up hostPtr allocation size
- align BaseAddress programmed in SurfaceState to DWORD

Change-Id: Ic6d02e53fd13dda881f8eb845a131bffe4deb45c
 2019-01-08 21:21:34 +01:00
Mrozek, Michal
acc5e87b40 Change CL_MEM_USE_HOST_PTR buffer allocation scheme. 
- Choose BUFFER type if local memory is present.
- add CL_MEM_FORCE_SHARED_PHYSICAL_MEMORY_INTEL for allocations that
require host pointer storage.

Change-Id: Ifd3c74800cd53a2a9bb2171212a47ef5bcffe2a1
 2019-01-08 16:24:10 +01:00
Mateusz Jablonski
b5d9ed77a6 Correct destruction logic of shared allocations 
wait for all os contexts that used the allocation
when os context is not ready then flush related command stream receiver

Change-Id: I5fb2c16c1d398c59fbd02e32ebbbb9254583244e
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2019-01-08 14:32:21 +01:00
Mrozek, Michal
1ce3898400 Improve checkMemory validation. 
- check that proper flags are passed if hostPtr is presented.
- fix a bug in buffer fixture.
- fix some bugs in other tests.

Change-Id: If708fd06598e5f3d8a94b3e24fb83f689f6b52c7
 2019-01-08 11:44:37 +01:00
Milczarek, Slawomir
ea028d2a9b Moved TBX and AUB CSR members to SimulatedCommonHw CSR 
Change-Id: I4b49b0cf886c70127a9983dd1c9d7b15f7a45b7a
 2019-01-08 09:39:28 +01:00
Mrozek, Michal
5c9f8eee23 Change the type for CL_MEM_ALLOC_HOST_PTR buffers in 64 bit. 
Change-Id: Ic70d8bb3e172b80b7c20b570e5e307be460defce
 2019-01-08 09:08:00 +01:00
Mateusz Jablonski
aee69779fa Minor renaming in a scope of multi os context allocations: 
shareable -> multiOsContextCapable
resetTaskCount -> releaseUsageInOsContext
resetResidencyTaskCount -> releaseResidencyInOsContext
isUsedByContext -> isUsedByOsContext

Change-Id: If824246a0e393b962bd12f8c63d429a0fcfcda25
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2019-01-07 11:42:43 +01:00
Milczarek, Slawomir
9083761dce Add AUBFillBuffer test with concurrent execution on CS 
Change-Id: Ia01614a9763ff67d27ed68c46a5ae1b9f7dd0ee8
 2019-01-04 17:04:55 +01:00
Filip Hazubski
7e3884e22d Add clEnqueueVerifyMemory API 
Change-Id: I15a514b14b9efdaeb182c7abd98b8e236932d50f
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2019-01-04 08:30:02 +01:00
Napiatek, Henryk J
f7e0decf44 Improve capturing profiling timestamps 
Change-Id: I3a568afb664cae5c871e53de2c36fc8be65a4bdf
 2019-01-03 12:35:56 +01:00
Milczarek, Slawomir
ba2b8f05fc AubManager to accept memory bank size in bytes 
Change-Id: Ie98cb7c0c0eaf93c9a2312aa87428173421609a9
 2019-01-02 15:56:36 +01:00
Filip Hazubski
9d9b11734d Enhance processing Queue properties 
Change-Id: I53ab00bdbfb6b11a7d9fdcaec816eead625ae737
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2019-01-02 14:52:02 +01:00
Venevtsev, Igor
73a63c7689 Fix Read/WriteBuffer for unaligned offsets 
Change-Id: I08d33e80243f41174f4629c8a611e286629d2e10
 2018-12-31 14:50:07 +01:00
Hoppe, Mateusz
a31c446d9f Allocate non USE_HOST_PTR and non-buffer images in preferred pool. 
Change-Id: Ia486c7b32932202162d6587d06dc61023e38fff6
 2018-12-31 14:37:44 +01:00
Hoppe, Mateusz
e195b0e380 Initialize TBX stream only when hardwareContext is not created 
Change-Id: I05d8c5c395cc342ea699333dd59966913f9a98df
 2018-12-31 12:14:55 +01:00
Mateusz Jablonski
56eced2faa Don't allow 32bit allocation for SVM allocation type 
Change-Id: I2fbae4ce3be956a386bdc22c9b129f37d75c8e8f
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2018-12-31 10:43:08 +01:00
Kamil Diedrich
fad2f8dbd1 Change auxTranslationDirectory 
Change-Id: I5d433d340e945b799dbec25a22fd610312f00c0a
 2018-12-28 16:46:42 +01:00
Hoppe, Mateusz
694b643df1 Add useLocalMemory flag to ImageInfo 
Change-Id: I664f9e17c0c480c2b7b2b34dcfaefa7929b9ddfe
 2018-12-28 13:53:53 +01:00
Adam Cetnerowski
a2a4bcc33d Correct extension string typo 
Change-Id: I1305a0251b06e8601e78a9b8774c285e035ff28d
 2018-12-27 12:36:49 +01:00
Dunajski, Bartosz
8029639898 Pin allocation with specific DrmContextId at creation time 
Change-Id: Ic132fb70b1da2cf3b7c70ab899822705adb83edc
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2018-12-27 09:35:58 +01:00
Katarzyna Cencelewska
ebd0889216 Fix for load function wglMakeCurrent 
Load from glLibrary instead of wglLibrary

Change-Id: I426209407ddd9efdad0b26b47ff02382ccb7f5ab
 2018-12-26 21:52:09 +01:00
Artur Harasimiuk
b5f443edc0 Revert commit cc1f4bed60. 
This reverts commit cc1f4bed60.
Revert "Revert "Use GPU instead of CPU address in programming commands
for HwTim(...)""

Change-Id: Iff122612bb46ba80bcc70b07b2609bfd5f0b9653
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
 2018-12-21 13:25:49 +01:00
Artur Harasimiuk
b2c1d68a91 Revert "Revert "Revert "Fix Read/WriteBuffer for unaligned offsets""" 
This reverts commit f6757c02a4.

Change-Id: I239528e7588dc9766b10a7ce7e517d6b2cdd6375
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
 2018-12-21 08:57:45 +01:00
Kai Chen
1251ccc3c6 Allocate CPU address for Linux internal 32bit allocator base 
The internal 32bit allocator sometimes need CPU address to access
or store data when it is in reduced address space scenario.

Change-Id: I6c0b3f9703ae3e124249b41ad7d81f03ad93ad17
Signed-off-by: Kai Chen <kai.chen@intel.com>
 2018-12-21 07:11:48 +01:00