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[RISCV] Add PseudoCCADDIW/SLLW/SRLW/SRAW/SLLIW/SRLIW/SRAIW to RISCVOptWInstrs.

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These can be treated simlarly to PseudoCCADDW/SUBW.
This commit is contained in:
Craig Topper
2023-11-13 22:37:50 -08:00
parent d3876c58a8
commit c14602b318
1 changed files with 9 additions and 2 deletions
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11
llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
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@@ -482,9 +482,16 @@ static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST,
break;
case RISCV::PseudoCCADDW:
case RISCV::PseudoCCADDIW:
case RISCV::PseudoCCSUBW:
// Returns operand 4 or an ADDW/SUBW of operands 5 and 6. We only need to
// check if operand 4 is sign extended.
case RISCV::PseudoCCSLLW:
case RISCV::PseudoCCSRLW:
case RISCV::PseudoCCSRAW:
case RISCV::PseudoCCSLLIW:
case RISCV::PseudoCCSRLIW:
case RISCV::PseudoCCSRAIW:
// Returns operand 4 or an ADDW/SUBW/etc. of operands 5 and 6. We only
// need to check if operand 4 is sign extended.
if (!AddRegDefToWorkList(MI->getOperand(4).getReg()))
return false;
break;