ACPI: Add broken-cd property for SDMMC

Missed this change. The Windows driver needs to be made aware that the internal card detect register cannot be trusted. But card detection still works there, because sdport keeps track of the state based on the GPIO interrupt. Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
FydetabDuo: Disable SD card detection
2026-01-12 23:24:44 +08:00 · 2024-07-11 04:03:19 +03:00 · 2024-07-10 20:18:00 +03:00 · 2024-07-10 19:41:15 +03:00 · 2024-07-09 05:50:16 +03:00 · 2024-07-09 05:22:31 +03:00
234 changed files with 17868 additions and 2656 deletions
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -25,10 +25,14 @@ jobs:
        PLATFORM:
          - rock-5b
          - rock-5a
+          - rock-5-itx
          - orangepi-5
          - orangepi-5plus
          - indiedroid-nova
+          - fydetab-duo
          - roc-rk3588s-pc
+          - itx-3588j
+          - aio-3588q
          - station-m3
          - r58x
          - r58-mini
@@ -41,7 +45,7 @@ jobs:
        CONFIGURATION: ${{ fromJSON(format('[{0}]', inputs.build-configs || '"Debug"')) }}
    steps:
      - name: Checkout
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4
        with:
          submodules: recursive

@@ -79,19 +83,23 @@ jobs:
      - name: Build platform
        shell: bash
        run: |
-          export BUILD_FLAGS="-D SECURE_BOOT_ENABLE=TRUE"
-          export DEFAULT_KEYS="-D DEFAULT_KEYS=TRUE \
-                               -D PK_DEFAULT_FILE=keys/pk.cer \
-                               -D KEK_DEFAULT_FILE1=keys/ms_kek.cer \
-                               -D DB_DEFAULT_FILE1=keys/ms_db1.cer \
-                               -D DB_DEFAULT_FILE2=keys/ms_db2.cer \
-                               -D DBX_DEFAULT_FILE1=keys/arm64_dbx.bin"
+          export EDK2_SECUREBOOT_FLAGS=" \
+              -D DEFAULT_KEYS=TRUE \
+              -D PK_DEFAULT_FILE=keys/pk.cer \
+              -D KEK_DEFAULT_FILE1=keys/ms_kek.cer \
+              -D DB_DEFAULT_FILE1=keys/ms_db1.cer \
+              -D DB_DEFAULT_FILE2=keys/ms_db2.cer \
+              -D DBX_DEFAULT_FILE1=keys/arm64_dbx.bin \
+              -D SECURE_BOOT_ENABLE=TRUE"

-          ./build.sh --device ${{matrix.PLATFORM}} --release ${{matrix.CONFIGURATION}} --build-flags="${BUILD_FLAGS} ${DEFAULT_KEYS}"
+          export EDK2_BUILD_FLAGS=" \
+              ${EDK2_SECUREBOOT_FLAGS}"
+
+          ./build.sh --device ${{matrix.PLATFORM}} --release ${{matrix.CONFIGURATION}} --edk2-flags "${EDK2_BUILD_FLAGS}"
          mv RK3588_NOR_FLASH.img ${{matrix.PLATFORM}}_UEFI_${{matrix.CONFIGURATION}}_${{steps.get_version_tag.outputs.version}}.img

      - name: Upload artifact
-        uses: actions/upload-artifact@v3
+        uses: actions/upload-artifact@v4
        with:
          name: ${{matrix.PLATFORM}} UEFI ${{matrix.CONFIGURATION}} image
          path: ./*.img
--- a/.github/workflows/release.yml
+++ b/.github/workflows/release.yml
@@ -17,20 +17,12 @@ jobs:
      contents: write
    steps:
      - name: Download all workflow run artifacts
-        uses: actions/download-artifact@v3
+        uses: actions/download-artifact@v4

      - name: Create release
-        uses: softprops/action-gh-release@v1
+        uses: softprops/action-gh-release@v2
        with:
          draft: true
          prerelease: false
          files: "*/*Release*.img"
          fail_on_unmatched_files: true
-          generate_release_notes: true
-          append_body: true
-          body: |
-            ## Usage
-            Flash the board-specific image to SPINOR with rkdevtool / rkdeveloptool or to an EMMC / SD card.
-            If your board is not yet supported, using a similar image may work but beware of potential issues.
-
-            Debug builds can be found in the artifacts of the workflow run for this release.
--- a/.gitmodules
+++ b/.gitmodules
@@ -10,3 +10,7 @@
 [submodule "misc/rkbin"]
 	path = misc/rkbin
 	url = https://github.com/rockchip-linux/rkbin.git
+[submodule "arm-trusted-firmware"]
+	path = arm-trusted-firmware
+	url = https://github.com/worproject/arm-trusted-firmware
+	branch = rk3588
--- a/README.md
+++ b/README.md
@@ -1,12 +1,16 @@
 # EDK2 UEFI firmware for Rockchip RK3588 platforms
 This repository contains an UEFI firmware implementation based on EDK2 for various RK3588 boards.

-## Supported platforms
- [Radxa ROCK 5B](https://wiki.radxa.com/Rock5/hardware/5b)
- [Radxa ROCK 5A](https://wiki.radxa.com/Rock5/hardware/5a)
+# Supported platforms
+- [Radxa ROCK 5B](https://radxa.com/products/rock5/5b/)
+- [Radxa ROCK 5A](https://radxa.com/products/rock5/5a/)
+- [Radxa ROCK 5 ITX](https://radxa.com/products/rock5/5itx/)
 - [Orange Pi 5](http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-5.html)
 - [Orange Pi 5 Plus](http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-5-plus.html)
 - [ameriDroid Indiedroid Nova](https://indiedroid.us)
+- [Fydetab Duo](https://fydetabduo.com/)
+- [Firefly AIO-3588Q](https://en.t-firefly.com/product/industry/aio3588q)
+- [Firefly ITX-3588J](https://en.t-firefly.com/product/industry/itx3588j)
 - [Firefly ROC-RK3588S-PC](https://en.t-firefly.com/product/industry/rocrk3588spc)
 - [StationPC Station M3](https://www.stationpc.com/product/stationm3)
 - [Mekotronics R58X](https://www.mekotronics.com/h-pd-75.html)
@@ -18,8 +22,29 @@ This repository contains an UEFI firmware implementation based on EDK2 for vario
 - [FriendlyELEC NanoPi R6S](https://wiki.friendlyelec.com/wiki/index.php/NanoPi_R6S)
 - [Hinlink H88K](http://www.hinlink.com)

-## Supported peripherals
-Applicable to all platforms unless otherwise noted.
+# Supported OSes
+## In ACPI mode
+| OS | Version | Tested/supported hardware | Notes |
+| --- | --- | --- | --- |
+| Windows | 11 | [Status](https://github.com/worproject/Rockchip-Windows-Drivers#hardware-support-status) ||
+| NetBSD | 10 | Display, UART, USB, PCIe (incl. NVME), SATA, eMMC, GMAC Ethernet ||
+| VMware ESXi Arm Fling | >= 1.12 | Display, USB | * PCIe devices will hang at boot, need to disable in settings or leave the ports empty.<br>* GMAC Ethernet gets detected but does not work. |
+| Linux | tested Ubuntu 22.04, kernel 5.15.0-75-generic | Display, UART, USB, PCIe (incl. NVME & Ethernet), SATA | For full hardware functionality, use a kernel with RK3588 support and switch to Device Tree mode. |
+
+> [!NOTE]
+> ACPI support is only being developed and tested against Windows. There are no plans to further improve functionality for other OSes. Consider using Device Tree instead (where applicable, for instance Linux).
+
+## In Device Tree mode
+| OS | Version | Tested/supported hardware | Notes |
+| --- | --- | --- | --- |
+| Rockchip SDK Linux | 5.10 legacy, tested with [Armbian rk3588-live-iso](https://github.com/amazingfate/rk3588-live-iso) | Platform-dependent, most peripherals work. | If using a different kernel, see [Device Tree configuration](#device-tree-configuration). |
+
+# Supported peripherals in UEFI
+
+> [!NOTE]
+> Applicable to all platforms unless otherwise noted.
+>
+> Only devices relevant to the firmware itself (not OS) are listed below.

 | Device | Status | Notes |
 | --- | --- | --- |
@@ -29,9 +54,9 @@ Applicable to all platforms unless otherwise noted.
 | SATA                               | 🟢 Working     | |
 | SD/eMMC                            | 🟢 Working     | |
 | HDMI output                        | 🟡 Partial     | Single display with mode limited at 1080p 60 Hz |
-| DisplayPort output (USB-C)         | 🟡 Partial     | Mode fixed at 1080p 60 Hz, only works in one orientation of the Type-C port. |
+| DisplayPort output (USB-C)         | 🟡 Partial     | Mode fixed at 1080p 60 Hz, only works in one orientation of the Type-C port. Some displays may not work regardless. |
 | eDP output                         | 🟡 Partial     | Disabled, requires manual configuration depending on the platform and panel. |
-| DSI output                         | 🔴 Not working | |
+| DSI output                         | 🟢 Working     | Only enabled on Fydetab Duo. Requires manual configuration depending on the platform and panel. |
 | GMAC Ethernet                      | 🔴 Not working | Only brought-up for OS usage |
 | Realtek PCIe Ethernet              | 🟢 Working     | Some platforms don't have MAC addresses set, networking may not work in that case. |
 | UART                               | 🟢 Working     | UART2 console available at 1500000 baud rate |
@@ -41,45 +66,28 @@ Applicable to all platforms unless otherwise noted.
 | PWM                                | 🟢 Working     | |
 | SPI NOR Flash                      | 🟢 Working     | |
 | HYM8563 real-time clock            | 🟢 Working     | |
+| RNG                                | 🟢 Working     | |
 | Cooling fan                        | 🟢 Working     | Supported on most platforms. Fan connector where present, otherwise available at the GPIO header for 3-pin PWM fans (do *not* connect 2-pin fans there!):<br>* Orange Pi 5: `GPIO4_B2`<br>* Indiedroid Nova: `GPIO4_B4` |
 | Status LED                         | 🟢 Working     | |
 | Voltage regulators (RK806, RK860)  | 🟢 Working     | |
 | FUSB302 USB Type-C Controller      | 🔴 Not working | Required for PD negotiation and connector orientation switching |

-## Supported OSes
-### In ACPI mode
-| OS | Version | Tested/supported hardware | Notes |
-| --- | --- | --- | --- |
-| Windows | 10 (1904x), 11 | [Status](https://github.com/worproject/Rockchip-Windows-Drivers#hardware-support-status) ||
-| NetBSD | 10 | Display, UART, USB, PCIe (incl. NVME), SATA, eMMC, GMAC Ethernet ||
-| VMware ESXi Arm Fling | >= 1.12 | Display, USB | * PCIe devices will hang at boot, need to disable in settings or leave the ports empty.<br>* GMAC Ethernet gets detected but does not work. |
-| Linux | tested Ubuntu 22.04, kernel 5.15.0-75-generic | Display, UART, USB, PCIe (incl. NVME & Ethernet), SATA | For full hardware functionality, use a kernel with RK3588 support and switch to Device Tree mode. |
-
-#### Additional limitations when using ACPI
-* Devices behind PCIe switches do not work (e.g. the two NICs on Mixtile Blade 3).
-* GMAC is limited to Gigabit speed (i.e. no 10/100).
-
-### In Device Tree mode
-| OS | Version | Tested/supported hardware | Notes |
-| --- | --- | --- | --- |
-| Rockchip SDK Linux | 5.10 legacy, tested with [Armbian rk3588-live-iso](https://github.com/amazingfate/rk3588-live-iso) | Platform-dependent, most peripherals work. | If using a different kernel, see [Device Tree configuration](#device-tree-configuration). |
-
-## Getting started
-### 1. Requirements
+# Getting started
+## 1. Requirements
 * One of the [supported devices](#supported-platforms).
-* Either SPI NOR flash (included with some devices), SD card or eMMC to store the firmware on.
+* Storage for the firmware: SPI NOR flash (included with some devices), SD card or eMMC.
 * Quality power supply that can provide at least 15 W. Depending on the peripherals you use, more may be needed.

  Note: on Mixtile Blade 3, a fixed voltage *higher than* 5V must be supplied. The board cannot power any external peripherals if the input voltage is just 5V. USB-PD negotiation is not supported by firmware.
 * HDMI or DisplayPort (USB-C) screen capable of at least 1080p 60Hz.
 * Optionally, if display is not available or for debugging purposes, an UART adapter capable of 1500000 baud rate (e.g. USB CH340, CP2104).

-### 2. Download the firmware image
+## 2. Download the firmware image
 The latest version can be obtained from <https://github.com/edk2-porting/edk2-rk3588/releases>.

 If your platform is not yet supported, using an image meant for another device is **not** recommended. Although they are generally similar, voltage setup can happen to be different and you may risk damaging the board. External peripherals are unlikely to work either.

-### 3. Flash the firmware
+## 3. Flash the firmware
 UEFI can be flashed to either a SPI NOR flash, SD card or eMMC module:
 * For removable SD or eMMC (easiest), you can simply use balenaEtcher, RPi Imager or dd.
 * For SPI NOR or soldered eMMC, instructions can be found at: <https://wiki.radxa.com/Rock5/install/spi>.
@@ -92,37 +100,31 @@ If you wish to have both UEFI and an OS on the same SD or eMMC device: flash UEF

 Note: Using SPI NOR (if present) is recommeded, as it leaves the other storage options free for other purposes. Additionally, SD/eMMC will limit the firmware's ability to access its own storage (variable store) when an OS is running. This feature is mostly used by OS installers to create the boot menu options, it is not mandatory.

-### 4. Connect peripherals and power on the device
+## 4. Connect peripherals and power on the device
 If the flashing process has been done correctly, you should see the status LED blinking (if present), and shortly after, the platform's boot logo with a progress bar at the bottom on the connected display.

 At this stage, you can press <kbd>Esc</kbd> to enter the firmware setup, <kbd>F1</kbd> to launch the UEFI Shell, or, provided you also have an UEFI bootloader/app on a storage device, you can let the system automatically run that, which is the default behavior if no action is taken.

-Check the [Supported peripherals](#supported-peripherals) and [Supported OSes](#supported-oses-with-acpi) sections to see what's currently possible with this firmware.
+Check the [Supported OSes](#supported-oses) and [Supported peripherals in UEFI](#supported-peripherals-in-uefi) sections to see what's currently possible with this firmware.

 Also check the configuration options described below, some of which may need to be changed depending on the OS used.

 If you experience any issues, please see the [Troubleshooting](#troubleshooting) section.

-## Configuration settings
-The UEFI provides a few configuration options, like CPU frequency, PCIe/SATA selection for an M.2 port, fan control, etc. These can be viewed and changed using both the UI configuration menu (under `Device Manager` -> `Rockchip Platform Configuration`), as well as the UEFI Shell.
+# Configuration settings
+The UEFI provides a few configuration options, like CPU frequency, PCIe/SATA selection for an M.2 port, fan control, etc. These can be viewed and changed using the UI configuration menu (under `Device Manager` -> `Rockchip Platform Configuration`).

-Configuration through the user interface is fairly straightforward and help information is provided on the right side of the menu.
+Configuration through the user interface is fairly straightforward and help/navigation information is provided around the menus.

-Configuration through the UEFI shell is more advanced and mostly useful for scripts. See [Setting configuration options via the shell](#setting-configuration-options-via-the-shell).
-
-### Tips
+## Tips
 * CPU clocks are set to 816 MHz (boot default) on platforms without a cooling fan included. If you have adequate cooling, go to the configuration menu -> `CPU Performance` and set all Cluster Presets to `Maximum`.

-* If you only wish to boot non-Windows OSes in ACPI mode, go to the configuration menu -> `ACPI / Device Tree` and set `USB 2.0 Support` to `Enabled`, in order to get maximum speed from USB 2.0 ports.
-
-  Booting Windows with this option enabled will cause it to crash.
-
-### Device Tree configuration
+## Device Tree configuration
 For rich Linux support, it is recommended to enable Device Tree mode. You can do so by going to the configuration menu -> `ACPI / Device Tree` and setting `Config Table Mode` to `Device Tree`.

 By default, the firmware installs a [DTB compatible with (most) Rockchip SDK Linux 5.10 legacy kernel variants](https://github.com/edk2-porting/edk2-rk3588/tree/master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree).

-#### Custom Device Tree Blob (DTB) override and overlays
+### Custom Device Tree Blob (DTB) override and overlays
 It is also possible to provide a custom DTB and overlays. To enable this, go to the configuration menu -> `ACPI / Device Tree` and set `Support DTB override & overlays` to `Enabled`.

 The firmware will now look for overrides in the partition of a selected boot option / OS loader. In most cases this will be the first FAT32 EFI System Partition.
@@ -140,20 +142,23 @@ The paths above are relative to the root of the file system. That is, the `dtb`
 `<PLATFORM-DT-NAME>` can be:
 | Name                                    | Platform                      |
 | --------------------------------------- | ----------------------------- |
+| `rk3588-rock-5b`                        | ROCK 5B                       |
+| `rk3588s-rock-5a`                       | ROCK 5A                       |
+| `rk3588-rock-5-itx`                     | ROCK 5 ITX                    |
+| `rk3588s-orangepi-5`                    | Orange Pi 5                   |
+| `rk3588-orangepi-5-plus`                | Orange Pi 5 Plus              |
 | `rk3588s-9tripod-linux`                 | Indiedroid Nova               |
+| `rk3588-firefly-aio-3588q`              | Firefly AIO-3588Q             |
+| `itx-3588j`                             | Firefly ITX-3588J             |
 | `roc-rk3588s-pc`                        | ROC-RK3588S-PC / Station M3   |
+| `rk3588-blueberry-edge-v12-linux`       | R58X (v1.2)                   |
+| `rk3588-blueberry-minipc-linux`         | R58 Mini                      |
+| `rk3588s-khadas-edge2`                  | Edge2                         |
+| `rk3588-blade3-v101-linux`              | Blade 3                       |
 | `rk3588-nanopc-t6`                      | NanoPC T6                     |
 | `rk3588s-nanopi-r6c`                    | NanoPi R6C                    |
 | `rk3588s-nanopi-r6s`                    | NanoPi R6S                    |
 | `rk3588-hinlink-h88k`                   | H88K                          |
-| `rk3588s-khadas-edge2`                  | Edge2                         |
-| `rk3588-blueberry-minipc-linux`         | R58 Mini                      |
-| `rk3588-blueberry-edge-v12-linux`       | R58X (v1.2)                   |
-| `rk3588-blade3-v101-linux`              | Blade 3                       |
-| `rk3588s-orangepi-5`                    | Orange Pi 5                   |
-| `rk3588-orangepi-5-plus`                | Orange Pi 5 Plus              |
-| `rk3588s-rock-5a`                       | ROCK 5A                       |
-| `rk3588-rock-5b`                        | ROCK 5B                       |

 In the absence of a custom base DTB override, the overlays are applied on top of the firmware-provided DTB.

@@ -165,7 +170,7 @@ If the custom base DTB is invalid, the firmware-provided one will be passed to t

 This entire process is logged to the [serial console](#advanced-troubleshooting). There's currently no other way to see potential errors.

-## Updating the firmware
+# Updating the firmware
 If the storage is only used for UEFI and nothing else, simply download the latest image and flash it as described in the [Getting started](#getting-started) section.

 If it is also used by an OS and has additional partitions, only part of the image needs to be applied. This can be done with the `dd` tool:
@@ -179,12 +184,16 @@ dd if=FIRMWARE.img of=DESTINATION bs=512 skip=64 seek=64 conv=notrunc

 Here we skip the GPT and copy the firmware starting at offset 0x8000 (`64` blocks * `512` bytes block size) until its end. See [Flash layout](#flash-layout) for more details.

-## Troubleshooting
-First of all, make sure your device can only possibly load the UEFI firmware and nothing else. U-Boot must not present on either SPI NOR, SD or eMMC, otherwise it could take precedence.
+# Troubleshooting
+
+> [!IMPORTANT]
+> First of all, make sure your device can only possibly load the UEFI firmware and nothing else.
+>
+> **U-Boot must not present on either SPI NOR, SD or eMMC, otherwise it could take precedence and cause hidden issues.**

 Below you can find some basic debugging information. If none of this helps, please see the [Advanced troubleshooting](#advanced-troubleshooting) section.

-### Meaning of the Status LED
+## Meaning of the Status LED
 If your device has an activity LED, the firmware will blink it in different patterns to indicate the current system status.

 1. Immediately after power on, the LED should start pulsing quickly. This indicates that the firmware is initializing.
@@ -199,8 +208,8 @@ If the LED:

  Note that it is only expected to stop as described at point 3) above.

-### Common issues
-#### Nothing shows up on the screen
+## Common issues
+### Nothing shows up on the screen
 Make sure you've flashed the firmware correctly and that it is the version designed for your device. In most cases this is the culprit.

 Assuming the firmware loads fine:
@@ -210,12 +219,21 @@ Assuming the firmware loads fine:

 If you are not able to get any display output, the only way to interact with UEFI is via the [serial console](#advanced-troubleshooting).

-#### USB 3 devices do not work
+### Configuration settings do not get saved
+This has been observed in cases where U-Boot was still present on another boot device (SD, eMMC or SPI NOR).  This is not a supported scenario. The solution is to unplug or erase devices that may have other firmware on them.
+
+What's happening:
+1. Board loads U-Boot from a storage device that has higher priority (let's say eMMC).
+2. That U-Boot image in turn loads UEFI and its settings from another device with lower priority (let's say SD).
+3. UEFI cannot accurately determine to which device it belongs. The parameter used to verify this points to eMMC (U-Boot), while UEFI actually got loaded from SD.
+4. Consequently, UEFI mistakenly saves the user settings to eMMC. On reboot, U-Boot loads UEFI and the original/unchanged settings from SD and the cycle repeats.
+
+### USB 3 devices do not work
 * Try a different port.
 * If you're using USB-C, 3.0 devices will only work in one orientation of the connector. Check both.
-* Make sure the power supply and cable are good
+* Make sure the power supply and cable are good.

-#### Networking does not work
+### Networking does not work
 * Only Realtek PCIe and USB controllers are supported. Native Gigabit provided by RK3588 isn't.

 * Some boards with Realtek NICs do not have a MAC address set at factory and will show-up as being all zeros in UEFI, possibly preventing the adapter from obtaining an IP address.
@@ -258,7 +276,7 @@ If you are not able to get any display output, the only way to interact with UEF

  **Note:** the number of eFuses is limited, thus MAC addresses can only be changed a few times.

-### Advanced troubleshooting
+## Advanced troubleshooting
 The firmware will log detailed information to the serial console when using a debug version. See the [release notes](https://github.com/edk2-porting/edk2-rk3588/releases) for details on how to obtain this version.

 1. The debug image needs to be flashed in place of the existing one.
@@ -269,18 +287,18 @@ The firmware will log detailed information to the serial console when using a de

 4. Power on the device.

-You should be able to see a lot of debug messages being printed. If that's not the case, double check the connections (swap RX/TX), make sure the adapter is functional and configured correctly.
+You should be able to see many debug messages being printed to the console. If that's not the case, double check the connections (swap RX/TX), make sure the adapter is functional and configured correctly.

 The logs should give an insight of what's going on. If you need help analyzing them, feel free to open an issue ticket.

-## Reporting issues
+# Reporting issues
 You can open issues related to UEFI at <https://github.com/edk2-porting/edk2-rk3588/issues>.

 Please include as many details as possible: expected behavior, what actually happens, steps to reproduce, [serial logs](#advanced-troubleshooting), etc.

 Also check the existing issues in case yours might be already reported.

-## Building
+# Building
 The firmware can only be built on Linux currently. For Windows use WSL.

 1. Install required packages:
@@ -308,9 +326,9 @@ The firmware can only be built on Linux currently. For Windows use WSL.

 If you get build errors, it is very likely that you're still missing some dependencies. The list of packages above is not complete and depending on the distro you may need to install additional ones. In most cases, looking up the error messages on the internet will point you at the right packages.

-## Notes
+# Notes

-### Flash layout
+## Flash layout
 | Address    | Size       | Desc                  | File                   |
 | ---------- | ---------- | --------------------- | ---------------------- |
 | 0x00000000 | 0x00004400 | GPT Table             | rk3588_spi_nor_gpt.img |
@@ -324,7 +342,7 @@ The variable store is not included in the flash image, in order to prevent overw

 The firmware expects these exact offsets, do not change them.

-### Memory Map
+## Memory Map
 | Address    | Size       | Desc                  | File                |
 | ---------- | ---------  | --------------------- | ------------------- |
 | 0x00040000 |            | ATF                   | bl31_0x00040000.bin |
@@ -336,98 +354,6 @@ The firmware expects these exact offsets, do not change them.
 | 0x08400000 |            | OP-TEE                | bl32.bin            |
 | 0xff100000 |            | ATF (PMU_MEM)         | bl31_0xff100000.bin |

-### Setting configuration options via the shell
-To configure using the UEFI Shell, use `setvar` command to read/write the UEFI variables with GUID = `10f41c33-a468-42cd-85ee-7043213f73a3`.
-
-The syntax to read a setting is:
-```
-setvar <NAME> -guid 10f41c33-a468-42cd-85ee-7043213f73a3
-```
-
-The syntax to write a setting is:
-```
-setvar <NAME> -guid 10f41c33-a468-42cd-85ee-7043213f73a3 -bs -rt -nv =<VALUE>
-```
-`VALUE` must be in hexadecimal.
-
-For string-type settings, the syntax to write is:
-```
-setvar <NAME> -guid 10f41c33-a468-42cd-85ee-7043213f73a3 -bs -rt -nv =L"<VALUE>" =0x0000
-```
-
-### CPU Performance
-#### Cluster clocks / voltages
-| Variable                          |    NAME                            |  VALUE                       |
-| --------------------------------- |----------------------------------- |----------------------------- |
-| CPU`x` Clock Preset               | `CpuPerf_CPUxClusterClockPreset`   | Boot default = `0x00000000`<br> Min = `0x00000001`<br> Max = `0x00000002`<br> Custom = `0x00000003` |
-| CPU`x` Custom Clock Preset (MHz)  | `CpuPerf_CPUxClusterClockCustom`   | Hex numeric option, 4-bytes<br> See below. |
-| CPU`x` Voltage Mode               | `CpuPerf_CPUxClusterVoltageMode`   | Auto = `0x00000000` (default)<br> Custom = `0x00000001`|
-| CPU`x` Custom Voltage (uV)        | `CpuPerf_CPUxClusterVoltageCustom` | Hex numeric value, 4-bytes<br> See below. |
-
-`x` can be :
-* `L` for LITTLE cluster
-* `B01` for big cluster #0
-* `B23` for big cluster #1
-
-`CpuPerf_CPUxClusterClockCustom` can have one of the following values:
-* All clusters: `408000000`, `600000000`, `816000000`, `1008000000`, `1200000000`, `1416000000`, `1608000000`, `1800000000`
-* Big cluster additional clocks: `2016000000`, `2208000000`, `2256000000`, `2304000000`, `2352000000`, `2400000000`
-
-`CpuPerf_CPUxClusterVoltageCustom` is the cluster voltage in microvolts. Min: `500000`, Max: `1500000`.
-Default value depends on cluster type.
-
-### PCIe/SATA/USB Combo PIPE PHY
-| Variable    |    NAME         |  VALUE                             |
-| ----------- | --------------- | ---------------------------------- |
-| PHY #0 Mode | `ComboPhy0Mode` | Unconnected = `0x00000000`<br> PCIe = `0x00000001`<br> SATA = `0x00000002` |
-| PHY #1 Mode | `ComboPhy1Mode` | Unconnected = `0x00000000`<br> PCIe = `0x00000001`<br> SATA = `0x00000002` |
-| PHY #2 Mode | `ComboPhy2Mode` | Unconnected = `0x00000000`<br> PCIe = `0x00000001`<br> SATA = `0x00000002`<br> USB3 = `0x00000003` |
-
-Default values and supported options depend on the platform. Check documentation and schematics for more details on PHY wiring.
-
-### USB/DP Combo PHY
-| Variable                      |    NAME              |  VALUE                            |
-| ----------------------------- | -------------------- | --------------------------------- |
-| PHY #0 USB 3 SuperSpeed State | `UsbDpPhy0Usb3State` | Enabled = `0x00000001`<br> Disabled = `0x00000000` |
-| PHY #1 USB 3 SuperSpeed State | `UsbDpPhy1Usb3State` | Enabled = `0x00000001`<br> Disabled = `0x00000000` |
-
-### PCI Express 3.0
-| Variable      |    NAME       |  VALUE                            |
-| ------------- | ------------- | --------------------------------- |
-| Support State | `Pcie30State` | Enabled = `0x00000001`<br> Disabled = `0x00000000` |
-
-### ACPI / Device Tree
-| Variable          |    NAME           |  VALUE                            |
-| ----------------- | ----------------- | --------------------------------- |
-| Config Table Mode | `ConfigTableMode` | ACPI = `0x00000001`<br> DeviceTree = `0x00000002`<br> Both = `0x00000003` |
-
-#### ACPI Configuration
-| Variable        |    NAME         |  VALUE                            |
-| --------------- | --------------- | --------------------------------- |
-| USB 2.0 Support | `AcpiUsb2State` | Enabled = `0x00000001`<br> Disabled = `0x00000000` |
-
-#### Device Tree Configuration
-| Variable                        |    NAME               |  VALUE                            |
-| ------------------------------- | --------------------- | --------------------------------- |
-| Support DTB override & overlays | `FdtSupportOverrides` | Enabled = `0x01`<br> Disabled = `0x00` |
-
-### Cooling fan
-| Variable        |    NAME           |  VALUE                            |
-| --------------- | ----------------- | --------------------------------- |
-| On-board Fan    | `CoolingFanState` | Enabled = `0x00000001`<br> Disabled = `0x00000000` |
-| Fan Speed (%)   | `CoolingFanSpeed` | Hex numeric value, 4-bytes<br> Percentage: 0-100 |
-
-**Examples:**
- To read the 'CPUL Clock Preset' setting :
-```
-setvar CpuPerf_CPULClusterClockPreset -guid 10f41c33-a468-42cd-85ee-7043213f73a3
-```
-
- To change the 'CPUL Clock Preset' setting to 'Maximum' :
-```
-setvar CpuPerf_CPULClusterClockPreset -guid 10f41c33-a468-42cd-85ee-7043213f73a3 -bs -rt -nv =0x00000002
-```
-
 ## Licenses
 Most of the UEFI code is licensed under the default EDK2 license, which is [BSD-2-Clause-Patent](https://github.com/tianocore/edk2/blob/master/License.txt).

@@ -440,7 +366,6 @@ The files in `edk2-rockchip-non-osi` are licensed as **GPL-2.0-only**.
 The license for some of the blobs in the `misc/rkbin/` directory can be found at: <https://github.com/rockchip-linux/rkbin/blob/master/LICENSE>. Note that it also contains binaries built from open-source projects such as U-Boot (SPL), Arm Trusted Firmware and OP-TEE, having a different license.

 ## Community
-* Radxa forum: <https://forum.radxa.com/t/windows-uefi-on-rock-5-mega-thread/12924>
 * Hack w/ Rockchip Telegram: <https://t.me/UEFIonRockchip>
 * Windows on R Discord: <https://discord.gg/vjHwptUCa3>

--- a/1
+++ b/1
--- a/build.sh
+++ b/build.sh
@@ -1,237 +1,252 @@
 #!/bin/bash

 function _help(){
-	echo "Usage: build.sh --device DEV"
-	echo
-	echo "Build edk2 for Rockchip RK35xx platforms."
-	echo
-	echo "Options: "
-	echo "	--device DEV, -d DEV:    build for DEV."
-	echo "	--all, -a:               build all devices."
-	echo "	--gui:                   Enable simple-init GUI."
-	echo "	--release MODE, -r MODE: Release mode for building, default is 'DEBUG', 'RELEASE' alternatively."
-	echo "	--toolchain TOOLCHAIN:   Set toolchain, default is 'GCC'."
-	echo " 	--skip-rootfs-gen:       skip generating SimpleInit rootfs to speed up building."
-	echo "	--clean, -C:             clean workspace and output."
-	echo "	--distclean, -D:         clean up all files that are not in repo."
-	echo "	--outputdir, -O:         output folder."
-	echo "	--build-flags:           flags appended to the EDK2 build process."
-	echo "	--help, -h:              show this help."
-	echo
-	exit "${1}"
+    echo
+    echo "Build EDK2 for Rockchip RK3588 platforms."
+    echo
+    echo "Usage: build.sh [options]"
+    echo
+    echo "Options:"
+    echo "  -d, --device DEV            Build for DEV, or 'all'."
+    echo "  -r, --release MODE          Release mode for building, default is 'DEBUG', 'RELEASE' alternatively."
+    echo "  -t, --toolchain TOOLCHAIN   Set toolchain, default is 'GCC'."
+    echo "  --open-tfa ENABLE           Use open-source TF-A submodule. Default: ${OPEN_TFA}"
+    echo "  -C, --clean                 Clean workspace and output."
+    echo "  -D, --distclean             Clean up all files that are not in repo."
+    echo "  --tfa-flags \"FLAGS\"         Flags appended to open TF-A build process."
+    echo "  --edk2-flags \"FLAGS\"        Flags appended to the EDK2 build process."
+    echo "  -h, --help                  Show this help."
+    echo
+    exit "${1}"
 }

-function _error(){ echo "${@}" >&2;exit 1; }
+function _error() { echo "${@}" >&2; exit 1; }

-MACHINE_TYPE=`uname -m`
+function _build_idblock() {
+    echo " => Building idblock.bin"
+    pushd ${WORKSPACE}

-# Fix-up possible differences in reported arch
-if [ ${MACHINE_TYPE} == 'arm64' ]; then
-	MACHINE_TYPE='aarch64'
-elif [ ${MACHINE_TYPE} == 'amd64' ]; then
-	MACHINE_TYPE='x86_64'
-fi
+    FLASHFILES="FlashHead.bin FlashData.bin FlashBoot.bin"
+    rm -f rk35*_spl_loader_*.bin idblock.bin rk35*_ddr_*.bin rk35*_usbplug*.bin UsbHead.bin ${FLASHFILES}

-function _build_idblock(){
-	echo " => Building idblock.bin"
-	pushd ${WORKSPACE}
-	FLASHFILES="FlashHead.bin FlashData.bin FlashBoot.bin"
-	rm -f rk35*_spl_loader_*.bin idblock.bin rk35*_ddr_*.bin rk35*_usbplug*.bin UsbHead.bin ${FLASHFILES}
+    DDRBIN_RKBIN=$(grep '^FlashData' ${ROOTDIR}/misc/rkbin/RKBOOT/${MINIALL_INI} | cut -d = -f 2-)
+    SPL_RKBIN=$(grep '^FlashBoot' ${ROOTDIR}/misc/rkbin/RKBOOT/${MINIALL_INI} | cut -d = -f 2-)

-	DDRBIN=$(grep '^FlashData' ${ROOTDIR}/misc/rkbin/RKBOOT/${MINIALL_INI} | cut -d = -f 2-)
-	SPL=$(grep '^FlashBoot' ${ROOTDIR}/misc/rkbin/RKBOOT/${MINIALL_INI} | cut -d = -f 2-)
+    DDRBIN="${ROOTDIR}/misc/rkbin/${DDRBIN_RKBIN}"

-	# Create idblock.bin
-	${ROOTDIR}/misc/tools/${MACHINE_TYPE}/mkimage -n rk3588 -T rksd -d ${ROOTDIR}/misc/rkbin/${DDRBIN}:${ROOTDIR}/misc/rkbin/${SPL} idblock.bin
-	popd
-	echo " => idblock.bin build done"
+    #
+    # SPL v1.13 has broken SD card support!
+    # Use v1.12 instead.
+    #
+    # SPL="${ROOTDIR}/misc/rkbin/${SPL_RKBIN}"
+    SPL="${ROOTDIR}/misc/rk3588_spl_v1.12.bin"
+
+    # Create idblock.bin
+    ${ROOTDIR}/misc/tools/${MACHINE_TYPE}/mkimage -n rk3588 -T rksd -d ${DDRBIN}:${SPL} idblock.bin
+
+    popd
+    echo " => idblock.bin build done"
 }

-function _build_fit(){
-	echo " => Building FIT"
-	pushd ${WORKSPACE}
-	BL31=$(grep '^PATH=.*_bl31_' ${ROOTDIR}/misc/rkbin/RKTRUST/${TRUST_INI} | cut -d = -f 2-)
-	BL32=$(grep '^PATH=.*_bl32_' ${ROOTDIR}/misc/rkbin/RKTRUST/${TRUST_INI} | cut -d = -f 2-)
-	rm -f bl31_0x*.bin ${WORKSPACE}/BL33_AP_UEFI.Fv ${SOC_L}_${DEVICE}_EFI.its
+function _build_fit() {
+    echo " => Building FIT"
+    pushd ${WORKSPACE}

-	${ROOTDIR}/misc/extractbl31.py ${ROOTDIR}/misc/rkbin/${BL31}
-	cp ${ROOTDIR}/misc/rkbin/${BL32} ${WORKSPACE}/bl32.bin
-	cp ${ROOTDIR}/misc/${SOC_L}_spl.dtb ${WORKSPACE}/${DEVICE}.dtb
-	cp ${WORKSPACE}/Build/${PLATFORM_NAME}/${_MODE}_${TOOLCHAIN}/FV/BL33_AP_UEFI.Fv ${WORKSPACE}/
-	cat ${ROOTDIR}/misc/uefi_${SOC_L}.its | sed "s,@DEVICE@,${DEVICE},g" > ${SOC_L}_${DEVICE}_EFI.its
-	${ROOTDIR}/misc/tools/${MACHINE_TYPE}/mkimage -f ${SOC_L}_${DEVICE}_EFI.its -E ${DEVICE}_EFI.itb
+    BL31_RKBIN=$(grep '^PATH=.*_bl31_' ${ROOTDIR}/misc/rkbin/RKTRUST/${TRUST_INI} | cut -d = -f 2-)
+    BL32_RKBIN=$(grep '^PATH=.*_bl32_' ${ROOTDIR}/misc/rkbin/RKTRUST/${TRUST_INI} | cut -d = -f 2-)

-	popd
-	echo " => FIT build done"
+    BL31="${ROOTDIR}/misc/rkbin/${BL31_RKBIN}"
+    BL32="${ROOTDIR}/misc/rkbin/${BL32_RKBIN}"
+
+    if [ ${OPEN_TFA} == 1 ]; then
+        BL31="${ROOTDIR}/arm-trusted-firmware/build/${TFA_PLAT}/${RELEASE_TYPE,,}/bl31/bl31.elf"
+    fi
+
+    rm -f bl31_0x*.bin ${WORKSPACE}/BL33_AP_UEFI.Fv ${SOC_L}_${DEVICE}_EFI.its
+
+    ${ROOTDIR}/misc/extractbl31.py ${BL31}
+    if [ ! -f bl31_0x000f0000.bin ]; then
+        # Not used but FIT expects it.
+        touch bl31_0x000f0000.bin
+    fi
+
+    cp ${BL32} ${WORKSPACE}/bl32.bin
+    cp ${ROOTDIR}/misc/${SOC_L}_spl.dtb ${WORKSPACE}/${DEVICE}.dtb
+    cp ${WORKSPACE}/Build/${PLATFORM_NAME}/${RELEASE_TYPE}_${TOOLCHAIN}/FV/BL33_AP_UEFI.Fv ${WORKSPACE}/
+    cat ${ROOTDIR}/misc/uefi_${SOC_L}.its | sed "s,@DEVICE@,${DEVICE},g" > ${SOC_L}_${DEVICE}_EFI.its
+    ${ROOTDIR}/misc/tools/${MACHINE_TYPE}/mkimage -f ${SOC_L}_${DEVICE}_EFI.its -E ${DEVICE}_EFI.itb
+
+    popd
+    echo " => FIT build done"
 }

-function _pack(){
-	_build_idblock
-	_build_fit
+function _pack_image() {
+    _build_idblock
+    _build_fit

-	echo " => Building 8MB NOR FLASH IMAGE"
-	cp ${WORKSPACE}/Build/${PLATFORM_NAME}/${_MODE}_${TOOLCHAIN}/FV/NOR_FLASH_IMAGE.fd ${WORKSPACE}/RK3588_NOR_FLASH.img
+    echo " => Building 8MB NOR FLASH IMAGE"
+    cp ${WORKSPACE}/Build/${PLATFORM_NAME}/${RELEASE_TYPE}_${TOOLCHAIN}/FV/NOR_FLASH_IMAGE.fd ${WORKSPACE}/RK3588_NOR_FLASH.img

-	# might be GPT table? size:0x4400
-	dd if=${ROOTDIR}/misc/rk3588_spi_nor_gpt.img of=${WORKSPACE}/RK3588_NOR_FLASH.img
-	# idblock at 0x8000
-	dd if=${WORKSPACE}/idblock.bin of=${WORKSPACE}/RK3588_NOR_FLASH.img bs=1K seek=32
-	# FIT Image at 0x100000
-	dd if=${WORKSPACE}/${DEVICE}_EFI.itb of=${WORKSPACE}/RK3588_NOR_FLASH.img bs=1K seek=1024
-	cp ${WORKSPACE}/RK3588_NOR_FLASH.img ${ROOTDIR}/
+    # GPT at 0x0, size:0x4400
+    dd if=${ROOTDIR}/misc/rk3588_spi_nor_gpt.img of=${WORKSPACE}/RK3588_NOR_FLASH.img
+    # idblock at 0x8000
+    dd if=${WORKSPACE}/idblock.bin of=${WORKSPACE}/RK3588_NOR_FLASH.img bs=1K seek=32
+    # FIT Image at 0x100000
+    dd if=${WORKSPACE}/${DEVICE}_EFI.itb of=${WORKSPACE}/RK3588_NOR_FLASH.img bs=1K seek=1024
+    cp ${WORKSPACE}/RK3588_NOR_FLASH.img ${ROOTDIR}/
 }

 function _build(){
-	local DEVICE="${1}"
-	shift
-	[ -d "${WORKSPACE}/Conf" ]||mkdir -p "${WORKSPACE}/Conf"
-	source "${ROOTDIR}/edk2/edksetup.sh"
-	[ -d "${WORKSPACE}" ]||mkdir "${WORKSPACE}"
-	set -x
-	make -C "${ROOTDIR}/edk2/BaseTools"||exit "$?"
+    local DEVICE="${1}"; shift

-	EXT=""
+    #
+    # Grab platform parameters
+    #
+    if [ -f "configs/${DEVICE}.conf" ]
+    then source "configs/${DEVICE}.conf"
+    else _error "Device configuration not found"
+    fi
+    if [ -f "configs/${SOC}.conf" ]
+    then source "configs/${SOC}.conf"
+    else _error "SoC configuration not found"
+    fi
+    typeset -l SOC_L="$SOC"

-	if [ -f "configs/${DEVICE}.conf" ]
-	then source "configs/${DEVICE}.conf"
-	else _error "Device configuration not found"
-	fi
-	if [ -f "configs/${SOC}.conf" ]
-	then source "configs/${SOC}.conf"
-	else _error "SoC configuration not found"
-	fi
-	typeset -l SOC_L="$SOC"
+    rm -f "${OUTDIR}/RK35*_NOR_FLASH.img"

-	# based on the instructions from edk2-platform
-	rm -f "${OUTDIR}/RK35*_NOR_FLASH.img"
+    #
+    # Build TF-A
+    #
+    if [ ${OPEN_TFA} == 1 ]; then
+        pushd arm-trusted-firmware

-	case "${MODE}" in
-		RELEASE) _MODE=RELEASE;;
-		*) _MODE=DEBUG;;
-	esac
+        if [ ${RELEASE_TYPE} == "DEBUG" ]; then
+            DEBUG=1
+        else
+            DEBUG=0
+        fi

-	build \
-		-s \
-		-n 0 \
-		-a AARCH64 \
-		-t "${TOOLCHAIN}" \
-		-p "${ROOTDIR}/${DSC_FILE}" \
-		-b "${_MODE}" \
-		-D FIRMWARE_VER="${GITCOMMIT}" \
-		-D ENABLE_SIMPLE_INIT="${BUILD_GUI}" \
-		-D CONFIG_SOC="${SOC}" \
-		${BUILD_FLAGS} \
-		||return "$?"
+        make PLAT=${TFA_PLAT} DEBUG=${DEBUG} all ${TFA_FLAGS}

-	_pack
-	set +x
+        popd
+    fi

-	echo "Build done: RK3588_NOR_FLASH.img"
+    #
+    # Build EDK2
+    #
+    [ -d "${WORKSPACE}/Conf" ] || mkdir -p "${WORKSPACE}/Conf"
+
+    export GCC_AARCH64_PREFIX="${CROSS_COMPILE}"
+    export CLANG38_AARCH64_PREFIX="${CROSS_COMPILE}"
+    export PACKAGES_PATH="${ROOTDIR}/edk2:${ROOTDIR}/edk2-platforms:${ROOTDIR}/edk2-rockchip:${ROOTDIR}/edk2-rockchip-non-osi:${ROOTDIR}/edk2-non-osi:${ROOTDIR}"
+
+    make -C "${ROOTDIR}/edk2/BaseTools"
+    source "${ROOTDIR}/edk2/edksetup.sh"
+
+    build \
+        -s \
+        -n 0 \
+        -a AARCH64 \
+        -t "${TOOLCHAIN}" \
+        -p "${ROOTDIR}/${DSC_FILE}" \
+        -b "${RELEASE_TYPE}" \
+        -D FIRMWARE_VER="${GIT_COMMIT}" \
+        ${EDK2_FLAGS}
+
+    #
+    # Compile final image
+    #
+    _pack_image
+
+    echo "Build done: RK3588_NOR_FLASH.img"
 }

-function _clean(){ rm --one-file-system --recursive --force "${OUTDIR}"/workspace "${OUTDIR}"/RK3588_*.img "${OUTDIR}"/uefi-*.img*; }
+function _clean() { rm --one-file-system --recursive --force "${OUTDIR}"/workspace "${OUTDIR}"/RK3588_*.img; }
+function _distclean() { if [ -d .git ]; then git clean -xdf; else _clean; fi; }

-function _distclean(){ if [ -d .git ];then git clean -xdf;else _clean;fi; }
-
-OUTDIR="${PWD}"
-ROOTDIR="$(realpath "$(dirname "$0")")"
-cd "${ROOTDIR}"||exit 1
+#
+# Default variables
+#
 typeset -l DEVICE
-typeset -u MODE
+typeset -u RELEASE_TYPE
 DEVICE=""
-MODE=DEBUG
+RELEASE_TYPE=DEBUG
+TOOLCHAIN=GCC
+OPEN_TFA=1
+TFA_FLAGS=""
+EDK2_FLAGS=""
 CLEAN=false
 DISTCLEAN=false
-TOOLCHAIN=GCC
-BUILD_FLAGS=""
-export ROOTDIR OUTDIR
-export GEN_ROOTFS=true
-export BUILD_GUI=false
-OPTS="$(getopt -o t:d:haCDO:r -l toolchain:,device:,help,all,skip-rootfs-gen,gui,clean,distclean,outputdir:,release:,build-flags: -n 'build.sh' -- "$@")"||exit 1
+OUTDIR="${PWD}"
+
+#
+# Get options
+#
+OPTS=$(getopt -o "d:r:t:CDh" -l "device:,release:,toolchain:,open-tfa:,tfa-flags:,edk2-flags:,clean,distclean,help" -n build.sh -- "${@}") || _help $?
 eval set -- "${OPTS}"
-while true
-do	case "${1}" in
-		-d|--device) DEVICE="${2}";shift 2;;
-		-a|--all) DEVICE=all;shift;;
-		-C|--clean) CLEAN=true;shift;;
-		-D|--distclean) DISTCLEAN=true;shift;;
-		-O|--outputdir) OUTDIR="${2}";shift 2;;
-		--skip-rootfs-gen) GEN_ROOTFS=false;shift;;
-		--gui) BUILD_GUI=true;shift;;
-		-r|--release) MODE="${2}";shift 2;;
-		-t|--toolchain) TOOLCHAIN="${2}";shift 2;;
-		--build-flags) BUILD_FLAGS="${2}";shift 2;;
-		-h|--help) _help 0;shift;;
-		--) shift;break;;
-		*) _help 1;;
-	esac
+while true; do
+    case "${1}" in
+        -d|--device) DEVICE="${2}"; shift 2 ;;
+        -r|--release) RELEASE_TYPE="${2}"; shift 2 ;;
+        -t|--toolchain) TOOLCHAIN="${2}"; shift 2 ;;
+        --open-tfa) OPEN_TFA="${2}"; shift 2 ;;
+        --tfa-flags) TFA_FLAGS="${2}"; shift 2 ;;
+        --edk2-flags) EDK2_FLAGS="${2}"; shift 2 ;;
+        -C|--clean) CLEAN=true; shift ;;
+        -D|--distclean) DISTCLEAN=true; shift ;;
+        -h|--help) _help 0; shift ;;
+        --) shift; break ;;
+        *) break ;;
+    esac
 done
-if "${DISTCLEAN}";then _distclean;exit "$?";fi
-if "${CLEAN}";then _clean;exit "$?";fi
-[ -z "${DEVICE}" ]&&_help 1
-
-if ! [ -f edk2/edksetup.sh ] && ! [ -f ../edk2/edksetup.sh ]
-then
-	set -e
-	echo "SKIP Updating submodules"
-	set +e
+if [[ -n "${@}" ]]; then
+    echo "Invalid additional arguments '${@}'"
+    _help 1
 fi

-for i in "${SIMPLE_INIT}" ./simple-init ../simple-init
-do
-	if [ -n "${i}" ]&&[ -f "${i}/SimpleInit.inc" ]
-	then
-		_SIMPLE_INIT="$(realpath "${i}")"
-		break
-	fi
-done
+if "${DISTCLEAN}"; then _distclean; exit "$?"; fi
+if "${CLEAN}"; then _clean; exit "$?"; fi

-[ -n "${_SIMPLE_INIT}" ]||[ ${BUILD_GUI} == false ]||error "SimpleInit not found, please see README.md"
-[ -f "configs/${DEVICE}.conf" ]||[ "${DEVICE}" == "all" ]||_error "Device configuration not found"
+[ -z "${DEVICE}" ] && _help 1
+[ -f "configs/${DEVICE}.conf" ] || [ "${DEVICE}" == "all" ] || _error "Device configuration not found"
+
+#
+# Get machine architecture
+#
+MACHINE_TYPE=$(uname -m)
+
+# Fix-up possible differences in reported arch
+if [ ${MACHINE_TYPE} == 'arm64' ]; then
+    MACHINE_TYPE='aarch64'
+elif [ ${MACHINE_TYPE} == 'amd64' ]; then
+    MACHINE_TYPE='x86_64'
+fi
+
+if [ ${MACHINE_TYPE} != 'aarch64' ]; then
+    export CROSS_COMPILE="${CROSS_COMPILE:-aarch64-linux-gnu-}"
+fi
+
+GIT_COMMIT="$(git describe --tags --always)" || GIT_COMMIT="unknown"

-export CROSS_COMPILE="${CROSS_COMPILE:-aarch64-linux-gnu-}"
-export GCC_AARCH64_PREFIX="${CROSS_COMPILE}"
-export CLANG38_AARCH64_PREFIX="${CROSS_COMPILE}"
-# export PACKAGES_PATH="$_EDK2:$_EDK2_PLATFORMS:$_SIMPLE_INIT:$PWD"
-export PACKAGES_PATH="${ROOTDIR}/edk2:${ROOTDIR}/edk2-platforms:${ROOTDIR}/edk2-rockchip:${ROOTDIR}/edk2-rockchip-non-osi:${ROOTDIR}/edk2-non-osi:${ROOTDIR}:${_SIMPLE_INIT}"
 export WORKSPACE="${OUTDIR}/workspace"
-GITCOMMIT="$(git describe --tags --always)"||GITCOMMIT="unknown"
-export GITCOMMIT
+[ -d "${WORKSPACE}" ] || mkdir "${WORKSPACE}"
+
+ROOTDIR="$(realpath "$(dirname "$0")")"
+cd "${ROOTDIR}" || exit 1
+
+# Exit on first error
 set -e

-if "${BUILD_GUI}"
-then
-	mkdir -p "${_SIMPLE_INIT}/build" "${_SIMPLE_INIT}/root/usr/share/locale"
-	for i in "${_SIMPLE_INIT}/po/"*.po
-	do
-		[ -f "${i}" ]||continue
-		_name="$(basename "$i" .po)"
-		_path="${_SIMPLE_INIT}/root/usr/share/locale/${_name}/LC_MESSAGES"
-		mkdir -p "${_path}"
-		msgfmt -o "${_path}/simple-init.mo" "${i}"
-	done
-
-	if "${GEN_ROOTFS}"
-	then
-		bash "${_SIMPLE_INIT}/scripts/gen-rootfs-source.sh" \
-			"${_SIMPLE_INIT}" \
-			"${_SIMPLE_INIT}/build"
-	fi
-fi
-
 if [ "${DEVICE}" == "all" ]
 then
-	E=0
-	for i in configs/*.conf
-	do
-		DEV="$(basename "$i" .conf)"
-		if [ "${DEV}" != "RK3588" ]&&[ "${DEV}" != "RK3568" ]
-		then
-			echo "Building ${DEV}"
-			_build "${DEV}"||E="$?"
-		fi
-	done
-	exit "${E}"
+    for i in configs/*.conf; do
+        DEV="$(basename "$i" .conf)"
+        if [ "${DEV}" != "RK3588" ]
+        then
+            echo "Building ${DEV}"
+            _build "${DEV}"
+        fi
+    done
 else
-	_build "${DEVICE}"
+    _build "${DEVICE}"
 fi
--- a/configs/RK3588.conf
+++ b/configs/RK3588.conf
@@ -1,2 +1,3 @@
 MINIALL_INI=RK3588MINIALL.ini
 TRUST_INI=RK3588TRUST.ini
+TFA_PLAT=rk3588_reference_pmic
--- a/configs/aio-3588q.conf
+++ b/configs/aio-3588q.conf
@@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc
+PLATFORM_NAME=AIO-3588Q
+SOC=RK3588
--- a/configs/fydetab-duo.conf
+++ b/configs/fydetab-duo.conf
@@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/FydeInnovations/FydetabDuo/FydetabDuo.dsc
+PLATFORM_NAME=FydetabDuo
+SOC=RK3588
--- a/configs/itx-3588j.conf
+++ b/configs/itx-3588j.conf
@@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.dsc
+PLATFORM_NAME=ITX-3588J
+SOC=RK3588
--- a/configs/rock-5-itx.conf
+++ b/configs/rock-5-itx.conf
@@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/Radxa/ROCK5ITX/ROCK5ITX.dsc
+PLATFORM_NAME=ROCK5ITX
+SOC=RK3588
--- a/2
+++ b/2
--- a/2
+++ b/2
--- a/2
+++ b/2
--- a/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/README.md
+++ b/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/README.md
@@ -1,8 +1,15 @@
 # Rockchip Platform Device Trees
 ## Sources
-* <https://github.com/armbian/linux-rockchip/tree/a8384552a2e009797aa5b3e9a046d30e8d2e5d3c/arch/arm64/boot/dts/rockchip>
+* <https://github.com/armbian/linux-rockchip/tree/f3fb30ac9de06b41fb621d17bc53603f1f48ac90/arch/arm64/boot/dts/rockchip>
+  * Updated to `rk-6.1-rkr1` branch, currently called `vendor` branch in armbian/build

 * roc-rk3588s-pc: <https://gitlab.com/firefly-linux/kernel/-/tree/b8646da2122f45a2c02082d949427b80d2e89b1f/arch/arm64/boot/dts/rockchip>

+* itx-3588j: <https://gitlab.com/firefly-linux/kernel/-/tree/e14c28295dd7ee8f807899e9b0b7da5f79742e4f/arch/arm64/boot/dts/rockchip>
+  (note: in the dtb given here, the builtin bootargs in the source above were commented out
+   before building. Not sure if that was a necessary step - SS)
+
+* rk3588-firefly-aio-3588q: <https://gitlab.com/firefly-linux/kernel/-/tree/fa0e053fd911339b825407cb6d4b167fad7cdc49/arch/arm64/boot/dts/rockchip>
+
 ## License
 SPDX-License-Identifier: GPL-2.0-only
--- a/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/itx-3588j.dtb
+++ b/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/itx-3588j.dtb
--- a/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-blade3-v101-linux.dtb
+++ b/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-blade3-v101-linux.dtb
--- a/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-blueberry-edge-v12-linux.dtb
+++ b/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-blueberry-edge-v12-linux.dtb
--- a/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-blueberry-minipc-linux.dtb
+++ b/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-blueberry-minipc-linux.dtb
--- a/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-firefly-aio-3588q.dtb
+++ b/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-firefly-aio-3588q.dtb
--- a/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-hinlink-h88k.dtb
+++ b/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-hinlink-h88k.dtb
--- a/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-nanopc-t6.dtb
+++ b/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-nanopc-t6.dtb
--- a/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-orangepi-5-plus.dtb
+++ b/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-orangepi-5-plus.dtb
--- a/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-rock-5-itx.dtb
+++ b/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-rock-5-itx.dtb
--- a/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-rock-5b.dtb
+++ b/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-rock-5b.dtb
--- a/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-9tripod-linux.dtb
+++ b/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-9tripod-linux.dtb
--- a/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-khadas-edge2.dtb
+++ b/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-khadas-edge2.dtb
--- a/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-nanopi-r6c.dtb
+++ b/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-nanopi-r6c.dtb
--- a/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-nanopi-r6s.dtb
+++ b/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-nanopi-r6s.dtb
--- a/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-orangepi-5.dtb
+++ b/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-orangepi-5.dtb
--- a/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-rock-5a.dtb
+++ b/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-rock-5a.dtb
--- a/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/AcpiTables/AcpiTables.inf
+++ b/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/AcpiTables/AcpiTables.inf
@@ -32,15 +32,6 @@
  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
  $(RK_COMMON_ACPI_DIR)/Pptt.aslc
-  $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl
-  $(RK_COMMON_ACPI_DIR)/Sata0.asl
-  $(RK_COMMON_ACPI_DIR)/Sata1.asl
-  $(RK_COMMON_ACPI_DIR)/Sata2.asl
-  $(RK_COMMON_ACPI_DIR)/Usb2Host.asl

 [Packages]
  ArmPkg/ArmPkg.dec
@@ -49,6 +40,7 @@
  MdeModulePkg/MdeModulePkg.dec
  MdePkg/MdePkg.dec
  Silicon/Rockchip/RockchipPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec

 [FixedPcd]
  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
@@ -59,3 +51,8 @@
  gArmTokenSpaceGuid.PcdGicDistributorBase
  gArmTokenSpaceGuid.PcdGicRedistributorsBase
  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gRK3588TokenSpaceGuid.PcdI2S0Supported
+  gRK3588TokenSpaceGuid.PcdI2S1Supported
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken
--- a/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/AcpiTables/Dsdt.asl
+++ b/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/AcpiTables/Dsdt.asl
@@ -13,22 +13,41 @@

 #include "AcpiTables.h"

+#define BOARD_I2S0_TPLG "i2s-jack"
+
+#define BOARD_AUDIO_CODEC_HID "ESSX8388"
+#define BOARD_CODEC_I2C "\\_SB.I2C7"
+#define BOARD_CODEC_I2C_ADDR 0x11
+#define BOARD_CODEC_GPIO "\\_SB.GPI4"
+#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PA7
+
 DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588  ", 2)
 {
  Scope (\_SB_)
  {
+    include ("DsdtCommon.asl")
+
    include ("Cpu.asl")

+    include ("Pcie.asl")
+    include ("Sata.asl")
    include ("Emmc.asl")
    include ("Sdhc.asl")
+    include ("Dma.asl")
    // include ("Gmac.asl")
-    // include ("Gpio.asl")
-    // include ("I2c.asl")
+    include ("Gpio.asl")
+    include ("I2c.asl")
    include ("Uart.asl")
    // include ("Spi.asl")

-    include ("Usb1Host.asl")
+    include ("I2s.asl")
+
+    include ("Usb2Host.asl")
    include ("Usb3Host0.asl")
    include ("Usb3Host2.asl")
+
+    Scope (I2C7) {
+      include ("Es8388.asl")
+    }
  }
 }
--- a/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/IndiedroidNova.dsc
+++ b/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/IndiedroidNova.dsc
@@ -65,9 +65,9 @@
  gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588s-9tripod-linux"

  # I2C
-  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51 }
-  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6 }
-  gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51, 0x11 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6, 0x7 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE, FALSE }
  gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
  gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 }
  gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) }
@@ -93,6 +93,11 @@
  gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE
  gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 }

+  #
+  # I2S
+  #
+  gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE
+
  #
  # On-Board fan output
  #
--- a/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -145,32 +145,32 @@ I2cIomux (
 {
  switch (id) {
  case 0:
-    /* io mux M2 */
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
+    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
+    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
    break;
  case 1:
-    /* io mux */
-    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
-    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
    break;
  case 2:
-    /* io mux */
-    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
-    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
-    PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
-    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
    break;
  case 3:
    break;
  case 4:
+    GpioPinSetFunction(1, GPIO_PIN_PA3, 9); //i2c4_scl_m3
+    GpioPinSetFunction(1, GPIO_PIN_PA2, 9); //i2c4_sda_m3
    break;
  case 5:
+    GpioPinSetFunction(3, GPIO_PIN_PC7, 9); //i2c5_scl_m0
+    GpioPinSetFunction(3, GPIO_PIN_PD0, 9); //i2c5_sda_m0
    break;
  case 6:
-    /* io mux M3 */
-    BUS_IOC->GPIO4B_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0090;
-    BUS_IOC->GPIO4B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
+    GpioPinSetFunction(4, GPIO_PIN_PB1, 9); //i2c6_scl_m3
+    GpioPinSetFunction(4, GPIO_PIN_PB0, 9); //i2c6_sda_m3
+    break;
+  case 7:
+    GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0
+    GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0
    break;
  default:
    break;
@@ -292,4 +292,5 @@ PlatformEarlyInit (
  )
 {
  // Configure various things specific to this platform
+  GpioPinSetFunction(4, GPIO_PIN_PA7, 0); //jdet
 }
--- a/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.Modules.fdf.inc
+++ b/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.Modules.fdf.inc
@@ -0,0 +1,18 @@
+## @file
+#
+#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+  # ACPI Support
+  INF RuleOverride = ACPITABLE Platform/Firefly/AIO-3588Q/AcpiTables/AcpiTables.inf
+
+  # Device Tree Support
+  FILE FREEFORM = gDtPlatformDefaultDtbFileGuid {
+    SECTION RAW = Platform/Rockchip/DeviceTree/rk3588-firefly-aio-3588q.dtb
+  }
+
+  # Splash screen logo
+  INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf
--- a/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc
+++ b/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc
@@ -0,0 +1,31 @@
+## @file
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = AIO-3588Q
+  PLATFORM_VENDOR                = Firefly
+  PLATFORM_GUID                  = 400f8259-7664-47df-b375-8ba262e4867e
+  PLATFORM_VERSION               = 0.2
+  DSC_SPECIFICATION              = 0x00010019
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  VENDOR_DIRECTORY               = Platform/$(PLATFORM_VENDOR)
+  PLATFORM_DIRECTORY             = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+
+  #
+  # Platform based on AIO-3588Q board
+  #
+!include Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc.inc
--- a/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc.inc
+++ b/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc.inc
@@ -0,0 +1,134 @@
+## @file
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  FLASH_DEFINITION               = Silicon/Rockchip/RK3588/RK3588.fdf
+  RK_PLATFORM_FVMAIN_MODULES     = Platform/Firefly/AIO-3588Q/AIO-3588Q.Modules.fdf.inc
+
+  #
+  # HYM8563 RTC support
+  # I2C location configured by PCDs below.
+  #
+  DEFINE RK_RTC8563_ENABLE = TRUE
+
+  #
+  # PCA9555 GPIO extender support
+  # I2C location configured by PCDs below.
+  #
+  DEFINE RK_PCA9555_ENABLE = TRUE
+
+  #
+  # RK3588-based platform
+  #
+!include Silicon/Rockchip/RK3588/RK3588Platform.dsc.inc
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+
+[LibraryClasses.common]
+  RockchipPlatformLib|Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform.
+#
+################################################################################
+
+[PcdsFixedAtBuild.common]
+  # SMBIOS platform config
+  gRockchipTokenSpaceGuid.PcdPlatformName|"AIO-3588Q"
+  gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Firefly"
+  gRockchipTokenSpaceGuid.PcdFamilyName|"AIO"
+  gRockchipTokenSpaceGuid.PcdProductUrl|"https://en.t-firefly.com/product/core/icore3588q"
+  gRockchipTokenSpaceGuid.PcdDeviceTreeName|"aio-3588q"
+
+  # I2C
+  # i2c0: pc9202@3c, rk8602@42, rk8603@43
+  # i2c1: rk8602@42 (npu)
+  # i2c3: es8388@11, XC7160b@1b, gc2053b@37, gc2093b@7e
+  # i2c6: pca9555@20, pca9555@21, fusb302@22, hym8563@51
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{           0x42,  0x43,  0x42,  0x11,  0x51, 0x20,  0x21,  0x22  }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{               0x0,   0x0,   0x1,   0x3,   0x6,  0x6,   0x6,   0x6   }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{     0x0,  0x0 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) }
+  gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
+  gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6
+  gRockchipTokenSpaceGuid.PcdPca9555Address|0x21
+  gRockchipTokenSpaceGuid.PcdPca9555Bus|0x6
+
+  #
+  # CPU Performance default values
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE)
+  gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_PCIE)
+  gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3)
+
+  #
+  # USB/DP Combo PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 }
+  gRK3588TokenSpaceGuid.PcdUsbDpPhy1Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x2, 0x3 }
+
+  #
+  # GMAC
+  #
+  gRK3588TokenSpaceGuid.PcdGmac0Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdGmac0TxDelay|0x47
+  gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x4f
+
+  #
+  # I2S
+  #
+  gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE
+
+  #
+  # On-Board fan output
+  #
+  gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform.
+#
+################################################################################
+[Components.common]
+  # ACPI Support
+  Platform/Firefly/AIO-3588Q/AcpiTables/AcpiTables.inf
+
+  # Splash screen logo
+  $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf
+
+  # Hack to enable use of PCA9555 during PCIe initialization.
+  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+    <LibraryClasses>
+      RockchipPlatformLib|Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLibPcaDepex.inf
+  }
--- a/edk2-rockchip/Platform/Firefly/AIO-3588Q/AcpiTables/AcpiTables.inf
+++ b/edk2-rockchip/Platform/Firefly/AIO-3588Q/AcpiTables/AcpiTables.inf
@@ -0,0 +1,58 @@
+#/** @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2019-2021, ARM Limited. All rights reserved.
+#  Copyright (c) Microsoft Corporation. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+  RK_COMMON_ACPI_DIR             = Silicon/Rockchip/RK3588/AcpiTables
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+
+[Sources]
+  Dsdt.asl
+  $(RK_COMMON_ACPI_DIR)/Madt.aslc
+  $(RK_COMMON_ACPI_DIR)/Fadt.aslc
+  $(RK_COMMON_ACPI_DIR)/Gtdt.aslc
+  $(RK_COMMON_ACPI_DIR)/Spcr.aslc
+  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
+  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
+  $(RK_COMMON_ACPI_DIR)/Pptt.aslc
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Rockchip/RockchipPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gRK3588TokenSpaceGuid.PcdI2S0Supported
+  gRK3588TokenSpaceGuid.PcdI2S1Supported
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken
--- a/edk2-rockchip/Platform/Firefly/AIO-3588Q/AcpiTables/Dsdt.asl
+++ b/edk2-rockchip/Platform/Firefly/AIO-3588Q/AcpiTables/Dsdt.asl
@@ -0,0 +1,55 @@
+/** @file
+ *
+ *  Differentiated System Definition Table (DSDT)
+ *
+ *  Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ *  Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
+ *  Copyright (c) Microsoft Corporation. All rights reserved.
+ *  Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include "AcpiTables.h"
+
+#define BOARD_I2S0_TPLG "i2s-jack"
+
+#define BOARD_AUDIO_CODEC_HID "ESSX8388"
+#define BOARD_CODEC_I2C "\\_SB.I2C3"
+#define BOARD_CODEC_I2C_ADDR 0x11
+#define BOARD_CODEC_GPIO "\\_SB.GPI1"
+#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PC4
+
+DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588  ", 2)
+{
+  Scope (\_SB_)
+  {
+    include ("DsdtCommon.asl")
+
+    include ("Cpu.asl")
+
+    include ("Pcie.asl")
+    include ("Sata.asl")
+    include ("Emmc.asl")
+    include ("Sdhc.asl")
+    include ("Dma.asl")
+    include ("Gmac0.asl")
+    include ("Gmac1.asl")
+    include ("Gpio.asl")
+    include ("I2c.asl")
+    include ("Uart.asl")
+    // include ("Spi.asl")
+
+    include ("I2s.asl")
+
+    include ("Usb2Host.asl")
+    include ("Usb3Host0.asl")
+    include ("Usb3Host1.asl")
+    include ("Usb3Host2.asl")
+
+    Scope (I2C3) {
+      include ("Es8388.asl")
+    }
+  }
+}
--- a/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -0,0 +1,460 @@
+/** @file
+*
+*  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include <Base.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/GpioLib.h>
+#include <Library/RK806.h>
+#include <Library/Rk3588Pcie.h>
+#include <Library/PWMLib.h>
+#include <Soc.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/Pca9555.h>
+
+static struct regulator_init_data rk806_init_data[] = {
+  /* Master PMIC */
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
+ // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+
+  /* No dual PMICs on this platform */
+};
+
+EFI_STATUS
+EFIAPI
+GetPca9555Protocol (
+  IN OUT PCA95XX_PROTOCOL        **Pca95xxProtocl
+  )
+{
+  EFI_HANDLE          *HandleBuffer;
+  EFI_STATUS           Status;
+  UINTN                HandleCount;
+
+  /* Locate Handles of all PCA95XX_PROTOCOL producers */
+  Status = gBS->LocateHandleBuffer (ByProtocol,
+                  &gPca95xxProtocolGuid,
+                  NULL,
+                  &HandleCount,
+                  &HandleBuffer);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "%a: Unable to locate handles\n", __FUNCTION__));
+    return Status;
+  }
+
+  DEBUG ((DEBUG_INFO,
+          "%a: got %d PCA95XX_PROTOCOLs\n",
+          __FUNCTION__,
+          HandleCount));
+
+  /*
+   * Open Pca95xxProtocl. With EFI_OPEN_PROTOCOL_GET_PROTOCOL attribute
+   * the consumer is not obliged to call CloseProtocol.
+   */
+  Status = gBS->OpenProtocol (HandleBuffer[0],
+                  &gPca95xxProtocolGuid,
+                  (VOID **)Pca95xxProtocl,
+                  HandleBuffer[0],
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+
+  return Status;
+}
+
+VOID
+EFIAPI
+SdmmcIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux (microSD socket) */
+  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+}
+
+VOID
+EFIAPI
+SdhciEmmcIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux */
+  /* Do not override, set by earlier boot stages. */
+}
+
+#define NS_CRU_BASE         0xFD7C0000
+#define CRU_CLKSEL_CON59    0x03EC
+#define CRU_CLKSEL_CON78    0x0438
+
+VOID
+EFIAPI
+Rk806SpiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
+  PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+}
+
+VOID
+EFIAPI
+Rk806Configure (
+  VOID
+  )
+{
+  UINTN RegCfgIndex;
+
+  RK806Init();
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
+    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+}
+
+VOID
+EFIAPI
+SetCPULittleVoltage (
+  IN UINT32 Microvolts
+  )
+{
+  struct regulator_init_data Rk806CpuLittleSupply =
+        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+
+  RK806RegulatorInit(Rk806CpuLittleSupply);
+}
+
+VOID
+EFIAPI
+NorFspiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  /* Do not override, set by earlier boot stages. */
+}
+
+VOID
+EFIAPI
+GmacIomux (
+  IN UINT32 Id
+  )
+{
+  switch (Id) {
+    case 0:
+      /* gmac0 iomux */
+      BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100; // GMAC0_RXD2, GMAC0_RXD3
+      BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111; // GMAC0_RXCLK, GMAC0_TXD2, GMAC0_TXD3, GMAC0_TXCLK
+      BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100; // GMAC0_TXD0, GMAC0_TXD1
+      BUS_IOC->GPIO2C_IOMUX_SEL_L = (0x0FFFUL << 16) | 0x0111; // GMAC0_TXEN, GMAC0_RXD0, GMAC0_RXD1
+      BUS_IOC->GPIO4C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100; // GMAC0_RXDV_CRS, GMAC0_MCLKINOUT
+      BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011; // GMAC0_MDC, GMAC0_MDIO
+
+      /* phy0 reset */
+      GpioPinSetDirection (3, GPIO_PIN_PC7, GPIO_PIN_OUTPUT);
+      break;
+    case 1:
+      /* gmac1 iomux */
+      BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111; /* GMAC1_MCLKINOUT, GMAC1_TXEN, GMAC1_TXD1 */
+      BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111; /* GMAC1_RXD3, GMAC1_RXD2, GMAC1_TXD3, GMAC1_TXD2 */
+      BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; /* GMAC1_TXD0, GMAC1_RXDV_CRS, GMAC1_RXD1 */
+      BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011; /* GMAC1_RXD0, GMAC1_RXCLK, GMAC1_TXCLK */
+      BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100; /* GMAC1_MDIO, GMAC1_MDC */
+
+      /* phy1 reset */
+      GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+GmacIoPhyReset (
+  UINT32   Id,
+  BOOLEAN  Enable
+  )
+{
+  switch (Id) {
+    case 0:
+      /* phy0 reset */
+      GpioPinWrite (3, GPIO_PIN_PC7, !Enable);
+      break;
+    case 1:
+      /* phy1 reset */
+      GpioPinWrite (3, GPIO_PIN_PB7, !Enable);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+NorFspiEnableClock (
+  UINT32 *CruBase
+  )
+{
+  UINTN BaseAddr = (UINTN) CruBase;
+
+  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+}
+
+VOID
+EFIAPI
+I2cIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); // I2C0_SCL_M2
+    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); // I2C0_SDA_M2
+    break;
+  case 1:
+    GpioPinSetFunction(0, GPIO_PIN_PD4, 9); // I2C1_SCL_M2
+    GpioPinSetFunction(0, GPIO_PIN_PD5, 9); // I2C1_SDA_M2
+    break;
+  case 3:
+    GpioPinSetFunction(1, GPIO_PIN_PC1, 9); // I2C3_SCL_M0
+    GpioPinSetFunction(1, GPIO_PIN_PC0, 9); // I2C3_SDA_M0
+    break;
+  case 6:
+    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); // I2C6_SCL_M0
+    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); // I2C6_SDA_M0
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+UsbPortPowerEnable (
+  VOID
+  )
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+  PCA95XX_PROTOCOL *Pca95xxProtocol;
+
+  /* On Firefly AIO-3588Q this is controlled via the PCA9555. */
+  Status = GetPca9555Protocol(&Pca95xxProtocol);
+  if (EFI_ERROR(Status)) {
+    DEBUG ((DEBUG_ERROR, "UsbPortPowerEnable failed to get PCA9555! (%d)\n", Status));
+  } else {
+    /* USB-C */
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      12, /* vbus5v0_typec_pwr_en */
+      GPIO_MODE_OUTPUT_0
+    );
+
+    gBS->Stall(1200000);
+
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      12, /* vbus5v0_typec_pwr_en */
+      GPIO_MODE_OUTPUT_1
+    );
+
+    /* other USB stuff */
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      5, /* vcc5v0_host */
+      GPIO_MODE_OUTPUT_1
+    );
+
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      4, /* vcc_hub_reset */
+      GPIO_MODE_OUTPUT_1
+    );
+
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      6, /* vcc_hub3_reset */
+      GPIO_MODE_OUTPUT_1
+    );
+
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      7, /* vcc5v0_host3 */
+      GPIO_MODE_OUTPUT_1
+    );
+  }
+}
+
+VOID
+EFIAPI
+Usb2PhyResume (
+  VOID
+  )
+{
+  MmioWrite32(0xfd5d0008, 0x20000000);
+  MmioWrite32(0xfd5d4008, 0x20000000);
+  MmioWrite32(0xfd5d8008, 0x20000000);
+  MmioWrite32(0xfd5dc008, 0x20000000);
+  MmioWrite32(0xfd7f0a10, 0x07000700);
+  MmioWrite32(0xfd7f0a10, 0x07000000);
+}
+
+VOID
+EFIAPI
+PcieIoInit (
+  UINT32 Segment
+  )
+{
+  switch (Segment) {
+  case PCIE_SEGMENT_PCIE30X4:
+    GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT); // PCIE30X4_PERSTN_M1
+    GpioPinSetDirection (4, GPIO_PIN_PC6, GPIO_PIN_OUTPUT); // vcc3v3_pcie30
+    break;
+  case PCIE_SEGMENT_PCIE20L0:
+    GpioPinSetDirection (1, GPIO_PIN_PB4, GPIO_PIN_OUTPUT);
+    break;
+  case PCIE_SEGMENT_PCIE20L1:
+    break;
+  case PCIE_SEGMENT_PCIE20L2:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+PciePowerEn (
+  UINT32 Segment,
+  BOOLEAN Enable
+  )
+{
+  switch (Segment) {
+  case PCIE_SEGMENT_PCIE30X4:
+    GpioPinWrite (4, GPIO_PIN_PC6, Enable); // vcc3v3_pcie30
+    break;
+  case PCIE_SEGMENT_PCIE20L0:
+    break;
+  case PCIE_SEGMENT_PCIE20L1:
+    break;
+  case PCIE_SEGMENT_PCIE20L2:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+PciePeReset (
+  UINT32 Segment,
+  BOOLEAN Enable
+  )
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+  PCA95XX_PROTOCOL *Pca95xxProtocol;
+
+  switch (Segment) {
+  case PCIE_SEGMENT_PCIE30X4:
+    GpioPinWrite (4, GPIO_PIN_PB6, !Enable); // PCIE30X4_PERSTN_M1
+    break;
+  case PCIE_SEGMENT_PCIE20L0:
+    GpioPinWrite (1, GPIO_PIN_PB4, !Enable);
+    break;
+  case PCIE_SEGMENT_PCIE20L1:
+    break;
+  case PCIE_SEGMENT_PCIE20L2:
+    Status = GetPca9555Protocol(&Pca95xxProtocol);
+    if (EFI_ERROR(Status)) {
+      DEBUG ((DEBUG_ERROR, "PciePeReset(L2) failed to get PCA9555! (%d)\n", Status));
+    } else {
+      Pca95xxProtocol->GpioProtocol.Set(
+        &Pca95xxProtocol->GpioProtocol,
+        14, /* PCA_IO1_6 */
+        Enable ? GPIO_MODE_OUTPUT_0 : GPIO_MODE_OUTPUT_1
+      );
+    }
+    break;
+  }
+}
+
+PWM_DATA pwm_data = {
+  .ControllerID = PWM_CONTROLLER3,
+  .ChannelID = PWM_CHANNEL3,
+  .PeriodNs = 50000,
+  .DutyNs = 50000,
+  .Polarity = FALSE,
+}; // PWM15
+
+VOID
+EFIAPI
+PwmFanIoSetup (
+  VOID
+  )
+{
+  GpioPinSetFunction (1, GPIO_PIN_PC6, 0xB); // PWM15_IR_M2
+  RkPwmSetConfig (&pwm_data);
+  RkPwmEnable (&pwm_data);
+}
+
+VOID
+EFIAPI
+PwmFanSetSpeed (
+  IN UINT32 Percentage
+  )
+{
+  pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100;
+  RkPwmSetConfig (&pwm_data);
+}
+
+VOID
+EFIAPI
+PlatformInitLeds (
+  VOID
+  )
+{
+  GpioPinWrite (3, GPIO_PIN_PB2, FALSE);
+  GpioPinSetDirection (3, GPIO_PIN_PB2, GPIO_PIN_OUTPUT);
+}
+
+VOID
+EFIAPI
+PlatformSetStatusLed (
+  IN BOOLEAN Enable
+  )
+{
+  GpioPinWrite (3, GPIO_PIN_PB2, Enable);
+}
+
+VOID
+EFIAPI
+PlatformEarlyInit (
+  VOID
+  )
+{
+  GpioPinSetDirection (4, GPIO_PIN_PB0, GPIO_PIN_OUTPUT); // headphone enable
+  GpioPinWrite (4, GPIO_PIN_PB0, TRUE);
+  GpioPinSetFunction (1, GPIO_PIN_PC4, 0); // headphone detect
+}
--- a/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+++ b/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.inf
@@ -0,0 +1,38 @@
+#
+#  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = RockchipPlatformLib
+  FILE_GUID                      = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RockchipPlatformLib
+  RKPLATLIB_COMMON_DIR           = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  SerialPortLib
+  CruLib
+  GpioLib
+  PWMLib
+
+[Protocols]
+  gPca95xxProtocolGuid
+
+[Sources.common]
+  RockchipPlatformLib.c
+  $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c
--- a/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLibPcaDepex.inf
+++ b/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLibPcaDepex.inf
@@ -0,0 +1,42 @@
+#
+#  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = RockchipPlatformLib
+  FILE_GUID                      = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RockchipPlatformLib
+  RKPLATLIB_COMMON_DIR           = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  SerialPortLib
+  CruLib
+  GpioLib
+  PWMLib
+
+[Protocols]
+  gPca95xxProtocolGuid
+
+[Sources.common]
+  RockchipPlatformLib.c
+  $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c
+
+# Hack to enable use of PCA9555 during PCIe initialization.
+[Depex]
+  gPca95xxProtocolGuid
--- a/edk2-rockchip/Platform/Firefly/ITX-3588J/AcpiTables/AcpiTables.inf
+++ b/edk2-rockchip/Platform/Firefly/ITX-3588J/AcpiTables/AcpiTables.inf
@@ -0,0 +1,58 @@
+#/** @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2019-2021, ARM Limited. All rights reserved.
+#  Copyright (c) Microsoft Corporation. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+  RK_COMMON_ACPI_DIR             = Silicon/Rockchip/RK3588/AcpiTables
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+
+[Sources]
+  Dsdt.asl
+  $(RK_COMMON_ACPI_DIR)/Madt.aslc
+  $(RK_COMMON_ACPI_DIR)/Fadt.aslc
+  $(RK_COMMON_ACPI_DIR)/Gtdt.aslc
+  $(RK_COMMON_ACPI_DIR)/Spcr.aslc
+  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
+  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
+  $(RK_COMMON_ACPI_DIR)/Pptt.aslc
+  
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Rockchip/RockchipPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gRK3588TokenSpaceGuid.PcdI2S0Supported
+  gRK3588TokenSpaceGuid.PcdI2S1Supported
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken
--- a/edk2-rockchip/Platform/Firefly/ITX-3588J/AcpiTables/Dsdt.asl
+++ b/edk2-rockchip/Platform/Firefly/ITX-3588J/AcpiTables/Dsdt.asl
@@ -0,0 +1,41 @@
+/** @file
+ *
+ *  Differentiated System Definition Table (DSDT)
+ *
+ *  Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ *  Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
+ *  Copyright (c) Microsoft Corporation. All rights reserved.
+ *  Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include "AcpiTables.h"
+
+DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588  ", 2)
+{
+  Scope (\_SB_)
+  {
+    include ("DsdtCommon.asl")
+
+    include ("Cpu.asl")
+
+    include ("Pcie.asl")
+    include ("Sata.asl")
+    include ("Emmc.asl")
+    include ("Sdhc.asl")
+    include ("Dma.asl")
+    include ("Gmac0.asl")
+    include ("Gmac1.asl")
+    include ("Gpio.asl")
+    include ("I2c.asl")
+    include ("Uart.asl")
+    // include ("Spi.asl")
+
+    include ("Usb2Host.asl")
+    include ("Usb3Host0.asl")
+    include ("Usb3Host1.asl")
+    include ("Usb3Host2.asl")
+  }
+}
--- a/edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.Modules.fdf.inc
+++ b/edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.Modules.fdf.inc
@@ -0,0 +1,19 @@
+## @file
+#
+#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+#  Copyright (c) 2023, Shimrra Shai <shimmyshai00@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+  # ACPI Support
+  INF RuleOverride = ACPITABLE Platform/Firefly/ITX-3588J/AcpiTables/AcpiTables.inf
+
+  # Device Tree Support
+  FILE FREEFORM = gDtPlatformDefaultDtbFileGuid {
+    SECTION RAW = Platform/Rockchip/DeviceTree/itx-3588j.dtb
+  }
+
+  # Splash screen logo
+  INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf
--- a/edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.dsc
+++ b/edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.dsc
@@ -0,0 +1,34 @@
+## @file
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+#  Copyright (c) 2023, Shimrra Shai <shimmyshai00@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = ITX-3588J
+  PLATFORM_VENDOR                = Firefly
+  PLATFORM_GUID                  = db88a604-ec99-4d39-84d4-af4fa5b5e757
+  PLATFORM_VERSION               = 0.2
+  DSC_SPECIFICATION              = 0x00010019
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  VENDOR_DIRECTORY               = Platform/$(PLATFORM_VENDOR)
+  PLATFORM_DIRECTORY             = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+
+  #
+  # Platform based on ITX-3588J board
+  #
+!include Platform/Firefly/ITX-3588J/ITX-3588J.dsc.inc
+
+  
--- a/edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.dsc.inc
+++ b/edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.dsc.inc
@@ -0,0 +1,120 @@
+## @file
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+#  Copyright (c) 2023, Shimrra Shai <shimmyshai00@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  FLASH_DEFINITION               = Silicon/Rockchip/RK3588/RK3588.fdf
+  RK_PLATFORM_FVMAIN_MODULES     = Platform/Firefly/ITX-3588J/ITX-3588J.Modules.fdf.inc
+
+  #
+  # HYM8563 RTC support
+  # I2C location configured by PCDs below.
+  #
+  DEFINE RK_RTC8563_ENABLE = TRUE
+  
+  #
+  # PCA9555 GPIO extender support
+  # I2C location configured by PCDs below.
+  #
+  DEFINE RK_PCA9555_ENABLE = TRUE
+
+  #
+  # RK3588-based platform
+  #
+!include Silicon/Rockchip/RK3588/RK3588Platform.dsc.inc
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+
+[LibraryClasses.common]
+  RockchipPlatformLib|Platform/Firefly/ITX-3588J/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform.
+#
+################################################################################
+
+[PcdsFixedAtBuild.common]
+  # SMBIOS platform config
+  gRockchipTokenSpaceGuid.PcdPlatformName|"ITX-3588J"
+  gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Firefly"
+  gRockchipTokenSpaceGuid.PcdFamilyName|"ITX"
+  gRockchipTokenSpaceGuid.PcdProductUrl|"https://en.t-firefly.com/product/industry/itx3588j"
+  gRockchipTokenSpaceGuid.PcdDeviceTreeName|"itx-3588j"
+
+  # I2C
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51, 0x21, 0x22 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6, 0x6, 0x6 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE, FALSE, FALSE }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) }
+  gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
+  gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6
+  gRockchipTokenSpaceGuid.PcdPca9555Address|0x21
+  gRockchipTokenSpaceGuid.PcdPca9555Bus|0x6
+
+  #
+  # CPU Performance default values
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_SATA)
+  gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_PCIE)
+  gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3)
+
+  #
+  # USB/DP Combo PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdUsbDpPhy1Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x2, 0x3 }
+  
+  #
+  # GMAC
+  #
+  gRK3588TokenSpaceGuid.PcdGmac0Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdGmac0TxDelay|0x45
+  gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x42
+
+  #
+  # On-Board fan output
+  #
+  gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform.
+#
+################################################################################
+[Components.common]
+  # ACPI Support
+  Platform/Firefly/ITX-3588J/AcpiTables/AcpiTables.inf
+
+  # Splash screen logo
+  $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf
+  
--- a/edk2-rockchip/Platform/Firefly/ITX-3588J/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/Firefly/ITX-3588J/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -0,0 +1,511 @@
+/** @file
+*
+*  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include <Base.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/GpioLib.h>
+#include <Library/RK806.h>
+#include <Library/Rk3588Pcie.h>
+#include <Library/PWMLib.h>
+#include <Soc.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/Pca9555.h>
+
+static struct regulator_init_data rk806_init_data[] = {
+  /* Master PMIC */
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
+ // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+
+  /* No dual PMICs on this platform */
+};
+
+EFI_STATUS
+EFIAPI
+GetPca9555Protocol (
+  IN OUT PCA95XX_PROTOCOL        **Pca95xxProtocl
+  )
+{
+  EFI_HANDLE          *HandleBuffer;
+  EFI_STATUS           Status;
+  UINTN                HandleCount;
+  UINTN                Index;
+
+  /* Locate Handles of all PCA95XX_PROTOCOL producers */
+  Status = gBS->LocateHandleBuffer (ByProtocol,
+                  &gPca95xxProtocolGuid,
+                  NULL,
+                  &HandleCount,
+                  &HandleBuffer);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "%a: Unable to locate handles\n", __FUNCTION__));
+    return Status;
+  }
+  
+  DEBUG ((DEBUG_INFO, 
+          "%a: got %d PCA95XX_PROTOCOLs\n", 
+          __FUNCTION__, 
+          HandleCount));
+  
+  /*
+   * Open Pca95xxProtocl. With EFI_OPEN_PROTOCOL_GET_PROTOCOL attribute
+   * the consumer is not obliged to call CloseProtocol.
+   */
+  Status = gBS->OpenProtocol (HandleBuffer[0],
+                  &gPca95xxProtocolGuid,
+                  (VOID **)Pca95xxProtocl,
+                  HandleBuffer[0],
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+                    
+  return Status;
+}
+
+VOID
+EFIAPI
+SdmmcIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux (microSD socket) */
+  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+}
+
+VOID
+EFIAPI
+SdhciEmmcIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux */
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+}
+
+#define NS_CRU_BASE         0xFD7C0000
+#define CRU_CLKSEL_CON59    0x03EC
+#define CRU_CLKSEL_CON78    0x0438
+
+VOID
+EFIAPI
+Rk806SpiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
+  PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+}
+
+VOID
+EFIAPI
+Rk806Configure (
+  VOID
+  )
+{
+  UINTN RegCfgIndex;
+
+  RK806Init();
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
+    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+}
+
+VOID
+EFIAPI
+SetCPULittleVoltage (
+  IN UINT32 Microvolts
+  )
+{
+  struct regulator_init_data Rk806CpuLittleSupply =
+        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+
+  RK806RegulatorInit(Rk806CpuLittleSupply);
+}
+
+VOID
+EFIAPI
+NorFspiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
+             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
+#define FSPI_M1
+#if defined(FSPI_M0)
+   /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
+#elif defined(FSPI_M1)
+  /*FSPI M1*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
+#else
+  /*FSPI M2*/
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
+#endif
+}
+
+VOID
+EFIAPI
+GmacIomux (
+  IN UINT32 Id
+  )
+{
+  switch (Id) {
+    case 0:
+      /* gmac0 iomux */
+      BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+      BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+      BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+      BUS_IOC->GPIO2C_IOMUX_SEL_L = (0x0FFFUL << 16) | 0x0111;
+      BUS_IOC->GPIO4C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100;
+      BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011;
+
+      /* phy0 reset */
+      GpioPinSetDirection (3, GPIO_PIN_PC7, GPIO_PIN_OUTPUT);
+      break;
+    case 1:
+      /* gmac1 iomux */
+      BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111; /* GMAC1_MCLKINOUT, GMAC1_TXEN, GMAC1_TXD1 */
+      BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111; /* GMAC1_RXD3, GMAC1_RXD2, GMAC1_TXD3, GMAC1_TXD2 */
+      BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; /* GMAC1_TXD0, GMAC1_RXDV_CRS, GMAC1_RXD1 */
+      BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011; /* GMAC1_RXD0, GMAC1_RXCLK, GMAC1_TXCLK */
+      BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100; /* GMAC1_MDIO, GMAC1_MDC */
+
+      /* phy1 reset */
+      GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+GmacIoPhyReset (
+  UINT32   Id,
+  BOOLEAN  Enable
+  )
+{
+  switch (Id) {
+    case 0:
+      /* phy0 reset */
+      GpioPinWrite (3, GPIO_PIN_PC7, !Enable);
+      break;
+    case 1:
+      /* phy1 reset */
+      GpioPinWrite (3, GPIO_PIN_PB7, !Enable);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+NorFspiEnableClock (
+  UINT32 *CruBase
+  )
+{
+  UINTN BaseAddr = (UINTN) CruBase;
+
+  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+}
+
+VOID
+EFIAPI
+I2cIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    /* io mux M2 */
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
+    break;
+  case 1:
+    /* io mux */
+    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
+    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
+    break;
+  case 2:
+    /* io mux */
+    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
+    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
+    PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
+    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    break;
+  case 3:
+    break;
+  case 4:
+    break;
+  case 5:
+    break;
+  case 6:
+    /* io mux M0 */
+    BUS_IOC->GPIO0C_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
+    BUS_IOC->GPIO0D_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
+    PMU2_IOC->GPIO0C_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+UsbPortPowerEnable (
+  VOID
+  )
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+  PCA95XX_PROTOCOL *Pca95xxProtocol;
+  
+  /* On Firefly ITX-3588J this is controlled via the PCA9555. */
+  Status = GetPca9555Protocol(&Pca95xxProtocol);
+  if (EFI_ERROR(Status)) {
+    DEBUG ((DEBUG_ERROR, "Failed to get PCA9555! (%d)\n", Status));
+  } else {
+    /* USB-C */
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      12, /* vbus5v0_typec_pwr_en */
+      GPIO_MODE_OUTPUT_0
+    );
+    
+    gBS->Stall(1200000);
+    
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      12, /* vbus5v0_typec_pwr_en */
+      GPIO_MODE_OUTPUT_1
+    );    
+
+    /* other USB stuff */    
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      5, /* vcc5v0_host */
+      GPIO_MODE_OUTPUT_1
+    );
+
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      4, /* vcc_hub_reset */
+      GPIO_MODE_OUTPUT_1
+    );
+    
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      6, /* vcc_hub3_reset */
+      GPIO_MODE_OUTPUT_1
+    );  
+    
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      7, /* vcc5v0_host3 */
+      GPIO_MODE_OUTPUT_1
+    );
+  }
+}
+
+VOID
+EFIAPI
+Usb2PhyResume (
+  VOID
+  )
+{
+  MmioWrite32(0xfd5d0008, 0x20000000);
+  MmioWrite32(0xfd5d4008, 0x20000000);
+  MmioWrite32(0xfd5d8008, 0x20000000);
+  MmioWrite32(0xfd5dc008, 0x20000000);
+  MmioWrite32(0xfd7f0a10, 0x07000700);
+  MmioWrite32(0xfd7f0a10, 0x07000000);
+}
+
+VOID
+EFIAPI
+PcieIoInit (
+  UINT32 Segment
+  )
+{
+  /* Set reset and power IO to gpio output mode */
+  if(Segment == PCIE_SEGMENT_PCIE30X4) {
+    /* reset */
+    GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
+    /* vcc3v3_pcie30 */
+    GpioPinSetDirection (2, GPIO_PIN_PC5, GPIO_PIN_OUTPUT);
+  }
+}
+
+VOID
+EFIAPI
+PciePowerEn (
+  UINT32 Segment,
+  BOOLEAN Enable
+  )
+{
+  if(Segment == PCIE_SEGMENT_PCIE30X4) {
+    /* vcc3v3_pcie30 */
+    GpioPinWrite (2, GPIO_PIN_PC5, Enable);
+  }
+}
+
+VOID
+EFIAPI
+PciePeReset (
+  UINT32 Segment,
+  BOOLEAN Enable
+  )
+{
+  if(Segment == PCIE_SEGMENT_PCIE30X4) {
+    GpioPinWrite (4, GPIO_PIN_PB6, !Enable);
+  }
+}
+
+PWM_DATA pwm_data = {
+  .ControllerID = PWM_CONTROLLER2,
+  .ChannelID = PWM_CHANNEL3,
+  .PeriodNs = 50000,
+  .DutyNs = 50000,
+  .Polarity = TRUE,
+}; // PWM2_CH3
+
+VOID
+EFIAPI
+PwmFanIoSetup (
+  VOID
+  )
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+  PCA95XX_PROTOCOL *Pca95xxProtocol;
+  
+  Status = GetPca9555Protocol(&Pca95xxProtocol);
+  if (EFI_ERROR(Status)) {
+    DEBUG ((DEBUG_ERROR, "Failed to get PCA9555! (%d)\n", Status));
+  } else {
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      11, /* vcc_fan_pwr_en */
+      GPIO_MODE_OUTPUT_1
+    );
+  }
+}
+
+VOID
+EFIAPI
+PwmFanSetSpeed (
+  IN UINT32 Percentage
+  )
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+  PCA95XX_PROTOCOL *Pca95xxProtocol;
+  
+  Status = GetPca9555Protocol(&Pca95xxProtocol);
+  if (EFI_ERROR(Status)) {
+    DEBUG ((DEBUG_ERROR, "Failed to get PCA9555! (%d)\n", Status));
+  } else {
+    /* (SS) NB: (TBA?) It doesn't *appear* we can regulate the fan speed,
+     *      only power up/down, but I could be wrong
+     */
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      11, /* vcc_fan_pwr_en */
+      (Percentage > 0) ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTPUT_0
+    );
+  }
+}
+
+VOID
+EFIAPI
+PlatformInitLeds (
+  VOID
+  )
+{
+  /* Activate power LED only */
+  GpioPinWrite (1, GPIO_PIN_PB3, TRUE);
+  GpioPinSetDirection (1, GPIO_PIN_PB3, GPIO_PIN_OUTPUT);
+  
+#if 0
+  /* Red off, Green for status, Blue for power */
+  GpioPinWrite (3, GPIO_PIN_PB2, FALSE);
+  GpioPinSetDirection (3, GPIO_PIN_PB2, GPIO_PIN_OUTPUT);
+  GpioPinWrite (3, GPIO_PIN_PC0, FALSE);
+  GpioPinSetDirection (3, GPIO_PIN_PC0, GPIO_PIN_OUTPUT);
+  GpioPinWrite (1, GPIO_PIN_PD5, TRUE);
+  GpioPinSetDirection (1, GPIO_PIN_PD5, GPIO_PIN_OUTPUT);
+#endif
+}
+
+VOID
+EFIAPI
+PlatformSetStatusLed (
+  IN BOOLEAN Enable
+  )
+{
+  /* (SS) does not seem to work and causes errors on I2C complaining
+   * about something being too high
+   */
+#if 0
+  EFI_STATUS Status = EFI_SUCCESS;
+  PCA95XX_PROTOCOL *Pca95xxProtocol;
+  
+  /* On Firefly ITX-3588J this is controlled via the PCA9555. */
+  Status = GetPca9555Protocol(&Pca95xxProtocol);
+  if (EFI_ERROR(Status)) {
+    DEBUG ((DEBUG_ERROR, "Failed to get PCA9555! (%d)\n", Status));
+  } else {
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      3, /* user_led */
+      Enable ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTPUT_0
+    );
+  }
+#endif
+}
+
+VOID
+EFIAPI
+PlatformEarlyInit (
+  VOID
+  )
+{
+
+}
--- a/edk2-rockchip/Platform/Firefly/ITX-3588J/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+++ b/edk2-rockchip/Platform/Firefly/ITX-3588J/Library/RockchipPlatformLib/RockchipPlatformLib.inf
@@ -0,0 +1,38 @@
+#
+#  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = RockchipPlatformLib
+  FILE_GUID                      = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RockchipPlatformLib
+  RKPLATLIB_COMMON_DIR           = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  SerialPortLib
+  CruLib
+  GpioLib
+  PWMLib
+
+[Protocols]
+  gPca95xxProtocolGuid
+
+[Sources.common]
+  RockchipPlatformLib.c
+  $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c
--- a/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/AcpiTables.inf
+++ b/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/AcpiTables.inf
@@ -32,15 +32,6 @@
  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
  $(RK_COMMON_ACPI_DIR)/Pptt.aslc
-  $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl
-  $(RK_COMMON_ACPI_DIR)/Sata0.asl
-  $(RK_COMMON_ACPI_DIR)/Sata1.asl
-  $(RK_COMMON_ACPI_DIR)/Sata2.asl
-  $(RK_COMMON_ACPI_DIR)/Usb2Host.asl

 [Packages]
  ArmPkg/ArmPkg.dec
@@ -49,6 +40,7 @@
  MdeModulePkg/MdeModulePkg.dec
  MdePkg/MdePkg.dec
  Silicon/Rockchip/RockchipPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec

 [FixedPcd]
  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
@@ -59,3 +51,8 @@
  gArmTokenSpaceGuid.PcdGicDistributorBase
  gArmTokenSpaceGuid.PcdGicRedistributorsBase
  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gRK3588TokenSpaceGuid.PcdI2S0Supported
+  gRK3588TokenSpaceGuid.PcdI2S1Supported
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken
--- a/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/Dsdt.asl
+++ b/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/Dsdt.asl
@@ -13,22 +13,41 @@

 #include "AcpiTables.h"

+#define BOARD_I2S0_TPLG "i2s-jack"
+
+#define BOARD_AUDIO_CODEC_HID "ESSX8388"
+#define BOARD_CODEC_I2C "\\_SB.I2C3"
+#define BOARD_CODEC_I2C_ADDR 0x11
+#define BOARD_CODEC_GPIO "\\_SB.GPI1"
+#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PA6
+
 DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588  ", 2)
 {
  Scope (\_SB_)
  {
+    include ("DsdtCommon.asl")
+
    include ("Cpu.asl")

+    include ("Pcie.asl")
+    include ("Sata.asl")
    include ("Emmc.asl")
    include ("Sdhc.asl")
+    include ("Dma.asl")
    include ("Gmac1.asl")
-    // include ("Gpio.asl")
-    // include ("I2c.asl")
+    include ("Gpio.asl")
+    include ("I2c.asl")
    include ("Uart.asl")
    // include ("Spi.asl")

-    include ("Usb1Host.asl")
+    include ("I2s.asl")
+
+    include ("Usb2Host.asl")
    include ("Usb3Host0.asl")
    include ("Usb3Host2.asl")
+
+    Scope (I2C3) {
+      include ("Es8388.asl")
+    }
  }
 }
--- a/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -197,28 +197,33 @@ I2cIomux (
 {
  switch (id) {
  case 0:
-    /* io mux M2 */
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
+    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
+    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
    break;
  case 1:
-    /* io mux */
-    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
-    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
    break;
  case 2:
-    /* io mux */
-    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
-    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
-    PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
-    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
    break;
  case 3:
+    GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0
+    GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0
    break;
  case 4:
+    GpioPinSetFunction(1, GPIO_PIN_PA3, 9); //i2c4_scl_m3 
+    GpioPinSetFunction(1, GPIO_PIN_PA2, 9); //i2c4_sda_m3
    break;
  case 5:
    break;
+  case 6:
+    GpioPinSetFunction(4, GPIO_PIN_PB1, 9); //i2c6_scl_m3
+    GpioPinSetFunction(4, GPIO_PIN_PB0, 9); //i2c6_sda_m3
+    break;
+  case 7:
+    GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0
+    GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0
+    break;
  default:
    break;
  }
@@ -359,5 +364,5 @@ PlatformEarlyInit (
  VOID
  )
 {
-
+  GpioPinSetFunction(1, GPIO_PIN_PA6, 0); //jdet
 }
--- a/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc.inc
+++ b/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc.inc
@@ -48,9 +48,9 @@
  gRockchipTokenSpaceGuid.PcdBoardVendorName|"Firefly"

  # I2C
-  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51 }
-  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x2 }
-  gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51, 0x11 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x2, 0x3 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE, FALSE }
  gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
  gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 }
  gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) }
@@ -89,6 +89,11 @@
  #
  gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE

+  #
+  # I2S
+  #
+  gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.
--- a/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/AcpiTables/AcpiTables.inf
+++ b/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/AcpiTables/AcpiTables.inf
@@ -32,15 +32,6 @@
  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
  $(RK_COMMON_ACPI_DIR)/Pptt.aslc
-  $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl
-  $(RK_COMMON_ACPI_DIR)/Sata0.asl
-  $(RK_COMMON_ACPI_DIR)/Sata1.asl
-  $(RK_COMMON_ACPI_DIR)/Sata2.asl
-  $(RK_COMMON_ACPI_DIR)/Usb2Host.asl

 [Packages]
  ArmPkg/ArmPkg.dec
@@ -49,6 +40,7 @@
  MdeModulePkg/MdeModulePkg.dec
  MdePkg/MdePkg.dec
  Silicon/Rockchip/RockchipPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec

 [FixedPcd]
  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
@@ -59,3 +51,8 @@
  gArmTokenSpaceGuid.PcdGicDistributorBase
  gArmTokenSpaceGuid.PcdGicRedistributorsBase
  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gRK3588TokenSpaceGuid.PcdI2S0Supported
+  gRK3588TokenSpaceGuid.PcdI2S1Supported
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken
--- a/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/AcpiTables/Dsdt.asl
+++ b/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/AcpiTables/Dsdt.asl
@@ -13,21 +13,30 @@

 #include "AcpiTables.h"

+#define BOARD_I2S0_TPLG "i2s-jack"
+
 DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588  ", 2)
 {
  Scope (\_SB_)
  {
+    include ("DsdtCommon.asl")
+
    include ("Cpu.asl")

+    include ("Pcie.asl")
+    include ("Sata.asl")
    include ("Emmc.asl")
    include ("Sdhc.asl")
+    include ("Dma.asl")
    // include ("Gmac.asl")
-    // include ("Gpio.asl")
-    // include ("I2c.asl")
+    include ("Gpio.asl")
+    include ("I2c.asl")
    include ("Uart.asl")
    // include ("Spi.asl")

-    include ("Usb1Host.asl")
+    include ("I2s.asl")
+
+    include ("Usb2Host.asl")
    include ("Usb3Host0.asl")
    include ("Usb3Host1.asl")
    // include ("Usb3Host2.asl")
--- a/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -164,34 +164,28 @@ I2cIomux (
 {
  switch (id) {
  case 0:
-    /* io mux M2 */
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
+    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
+    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
    break;
  case 1:
-    /* io mux */
-    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
-    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
    break;
  case 2:
-    /* io mux */
-    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
-    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
-    PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
-    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
    break;
  case 3:
+    GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0
+    GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0
    break;
  case 4:
    break;
  case 5:
    break;
  case 6:
-    /* io mux M0 */
-    BUS_IOC->GPIO0C_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
-    BUS_IOC->GPIO0D_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
-    PMU2_IOC->GPIO0C_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
+    break;
+  case 7:
    break;
  default:
    break;
@@ -209,6 +203,10 @@ UsbPortPowerEnable (
  GpioPinWrite (4, GPIO_PIN_PB0, TRUE);
  GpioPinSetDirection (4, GPIO_PIN_PB0, GPIO_PIN_OUTPUT);

+  /* Set GPIO4 PC6 output high to power the 4G/LTE module */
+  GpioPinWrite (4, GPIO_PIN_PC6, TRUE);
+  GpioPinSetDirection (4, GPIO_PIN_PC6, GPIO_PIN_OUTPUT);
+
  /* Set GPIO1 PD2 (TYPEC5V_PWREN) output high to power the type-c port */
  GpioPinWrite (1, GPIO_PIN_PD2, TRUE);
  GpioPinSetDirection (1, GPIO_PIN_PD2, GPIO_PIN_OUTPUT);
@@ -352,4 +350,5 @@ PlatformEarlyInit (
  )
 {
  // Configure various things specific to this platform
+  GpioPinSetFunction(1, GPIO_PIN_PC4, 0); //jdet
 }
--- a/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/NanoPC-T6.Modules.fdf.inc
+++ b/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/NanoPC-T6.Modules.fdf.inc
@@ -15,4 +15,4 @@
  }

  # Splash screen logo
-  INF MdeModulePkg/Logo/LogoDxe.inf
+  INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf
--- a/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/NanoPC-T6.dsc
+++ b/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/NanoPC-T6.dsc
@@ -98,6 +98,11 @@
  gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 }
  gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x0 }

+  #
+  # I2S
+  #
+  gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.
@@ -108,4 +113,4 @@
  $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf

  # Splash screen logo
-  MdeModulePkg/Logo/LogoDxe.inf
+  $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf
--- a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/AcpiTables/AcpiTables.inf
+++ b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/AcpiTables/AcpiTables.inf
@@ -32,15 +32,6 @@
  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
  $(RK_COMMON_ACPI_DIR)/Pptt.aslc
-  $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl
-  $(RK_COMMON_ACPI_DIR)/Sata0.asl
-  $(RK_COMMON_ACPI_DIR)/Sata1.asl
-  $(RK_COMMON_ACPI_DIR)/Sata2.asl
-  $(RK_COMMON_ACPI_DIR)/Usb2Host.asl

 [Packages]
  ArmPkg/ArmPkg.dec
@@ -60,3 +51,8 @@
  gArmTokenSpaceGuid.PcdGicDistributorBase
  gArmTokenSpaceGuid.PcdGicRedistributorsBase
  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gRK3588TokenSpaceGuid.PcdI2S0Supported
+  gRK3588TokenSpaceGuid.PcdI2S1Supported
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken
--- a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/AcpiTables/Dsdt.asl
+++ b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/AcpiTables/Dsdt.asl
@@ -17,17 +17,22 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588S", 2)
 {
  Scope (\_SB_)
  {
+    include ("DsdtCommon.asl")
+
    include ("Cpu.asl")

+    include ("Pcie.asl")
+    include ("Sata.asl")
    include ("Emmc.asl")
    include ("Sdhc.asl")
+    include ("Dma.asl")
    include ("Gmac1.asl")
-    //include ("Gpio.asl")
-    //include ("I2c.asl")
+    include ("Gpio.asl")
+    include ("I2c.asl")
    include ("Uart.asl")
    //include ("Spi.asl")

-    include ("Usb1Host.asl")
+    include ("Usb2Host.asl")
    include ("Usb3Host0.asl")
    include ("Usb3Host1.asl")
  }
--- a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -176,34 +176,28 @@ I2cIomux (
 {
  switch (id) {
  case 0:
-    /* io mux M2 */
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
+    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
+    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
    break;
  case 1:
-    /* io mux */
-    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
-    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
    break;
  case 2:
-    /* io mux */
-    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
-    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
-    PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
-    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
    break;
  case 3:
+    GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0
+    GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0
    break;
  case 4:
    break;
  case 5:
    break;
  case 6:
-    /* io mux M0 */
-    BUS_IOC->GPIO0C_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
-    BUS_IOC->GPIO0D_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
-    PMU2_IOC->GPIO0C_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
+    break;
+  case 7:
    break;
  default:
    break;
--- a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/AcpiTables/AcpiTables.inf
+++ b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/AcpiTables/AcpiTables.inf
@@ -32,15 +32,6 @@
  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
  $(RK_COMMON_ACPI_DIR)/Pptt.aslc
-  $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl
-  $(RK_COMMON_ACPI_DIR)/Sata0.asl
-  $(RK_COMMON_ACPI_DIR)/Sata1.asl
-  $(RK_COMMON_ACPI_DIR)/Sata2.asl
-  $(RK_COMMON_ACPI_DIR)/Usb2Host.asl

 [Packages]
  ArmPkg/ArmPkg.dec
@@ -49,6 +40,7 @@
  MdeModulePkg/MdeModulePkg.dec
  MdePkg/MdePkg.dec
  Silicon/Rockchip/RockchipPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec

 [FixedPcd]
  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
@@ -59,3 +51,8 @@
  gArmTokenSpaceGuid.PcdGicDistributorBase
  gArmTokenSpaceGuid.PcdGicRedistributorsBase
  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gRK3588TokenSpaceGuid.PcdI2S0Supported
+  gRK3588TokenSpaceGuid.PcdI2S1Supported
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken
--- a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/AcpiTables/Dsdt.asl
+++ b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/AcpiTables/Dsdt.asl
@@ -17,17 +17,22 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588  ", 2)
 {
  Scope (\_SB_)
  {
+    include ("DsdtCommon.asl")
+
    include ("Cpu.asl")

+    include ("Pcie.asl")
+    include ("Sata.asl")
    include ("Emmc.asl")
    include ("Sdhc.asl")
+    include ("Dma.asl")
    include ("Gmac1.asl")
-    // include ("Gpio.asl")
-    // include ("I2c.asl")
+    include ("Gpio.asl")
+    include ("I2c.asl")
    include ("Uart.asl")
    // include ("Spi.asl")

-    include ("Usb1Host.asl")
+    include ("Usb2Host.asl")
    include ("Usb3Host0.asl")
    include ("Usb3Host2.asl")
  }
--- a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -174,34 +174,28 @@ I2cIomux (
 {
  switch (id) {
  case 0:
-    /* io mux M2 */
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
+    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
+    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
    break;
  case 1:
-    /* io mux */
-    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
-    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
    break;
  case 2:
-    /* io mux */
-    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
-    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
-    PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
-    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
    break;
  case 3:
+    GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0
+    GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0
    break;
  case 4:
    break;
  case 5:
    break;
  case 6:
-    /* io mux M0 */
-    BUS_IOC->GPIO0C_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
-    BUS_IOC->GPIO0D_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
-    PMU2_IOC->GPIO0C_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
+    break;
+  case 7:
    break;
  default:
    break;
--- a/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/AcpiTables/AcpiTables.inf
+++ b/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/AcpiTables/AcpiTables.inf
@@ -0,0 +1,58 @@
+#/** @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2019-2021, ARM Limited. All rights reserved.
+#  Copyright (c) Microsoft Corporation. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+  RK_COMMON_ACPI_DIR             = Silicon/Rockchip/RK3588/AcpiTables
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+
+[Sources]
+  Dsdt.asl
+  $(RK_COMMON_ACPI_DIR)/Madt.aslc
+  $(RK_COMMON_ACPI_DIR)/Fadt.aslc
+  $(RK_COMMON_ACPI_DIR)/Gtdt.aslc
+  $(RK_COMMON_ACPI_DIR)/Spcr.aslc
+  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
+  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
+  $(RK_COMMON_ACPI_DIR)/Pptt.aslc
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Rockchip/RockchipPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gRK3588TokenSpaceGuid.PcdI2S0Supported
+  gRK3588TokenSpaceGuid.PcdI2S1Supported
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken
--- a/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/AcpiTables/Dsdt.asl
+++ b/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/AcpiTables/Dsdt.asl
@@ -0,0 +1,60 @@
+/** @file
+ *
+ *  Differentiated System Definition Table (DSDT)
+ *
+ *  Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ *  Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
+ *  Copyright (c) Microsoft Corporation. All rights reserved.
+ *  Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include "AcpiTables.h"
+
+#define BOARD_I2S0_TPLG "i2s-jack"
+
+#define BOARD_AUDIO_CODEC_HID "ESSX8388"
+#define BOARD_CODEC_I2C "\\_SB.I2C7"
+#define BOARD_CODEC_I2C_ADDR 0x11
+#define BOARD_CODEC_GPIO "\\_SB.GPI1"
+#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PC0
+
+//
+// WORKAROUND:
+// SDMMC may be unreliable at UHS-I speeds.
+//
+#define SDMMC_CAP_DDR50 0
+#define SDMMC_CAP_SDR50 0
+#define SDMMC_CAP_SDR104 0
+
+DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588  ", 2)
+{
+  Scope (\_SB_)
+  {
+    include ("DsdtCommon.asl")
+
+    include ("Cpu.asl")
+
+    include ("Pcie.asl")
+    include ("Sata.asl")
+    include ("Emmc.asl")
+    include ("Sdhc.asl")
+    include ("Dma.asl")
+
+    include ("Gpio.asl")
+    include ("I2c.asl")
+    include ("Uart.asl")
+
+    include ("I2s.asl")
+
+    include ("Usb2Host.asl")
+    include ("Usb3Host0.asl")
+    include ("Usb3Host2.asl")
+
+    Scope (I2C7) {
+      include ("Es8388.asl")
+    }
+  }
+}
--- a/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Drivers/LogoDxe/Logo.bmp
+++ b/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Drivers/LogoDxe/Logo.bmp
--- a/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Drivers/LogoDxe/Logo.c
+++ b/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Drivers/LogoDxe/Logo.c
@@ -0,0 +1,144 @@
+/** @file
+  Logo DXE Driver, install Edkii Platform Logo protocol.
+
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+  Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Protocol/HiiDatabase.h>
+#include <Protocol/GraphicsOutput.h>
+#include <Protocol/HiiImageEx.h>
+#include <Protocol/PlatformLogo.h>
+#include <Protocol/HiiPackageList.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+
+typedef struct {
+  EFI_IMAGE_ID                          ImageId;
+  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
+  INTN                                  OffsetX;
+  INTN                                  OffsetY;
+} LOGO_ENTRY;
+
+STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
+STATIC EFI_HII_HANDLE            mHiiHandle;
+STATIC LOGO_ENTRY                mLogos[] = {
+  {
+    IMAGE_TOKEN (IMG_LOGO),
+    EdkiiPlatformLogoDisplayAttributeCenter,
+    0,
+    0
+  }
+};
+
+/**
+  Load a platform logo image and return its data and attributes.
+
+  @param This              The pointer to this protocol instance.
+  @param Instance          The visible image instance is found.
+  @param Image             Points to the image.
+  @param Attribute         The display attributes of the image returned.
+  @param OffsetX           The X offset of the image regarding the Attribute.
+  @param OffsetY           The Y offset of the image regarding the Attribute.
+
+  @retval EFI_SUCCESS      The image was fetched successfully.
+  @retval EFI_NOT_FOUND    The specified image could not be found.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GetImage (
+  IN     EDKII_PLATFORM_LOGO_PROTOCOL          *This,
+  IN OUT UINT32                                *Instance,
+     OUT EFI_IMAGE_INPUT                       *Image,
+     OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
+     OUT INTN                                  *OffsetX,
+     OUT INTN                                  *OffsetY
+  )
+{
+  UINT32 Current;
+
+  if (Instance == NULL || Image == NULL ||
+      Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Current = *Instance;
+  if (Current >= ARRAY_SIZE (mLogos)) {
+    return EFI_NOT_FOUND;
+  }
+
+  (*Instance)++;
+  *Attribute = mLogos[Current].Attribute;
+  *OffsetX   = mLogos[Current].OffsetX;
+  *OffsetY   = mLogos[Current].OffsetY;
+
+  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
+                        mLogos[Current].ImageId, Image);
+}
+
+STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+  GetImage
+};
+
+/**
+  Entrypoint of this module.
+
+  This function is the entrypoint of this module. It installs the Edkii
+  Platform Logo protocol.
+
+  @param  ImageHandle       The firmware allocated handle for the EFI image.
+  @param  SystemTable       A pointer to the EFI System Table.
+
+  @retval EFI_SUCCESS       The entry point is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeLogo (
+  IN EFI_HANDLE               ImageHandle,
+  IN EFI_SYSTEM_TABLE         *SystemTable
+  )
+{
+  EFI_STATUS                  Status;
+  EFI_HII_PACKAGE_LIST_HEADER *PackageList;
+  EFI_HII_DATABASE_PROTOCOL   *HiiDatabase;
+  EFI_HANDLE                  Handle;
+
+  Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
+                  (VOID **) &HiiDatabase);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
+                  (VOID **) &mHiiImageEx);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Retrieve HII package list from ImageHandle
+  //
+  Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
+                  (VOID **) &PackageList, ImageHandle, NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR,
+      "HII Image Package with logo not found in PE/COFF resource section\n"));
+    return Status;
+  }
+
+  //
+  // Publish HII package list to HII Database.
+  //
+  Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
+                          &mHiiHandle);
+  if (!EFI_ERROR (Status)) {
+    Handle = NULL;
+    Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
+                    &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
+  }
+  return Status;
+}
--- a/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Drivers/LogoDxe/Logo.idf
+++ b/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Drivers/LogoDxe/Logo.idf
@@ -0,0 +1,10 @@
+// @file
+// Platform Logo image definition file.
+//
+// Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+// Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+
+#image IMG_LOGO Logo.bmp
--- a/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Drivers/LogoDxe/LogoDxe.inf
+++ b/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Drivers/LogoDxe/LogoDxe.inf
@@ -0,0 +1,48 @@
+## @file
+#  The default logo bitmap picture shown on setup screen.
+#
+#  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+#  Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = LogoDxe
+  FILE_GUID                      = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = InitializeLogo
+#
+#  This flag specifies whether HII resource section is generated into PE image.
+#
+  UEFI_HII_RESOURCE_SECTION      = TRUE
+
+[Sources]
+  Logo.bmp
+  Logo.c
+  Logo.idf
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  DebugLib
+
+[Protocols]
+  gEfiHiiDatabaseProtocolGuid        ## CONSUMES
+  gEfiHiiImageExProtocolGuid         ## CONSUMES
+  gEfiHiiPackageListProtocolGuid     ## PRODUCES CONSUMES
+  gEdkiiPlatformLogoProtocolGuid     ## PRODUCES
+
+[Depex]
+  gEfiHiiDatabaseProtocolGuid AND
+  gEfiHiiImageExProtocolGuid
--- a/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/FydetabDuo.Modules.fdf.inc
+++ b/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/FydetabDuo.Modules.fdf.inc
@@ -0,0 +1,18 @@
+## @file
+#
+#  Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+  # ACPI Support
+  INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf
+
+  # TODO: Device Tree Support
+  # FILE FREEFORM = gDtPlatformDefaultDtbFileGuid {
+  #   SECTION RAW = Platform/Rockchip/DeviceTree/rk3588s-9tripod-linux.dtb
+  # }
+
+  # Splash screen logo
+  INF $(PLATFORM_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf
--- a/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/FydetabDuo.dsc
+++ b/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/FydetabDuo.dsc
@@ -0,0 +1,113 @@
+## @file
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = FydetabDuo
+  PLATFORM_VENDOR                = FydeInnovations
+  PLATFORM_GUID                  = de3232fb-1716-4f63-a8fe-67a623ae5297
+  PLATFORM_VERSION               = 0.2
+  DSC_SPECIFICATION              = 0x00010019
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  VENDOR_DIRECTORY               = Platform/$(PLATFORM_VENDOR)
+  PLATFORM_DIRECTORY             = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = Silicon/Rockchip/RK3588/RK3588.fdf
+  RK_PLATFORM_FVMAIN_MODULES     = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc
+
+  #
+  # HYM8563 RTC support
+  # I2C location configured by PCDs below.
+  #
+  DEFINE RK_RTC8563_ENABLE = TRUE
+
+  # No HDMI output on this platform
+  DEFINE RK_DW_HDMI_QP_ENABLE = FALSE
+
+  #
+  # RK3588S-based platform
+  #
+!include Silicon/Rockchip/RK3588/RK3588SPlatform.dsc.inc
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+
+[LibraryClasses.common]
+  RockchipPlatformLib|$(PLATFORM_DIRECTORY)/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform.
+#
+################################################################################
+
+[PcdsFixedAtBuild.common]
+  # SMBIOS platform config
+  gRockchipTokenSpaceGuid.PcdPlatformName|"Fydetab Duo"
+  gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Fyde Innovations"
+  gRockchipTokenSpaceGuid.PcdFamilyName|"Fydetab"
+  gRockchipTokenSpaceGuid.PcdProductUrl|"https://fydetabduo.com/"
+  gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588s-12c"
+
+  # I2C
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x50, 0x51, 0x11 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6, 0x6, 0x7 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, FALSE, TRUE, FALSE }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) }
+  gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
+  gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6
+
+  #
+  # CPU Performance default values
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX)
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX)
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX)
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE)
+
+  #
+  # USB/DP Combo PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 }
+
+  #
+  # I2S
+  #
+  gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE
+
+  # SD card detect signal is inverted
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken|TRUE
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform.
+#
+################################################################################
+[Components.common]
+  # ACPI Support
+  $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf
+
+  # Splash screen logo
+  $(PLATFORM_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf
--- a/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Library/RockchipPlatformLib/CsotDsiPanel.c
+++ b/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Library/RockchipPlatformLib/CsotDsiPanel.c
@@ -0,0 +1,171 @@
+/** @file
+ *
+ *  Copyright (c) 2024, Mario Bălănică <mariobalanica02@gmail.com>
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <Uefi.h>
+#include <Protocol/RockchipDsiPanel.h>
+#include <Library/GpioLib.h>
+#include <Library/TimerLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+STATIC UINT8  mCsotDsiInitSequence[] = {
+  0x0a, 0x31, 0x58, 0x11, 0x00, 0x00, 0x89, 0x30, 0x80, 0x0A, 0x00, 0x06, 0x40, 0x00, 0x28, 0x06, 0x40, 0x06, 0x40, 0x02, 0x00, 0x04, 0x21, 0x00, 0x20, 0x05, 0xD0, 0x00, 0x16, 0x00, 0x0C, 0x02, 0x77, 0x00, 0xDA, 0x18, 0x00, 0x10, 0xE0, 0x03, 0x0C, 0x20, 0x00, 0x06, 0x0B, 0x0B, 0x33, 0x0E, 0x1C, 0x2A, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7B, 0x7D, 0x7E, 0x01, 0x02, 0x01, 0x00, 0x09, 0x40, 0x09, 0xBE, 0x19, 0xFC, 0x19, 0xFA, 0x19, 0xF8, 0x1A, 0x38, 0x1A, 0x78, 0x1A, 0xB6, 0x2A, 0xF6, 0x2B, 0x34, 0x2B, 0x74, 0x3B, 0x74, 0x6B, 0x74,
+  0x39, 0x00, 0x06, 0xB9, 0x83, 0x12, 0x1A, 0x55, 0x00,
+  0x39, 0x00, 0x03, 0x51, 0x08, 0x00,
+  0x39, 0x00, 0x02, 0x53, 0x24,
+  0x39, 0x00, 0x1D, 0xB1, 0x1C, 0x6B, 0x6B, 0x27, 0xE7, 0x00, 0x1B, 0x12, 0x20, 0x20, 0x2D, 0x2D, 0x1F, 0x33, 0x31, 0x40, 0xCD, 0xFF, 0x1A, 0x05, 0x15, 0x98, 0x00, 0x88, 0xF9, 0xFF, 0xFF, 0xCF,
+  0x39, 0x00, 0x12, 0xB2, 0x00, 0x6A, 0x40, 0x00, 0x00, 0x14, 0x6E, 0x40, 0x73, 0x02, 0x80, 0x21, 0x21, 0x00, 0x00, 0x10, 0x27,
+  0x39, 0x00, 0x2D, 0xB4, 0x64, 0x00, 0x08, 0x7F, 0x08, 0x7F, 0x00, 0x62, 0x01, 0x72, 0x01, 0x72, 0x00, 0x60, 0x00, 0x00, 0x0A, 0x08, 0x00, 0x29, 0x05, 0x05, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF, 0x14, 0x00, 0x00, 0x0F, 0x0F, 0x2D, 0x2D,
+  0x39, 0x00, 0x04, 0xB6, 0x8F, 0x8F, 0x03,
+  0x39, 0x00, 0x03, 0xBC, 0x06, 0x02,
+  0x39, 0x00, 0x07, 0xC0, 0x34, 0x34, 0x44, 0x00, 0x08, 0xD8,
+  0x39, 0x00, 0x06, 0xC9, 0x00, 0x1E, 0x80, 0xA5, 0x01,
+  0x39, 0x00, 0x07, 0xCB, 0x00, 0x13, 0x38, 0x00, 0x0B, 0x27,
+  0x39, 0x00, 0x02, 0xCC, 0x02,
+  0x39, 0x00, 0x02, 0xD1, 0x07,
+  0x39, 0x00, 0x29, 0xD3, 0x00, 0xC0, 0x08, 0x08, 0x08, 0x04, 0x04, 0x04, 0x14, 0x02, 0x07, 0x07, 0x07, 0x31, 0x13, 0x12, 0x12, 0x12, 0x03, 0x03, 0x03, 0x32, 0x10, 0x11, 0x00, 0x11, 0x32, 0x10, 0x03, 0x00, 0x03, 0x32, 0x10, 0x03, 0x00, 0x03, 0x00, 0x00, 0xFF, 0x00,
+  0x39, 0x00, 0x31, 0xD5, 0x19, 0x19, 0x18, 0x18, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05, 0x06, 0x06, 0x07, 0x07, 0x00, 0x00, 0x01, 0x01, 0x18, 0x18, 0x40, 0x40, 0x20, 0x20, 0x18, 0x18, 0x18, 0x18, 0x40, 0x40, 0x18, 0x18, 0x2F, 0x2F, 0x31, 0x31, 0x2F, 0x2F, 0x31, 0x31, 0x18, 0x18, 0x41, 0x41, 0x41, 0x41,
+  0x39, 0x00, 0x31, 0xD6, 0x40, 0x40, 0x18, 0x18, 0x05, 0x05, 0x04, 0x04, 0x03, 0x03, 0x02, 0x02, 0x01, 0x01, 0x00, 0x00, 0x07, 0x07, 0x06, 0x06, 0x18, 0x18, 0x19, 0x19, 0x20, 0x20, 0x18, 0x18, 0x18, 0x18, 0x40, 0x40, 0x18, 0x18, 0x2F, 0x2F, 0x31, 0x31, 0x2F, 0x2F, 0x31, 0x31, 0x18, 0x18, 0x41, 0x41, 0x41, 0x41,
+  0x39, 0x00, 0x40, 0xE1, 0x11, 0x00, 0x00, 0x89, 0x30, 0x80, 0x0A, 0x00, 0x06, 0x40, 0x00, 0x28, 0x06, 0x40, 0x06, 0x40, 0x02, 0x00, 0x04, 0x21, 0x00, 0x20, 0x05, 0xD0, 0x00, 0x16, 0x00, 0x0C, 0x02, 0x77, 0x00, 0xDA, 0x18, 0x00, 0x10, 0xE0, 0x03, 0x0C, 0x20, 0x00, 0x06, 0x0B, 0x0B, 0x33, 0x0E, 0x1C, 0x2A, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7B, 0x7D, 0x7E, 0x01, 0x02, 0x01, 0x00, 0x09,
+  0x39, 0x00, 0x0C, 0xE7, 0x06, 0x14, 0x14, 0x1A, 0x23, 0x38, 0x00, 0x23, 0x5D, 0x02, 0x02,
+  0x39, 0x00, 0x02, 0xBD, 0x01,
+  0x39, 0x00, 0x04, 0xB1, 0x01, 0x23, 0x00,
+  0x39, 0x00, 0x25, 0xD8, 0x20, 0x00, 0x02, 0x22, 0x00, 0x00, 0x20, 0x00, 0x02, 0x22, 0x00, 0x00, 0x20, 0x00, 0x02, 0x22, 0x00, 0x00, 0x20, 0x00, 0x02, 0x22, 0x00, 0x00, 0x20, 0x00, 0x02, 0x22, 0x00, 0x00, 0x20, 0x00, 0x02, 0x22, 0x00, 0x00,
+  0x39, 0x00, 0x1A, 0xE1, 0x40, 0x09, 0xBE, 0x19, 0xFC, 0x19, 0xFA, 0x19, 0xF8, 0x1A, 0x38, 0x1A, 0x78, 0x1A, 0xB6, 0x2A, 0xF6, 0x2B, 0x34, 0x2B, 0x74, 0x3B, 0x74, 0x6B, 0xF4,
+  0x39, 0x00, 0x0D, 0xE7, 0x02, 0x00, 0x40, 0x01, 0x84, 0x13, 0xBE, 0x14, 0x48, 0x00, 0x04, 0x26,
+  0x39, 0x00, 0x08, 0xCB, 0x1F, 0x55, 0x03, 0x28, 0x0D, 0x08, 0x0A,
+  0x39, 0x00, 0x02, 0xBD, 0x02,
+  0x39, 0x00, 0x0D, 0xD8, 0xAF, 0xFF, 0xFA, 0xFA, 0xBF, 0xEA, 0xAF, 0xFF, 0xFA, 0xFA, 0xBF, 0xEA,
+  0x39, 0x00, 0x23, 0xE7, 0x01, 0x05, 0x01, 0x03, 0x01, 0x03, 0x04, 0x02, 0x02, 0x24, 0x00, 0x24, 0x81, 0x02, 0x40, 0x00, 0x29, 0x60, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x39, 0x00, 0x02, 0xBD, 0x03,
+  0x39, 0x00, 0x19, 0xD8, 0xAA, 0xAA, 0xAA, 0xAB, 0xBF, 0xEA, 0xAA, 0xAA, 0xAA, 0xAB, 0xBF, 0xEA, 0xAF, 0xFF, 0xFA, 0xFA, 0xBF, 0xEA, 0xAF, 0xFF, 0xFA, 0xFA, 0xBF, 0xEA,
+  0x39, 0x00, 0x03, 0xE1, 0x01, 0x3F,
+  0x39, 0x00, 0x02, 0xBD, 0x00,
+  0x39, 0x00, 0x2F, 0xE0, 0x00, 0x13, 0x30, 0x36, 0x40, 0x78, 0x8B, 0x94, 0x95, 0x97, 0x94, 0x94, 0x91, 0x8F, 0x8F, 0x8B, 0x8A, 0x8C, 0x8E, 0xA6, 0xB7, 0x4D, 0x7F, 0x00, 0x13, 0x30, 0x36, 0x40, 0x78, 0x8B, 0x94, 0x95, 0x97, 0x94, 0x94, 0x91, 0x8F, 0x8F, 0x8B, 0x8A, 0x8C, 0x8E, 0xA6, 0xB7, 0x4D, 0x7F,
+  0x39, 0x00, 0x05, 0xBA, 0x70, 0x03, 0xA8, 0x92,
+  0x39, 0x00, 0x25, 0xD8, 0xEA, 0xAA, 0xAA, 0xAE, 0xAA, 0xAF, 0xEA, 0xAA, 0xAA, 0xAE, 0xAA, 0xAF, 0xE0, 0x00, 0x0A, 0x2E, 0x80, 0x2F, 0xE0, 0x00, 0x0A, 0x2E, 0x80, 0x2F, 0xE0, 0x00, 0x0A, 0x2E, 0x80, 0x2F, 0xE0, 0x00, 0x0A, 0x2E, 0x80, 0x2F,
+  0x39, 0x00, 0x02, 0xBD, 0x00,
+  0x39, 0x00, 0x02, 0xC1, 0x01,
+  0x39, 0x00, 0x02, 0xBD, 0x01,
+  0x39, 0x00, 0x3B, 0xC1, 0x00, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C, 0x1F, 0x23, 0x27, 0x2B, 0x2F, 0x33, 0x37, 0x3B, 0x3F, 0x43, 0x47, 0x4B, 0x52, 0x5A, 0x62, 0x69, 0x71, 0x79, 0x81, 0x89, 0x91, 0x98, 0xA1, 0xA9, 0xB1, 0xB9, 0xC1, 0xCA, 0xD2, 0xDA, 0xE3, 0xEA, 0xF4, 0xF8, 0xF9, 0xFB, 0xFD, 0xFF, 0x16, 0xA4, 0x44, 0x16, 0x90, 0xE7, 0xF9, 0x71, 0xA0, 0xF3, 0x1F, 0x40,
+  0x39, 0x00, 0x02, 0xBD, 0x02,
+  0x39, 0x00, 0x3B, 0xC1, 0x00, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C, 0x20, 0x24, 0x28, 0x2D, 0x31, 0x35, 0x39, 0x3D, 0x41, 0x45, 0x49, 0x4D, 0x55, 0x5D, 0x65, 0x6D, 0x75, 0x7D, 0x85, 0x8D, 0x94, 0x9C, 0xA4, 0xAC, 0xB4, 0xBC, 0xC4, 0xCC, 0xD4, 0xDC, 0xE4, 0xEC, 0xF4, 0xF8, 0xFA, 0xFC, 0xFE, 0xFF, 0x06, 0xAA, 0xFC, 0x5B, 0xFF, 0xFF, 0xA4, 0xF9, 0x86, 0xF9, 0x55, 0x40,
+  0x39, 0x00, 0x02, 0xBD, 0x03,
+  0x39, 0x00, 0x3B, 0xC1, 0x00, 0x04, 0x07, 0x0B, 0x0F, 0x13, 0x17, 0x1B, 0x1F, 0x23, 0x27, 0x2C, 0x30, 0x33, 0x38, 0x3C, 0x40, 0x44, 0x48, 0x4C, 0x53, 0x5B, 0x63, 0x6B, 0x72, 0x7A, 0x82, 0x89, 0x91, 0x99, 0xA1, 0xA9, 0xB1, 0xB9, 0xC1, 0xC9, 0xD1, 0xDA, 0xE2, 0xEA, 0xF3, 0xF6, 0xF9, 0xFA, 0xFE, 0xFF, 0x0F, 0x9A, 0xFC, 0x31, 0x40, 0xE4, 0xFB, 0xE9, 0xA3, 0xD9, 0x77, 0x00,
+  0x39, 0x00, 0x02, 0xBD, 0x02,
+  0x39, 0x00, 0x02, 0xBF, 0x72,
+  0x39, 0x00, 0x02, 0xBD, 0x00,
+  0x39, 0x00, 0x08, 0xBF, 0xFD, 0x00, 0x80, 0x9C, 0x10, 0x00, 0x80,
+  0x39, 0x00, 0x02, 0xE9, 0xDE,
+  0x39, 0x00, 0x04, 0xB1, 0xCC, 0x03, 0x00,
+  0x39, 0x00, 0x02, 0xE9, 0x3F,
+  0x39, 0x00, 0x07, 0xD0, 0x07, 0xC0, 0x08, 0x03, 0x11, 0x00,
+  0x39, 0x00, 0x03, 0xB0, 0x00, 0x00,
+  0x39, 0x00, 0x02, 0xE9, 0xCF,
+  0x39, 0x00, 0x02, 0xBA, 0x03,
+  0x39, 0x00, 0x02, 0xE9, 0x3F,
+  // 0x39, 0x00, 0x04, 0xB9, 0x83, 0x12, 0x1A,
+  // 0x39, 0x00, 0x02, 0xC7, 0x00,
+  // 0x39, 0x00, 0x02, 0xCF, 0xFF,
+
+  0x39, 0x00, 0x01, 0x11,
+  0x39, 0x00, 0x01, 0x29,
+};
+
+EFI_STATUS
+EFIAPI
+CsotDsiPanelPrepare (
+  IN ROCKCHIP_DSI_PANEL_PROTOCOL  *This
+  )
+{
+  /* vcc_lcd_en_pin */
+  GpioPinWrite (4, GPIO_PIN_PA3, TRUE);
+  GpioPinSetDirection (4, GPIO_PIN_PA3, GPIO_PIN_OUTPUT);
+  MicroSecondDelay (5 * 1000);
+
+  /* avdd_lcd_gpio */
+  GpioPinWrite (3, GPIO_PIN_PA7, TRUE);
+  GpioPinSetDirection (3, GPIO_PIN_PA7, GPIO_PIN_OUTPUT);
+  MicroSecondDelay (5 * 1000);
+
+  /* avee_lcd_gpio */
+  GpioPinWrite (3, GPIO_PIN_PA6, TRUE);
+  GpioPinSetDirection (3, GPIO_PIN_PA6, GPIO_PIN_OUTPUT);
+  MicroSecondDelay (5 * 1000);
+
+  MicroSecondDelay (120 * 1000);
+
+  /* lcd_rst_gpio (inverted) */
+  GpioPinWrite (3, GPIO_PIN_PC6, FALSE);
+  GpioPinSetDirection (3, GPIO_PIN_PC6, GPIO_PIN_OUTPUT);
+  MicroSecondDelay (120 * 1000);
+
+  /* lcd_rst_gpio (inverted) */
+  GpioPinWrite (3, GPIO_PIN_PC6, TRUE);
+  MicroSecondDelay (120 * 1000);
+
+  return EFI_SUCCESS;
+}
+
+STATIC ROCKCHIP_DSI_PANEL_PROTOCOL  mCsotDsiPanel = {
+  .DsiId       = 0,
+  .DsiLaneRate = 676000,
+  .DsiLanes    = 4,
+  .DsiFlags    = MIPI_DSI_MODE_VIDEO |
+                 MIPI_DSI_MODE_VIDEO_BURST |
+                 MIPI_DSI_MODE_LPM |
+                 MIPI_DSI_MODE_EOT_PACKET,
+  .DsiFormat    = MIPI_DSI_FMT_RGB888,
+  .DscEnable    = TRUE,
+  .SliceWidth   = 1600,
+  .SliceHeight  = 40,
+  .VersionMajor = 1,
+  .VersionMinor = 1,
+
+  .InitSequence       = mCsotDsiInitSequence,
+  .InitSequenceLength = ARRAY_SIZE (mCsotDsiInitSequence),
+
+  .NativeMode         = {
+    .CrtcId     = 2,
+    .OscFreq    = 275000000,
+    .Horizontal = {
+      .Resolution = 1600,
+      .Sync       = 20,
+      .BackPorch  = 40,
+      .FrontPorch = 60
+    },
+    .Vertical         = {
+      .Resolution = 2560,
+      .Sync       = 4,
+      .BackPorch  = 18,
+      .FrontPorch = 112
+    },
+    .HsyncActive     = 0,
+    .VsyncActive     = 0,
+    .DenActive       = 0,
+    .ClkActive       = 0,
+    .VpsConfigModeID = 1
+  },
+
+  .Prepare            = CsotDsiPanelPrepare,
+};
+
+EFI_STATUS
+EFIAPI
+AttachCsotDsiPanel (
+  VOID
+  )
+{
+  EFI_HANDLE  Handle = NULL;
+
+  return gBS->InstallMultipleProtocolInterfaces (
+                &Handle,
+                &gRockchipDsiPanelProtocolGuid,
+                &mCsotDsiPanel,
+                NULL
+                );
+}
--- a/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -0,0 +1,306 @@
+/** @file
+*
+*  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include <Base.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/GpioLib.h>
+#include <Library/RK806.h>
+#include <Library/Rk3588Pcie.h>
+#include <Library/PWMLib.h>
+#include <Soc.h>
+
+static struct regulator_init_data rk806_init_data[] = {
+  /* Master PMIC */
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
+ // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+
+  /* No dual PMICs on this platform */
+};
+
+VOID
+EFIAPI
+SdmmcIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux (microSD socket) */
+  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+}
+
+VOID
+EFIAPI
+SdhciEmmcIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux */
+  /* Do not override, set by earlier boot stages. */
+}
+
+#define NS_CRU_BASE         0xFD7C0000
+#define CRU_CLKSEL_CON59    0x03EC
+#define CRU_CLKSEL_CON78    0x0438
+
+VOID
+EFIAPI
+Rk806SpiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
+  PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+}
+
+VOID
+EFIAPI
+Rk806Configure (
+  VOID
+  )
+{
+  UINTN RegCfgIndex;
+
+  RK806Init();
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
+    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+}
+
+VOID
+EFIAPI
+SetCPULittleVoltage (
+  IN UINT32 Microvolts
+  )
+{
+  struct regulator_init_data Rk806CpuLittleSupply =
+        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+
+  RK806RegulatorInit(Rk806CpuLittleSupply);
+}
+
+VOID
+EFIAPI
+NorFspiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  /* Do not override, set by earlier boot stages. */
+}
+
+VOID
+EFIAPI
+GmacIomux (
+  IN UINT32 Id
+  )
+{
+  /* No GMAC here */
+}
+
+VOID
+EFIAPI
+NorFspiEnableClock (
+  UINT32 *CruBase
+  )
+{
+  UINTN BaseAddr = (UINTN) CruBase;
+
+  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+}
+
+VOID
+EFIAPI
+I2cIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
+    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
+    break;
+  case 1:
+    break;
+  case 2:
+    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
+    break;
+  case 3:
+    GpioPinSetFunction(3, GPIO_PIN_PB7, 9); //i2c3_scl_m1
+    GpioPinSetFunction(3, GPIO_PIN_PC0, 9); //i2c3_sda_m1
+    break;
+  case 4:
+    GpioPinSetFunction(1, GPIO_PIN_PA3, 9); //i2c4_scl_m3
+    GpioPinSetFunction(1, GPIO_PIN_PA2, 9); //i2c4_sda_m3
+    break;
+  case 5:
+    GpioPinSetFunction(1, GPIO_PIN_PB6, 9); //i2c5_scl_m3
+    GpioPinSetFunction(1, GPIO_PIN_PB7, 9); //i2c5_sda_m3
+    break;
+  case 6:
+    GpioPinSetFunction(4, GPIO_PIN_PB1, 9); //i2c6_scl_m3
+    GpioPinSetFunction(4, GPIO_PIN_PB0, 9); //i2c6_sda_m3
+    break;
+  case 7:
+    GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0
+    GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+UsbPortPowerEnable (
+  VOID
+  )
+{
+
+}
+
+VOID
+EFIAPI
+Usb2PhyResume (
+  VOID
+  )
+{
+  MmioWrite32(0xfd5d0008, 0x20000000);
+  MmioWrite32(0xfd5d4008, 0x20000000);
+  MmioWrite32(0xfd5d8008, 0x20000000);
+  MmioWrite32(0xfd5dc008, 0x20000000);
+  MmioWrite32(0xfd7f0a10, 0x07000700);
+  MmioWrite32(0xfd7f0a10, 0x07000000);
+}
+
+VOID
+EFIAPI
+PcieIoInit (
+  UINT32 Segment
+  )
+{
+  /* Set reset to gpio output mode */
+  if(Segment == PCIE_SEGMENT_PCIE20L2) { // AP6275P Wi-Fi
+    GpioPinSetDirection (3, GPIO_PIN_PD1, GPIO_PIN_OUTPUT);
+
+    /* wifi_poweren_gpio */
+    GpioPinSetDirection (0, GPIO_PIN_PC7, GPIO_PIN_OUTPUT);
+  }
+}
+
+VOID
+EFIAPI
+PciePowerEn (
+  UINT32 Segment,
+  BOOLEAN Enable
+  )
+{
+  if(Segment == PCIE_SEGMENT_PCIE20L2) {
+    /* wifi_poweren_gpio */
+    GpioPinWrite (0, GPIO_PIN_PC7, Enable);
+  }
+}
+
+VOID
+EFIAPI
+PciePeReset (
+  UINT32 Segment,
+  BOOLEAN Enable
+  )
+{
+  if(Segment == PCIE_SEGMENT_PCIE20L2) {
+    GpioPinWrite (3, GPIO_PIN_PD1, !Enable);
+  }
+}
+
+VOID
+EFIAPI
+PwmFanIoSetup (
+  VOID
+  )
+{
+
+}
+
+VOID
+EFIAPI
+PwmFanSetSpeed (
+  IN UINT32 Percentage
+  )
+{
+
+}
+
+VOID
+EFIAPI
+PlatformInitLeds (
+  VOID
+  )
+{
+  GpioPinWrite (3, GPIO_PIN_PC2, FALSE);
+  GpioPinSetDirection (3, GPIO_PIN_PC2, GPIO_PIN_OUTPUT);
+}
+
+VOID
+EFIAPI
+PlatformSetStatusLed (
+  IN BOOLEAN Enable
+  )
+{
+  GpioPinWrite (3, GPIO_PIN_PC2, Enable);
+}
+
+extern
+EFI_STATUS
+EFIAPI
+AttachCsotDsiPanel (
+  VOID
+  );
+
+VOID
+EFIAPI
+PlatformEarlyInit (
+  VOID
+  )
+{
+  /* vcc_5v0_en */
+  GpioPinWrite (4, GPIO_PIN_PA2, TRUE);
+  GpioPinSetDirection (4, GPIO_PIN_PA2, GPIO_PIN_OUTPUT);
+
+  GpioPinSetFunction(1, GPIO_PIN_PC0, 0); //jdet
+
+  /* spk-con-gpio */
+  GpioPinWrite (4, GPIO_PIN_PA5, TRUE);
+  GpioPinSetDirection (4, GPIO_PIN_PA5, GPIO_PIN_OUTPUT);
+
+  AttachCsotDsiPanel();
+}
--- a/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+++ b/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Library/RockchipPlatformLib/RockchipPlatformLib.inf
@@ -0,0 +1,41 @@
+#
+#  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = RockchipPlatformLib
+  FILE_GUID                      = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RockchipPlatformLib
+  RKPLATLIB_COMMON_DIR           = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  SerialPortLib
+  CruLib
+  GpioLib
+  PWMLib
+  TimerLib
+  UefiBootServicesTableLib
+
+[Protocols]
+  gRockchipDsiPanelProtocolGuid
+
+[Sources.common]
+  RockchipPlatformLib.c
+  CsotDsiPanel.c
+  $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c
--- a/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/AcpiTables.inf
+++ b/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/AcpiTables.inf
@@ -32,15 +32,6 @@
  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
  $(RK_COMMON_ACPI_DIR)/Pptt.aslc
-  $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl
-  $(RK_COMMON_ACPI_DIR)/Sata0.asl
-  $(RK_COMMON_ACPI_DIR)/Sata1.asl
-  $(RK_COMMON_ACPI_DIR)/Sata2.asl
-  $(RK_COMMON_ACPI_DIR)/Usb2Host.asl

 [Packages]
  ArmPkg/ArmPkg.dec
@@ -49,6 +40,7 @@
  MdeModulePkg/MdeModulePkg.dec
  MdePkg/MdePkg.dec
  Silicon/Rockchip/RockchipPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec

 [FixedPcd]
  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
@@ -59,3 +51,8 @@
  gArmTokenSpaceGuid.PcdGicDistributorBase
  gArmTokenSpaceGuid.PcdGicRedistributorsBase
  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gRK3588TokenSpaceGuid.PcdI2S0Supported
+  gRK3588TokenSpaceGuid.PcdI2S1Supported
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken
--- a/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/Dsdt.asl
+++ b/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/Dsdt.asl
@@ -13,23 +13,42 @@

 #include "AcpiTables.h"

+#define BOARD_I2S0_TPLG "i2s-jack"
+
+#define BOARD_AUDIO_CODEC_HID "ESSX8388"
+#define BOARD_CODEC_I2C "\\_SB.I2C7"
+#define BOARD_CODEC_I2C_ADDR 0x11
+#define BOARD_CODEC_GPIO "\\_SB.GPI1"
+#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PD5
+
 DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588  ", 2)
 {
  Scope (\_SB_)
  {
+    include ("DsdtCommon.asl")
+
    include ("Cpu.asl")

+    include ("Pcie.asl")
+    include ("Sata.asl")
    include ("Emmc.asl")
    include ("Sdhc.asl")
+    include ("Dma.asl")
    include ("Gmac0.asl")
-    // include ("Gpio.asl")
-    // include ("I2c.asl")
+    include ("Gpio.asl")
+    include ("I2c.asl")
    include ("Uart.asl")
    // include ("Spi.asl")

-    include ("Usb1Host.asl")
+    include ("I2s.asl")
+
+    include ("Usb2Host.asl")
    include ("Usb3Host0.asl")
    include ("Usb3Host1.asl")
    include ("Usb3Host2.asl")
+
+    Scope (I2C7) {
+      include ("Es8388.asl")
+    }
  }
 }
--- a/edk2-rockchip/Platform/Hinlink/H88K/H88K.dsc
+++ b/edk2-rockchip/Platform/Hinlink/H88K/H88K.dsc
@@ -63,9 +63,9 @@
  gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588-hinlink-h88k"

  # I2C
-  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51 }
-  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x2 }
-  gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51, 0x11 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x2, 0x7 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE, FALSE }
  gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
  gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 }
  gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) }
@@ -103,6 +103,11 @@
  gRK3588TokenSpaceGuid.PcdGmac0Supported|TRUE
  gRK3588TokenSpaceGuid.PcdGmac0TxDelay|0x44

+  #
+  # I2S
+  #
+  gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.
--- a/edk2-rockchip/Platform/Hinlink/H88K/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/Hinlink/H88K/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -197,27 +197,36 @@ I2cIomux (
 {
  switch (id) {
  case 0:
-    /* io mux M2 */
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
+    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
+    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
    break;
  case 1:
-    /* io mux */
-    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
-    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
+    GpioPinSetFunction(0, GPIO_PIN_PB5, 9); //i2c1_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PB6, 9); //i2c1_sda_m0
    break;
  case 2:
-    /* io mux */
-    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
-    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
-    PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
-    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
    break;
  case 3:
+    GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0
+    GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0
    break;
  case 4:
+    GpioPinSetFunction(3, GPIO_PIN_PA6, 9); //i2c4_scl_m0
+    GpioPinSetFunction(3, GPIO_PIN_PA5, 9); //i2c4_sda_m0
    break;
  case 5:
+    GpioPinSetFunction(3, GPIO_PIN_PC7, 9); //i2c5_scl_m0
+    GpioPinSetFunction(3, GPIO_PIN_PD0, 9); //i2c5_sda_m0
+    break;
+  case 6:
+    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
+    break;
+  case 7:
+    GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0
+    GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0
    break;
  default:
    break;
@@ -373,4 +382,5 @@ PlatformEarlyInit (
  )
 {
  // Configure various things specific to this platform
+  GpioPinSetFunction(1, GPIO_PIN_PD5, 0); //jdet
 }
--- a/edk2-rockchip/Platform/Khadas/Edge2/AcpiTables/AcpiTables.inf
+++ b/edk2-rockchip/Platform/Khadas/Edge2/AcpiTables/AcpiTables.inf
@@ -32,15 +32,6 @@
  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
  $(RK_COMMON_ACPI_DIR)/Pptt.aslc
-  $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl
-  $(RK_COMMON_ACPI_DIR)/Sata0.asl
-  $(RK_COMMON_ACPI_DIR)/Sata1.asl
-  $(RK_COMMON_ACPI_DIR)/Sata2.asl
-  $(RK_COMMON_ACPI_DIR)/Usb2Host.asl

 [Packages]
  ArmPkg/ArmPkg.dec
@@ -49,6 +40,7 @@
  MdeModulePkg/MdeModulePkg.dec
  MdePkg/MdePkg.dec
  Silicon/Rockchip/RockchipPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec

 [FixedPcd]
  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
@@ -59,3 +51,8 @@
  gArmTokenSpaceGuid.PcdGicDistributorBase
  gArmTokenSpaceGuid.PcdGicRedistributorsBase
  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gRK3588TokenSpaceGuid.PcdI2S0Supported
+  gRK3588TokenSpaceGuid.PcdI2S1Supported
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken
--- a/edk2-rockchip/Platform/Khadas/Edge2/AcpiTables/Dsdt.asl
+++ b/edk2-rockchip/Platform/Khadas/Edge2/AcpiTables/Dsdt.asl
@@ -13,22 +13,41 @@

 #include "AcpiTables.h"

+#define BOARD_I2S0_TPLG "i2s-jack"
+
+#define BOARD_AUDIO_CODEC_HID "ESSX8316"
+#define BOARD_CODEC_I2C "\\_SB.I2C3"
+#define BOARD_CODEC_I2C_ADDR 0x10
+#define BOARD_CODEC_GPIO "\\_SB.GPI1"
+#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PD3
+
 DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588  ", 2)
 {
  Scope (\_SB_)
  {
+    include ("DsdtCommon.asl")
+
    include ("Cpu.asl")

+    include ("Pcie.asl")
+    include ("Sata.asl")
    include ("Emmc.asl")
    include ("Sdhc.asl")
+    include ("Dma.asl")
    // include ("Gmac.asl")
-    // include ("Gpio.asl")
-    // include ("I2c.asl")
+    include ("Gpio.asl")
+    include ("I2c.asl")
    include ("Uart.asl")
    // include ("Spi.asl")

-    include ("Usb1Host.asl")
+    include ("I2s.asl")
+
+    include ("Usb2Host.asl")
    include ("Usb3Host0.asl")
    include ("Usb3Host2.asl")
+
+    Scope (I2C3) {
+      include ("Es8388.asl")
+    }
  }
 }
--- a/edk2-rockchip/Platform/Khadas/Edge2/Edge2.dsc
+++ b/edk2-rockchip/Platform/Khadas/Edge2/Edge2.dsc
@@ -62,9 +62,9 @@
  gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588s-khadas-edge2"

  # I2C
-  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51, 0x18 }
-  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x2, 0x2 }
-  gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE, FALSE }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51, 0x18, 0x10 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x2, 0x2, 0x3 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE, FALSE, FALSE }
  gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
  gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 }
  gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) }
@@ -94,6 +94,11 @@
  gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE
  gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 }

+  #
+  # I2S
+  #
+  gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE
+
  #
  # On-Board fan output
  #
--- a/edk2-rockchip/Platform/Khadas/Edge2/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/Khadas/Edge2/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -175,28 +175,31 @@ I2cIomux (
 {
  switch (id) {
  case 0:
-    /* io mux M2 */
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
+    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
+    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
    break;
  case 1:
-    /* io mux */
-    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
-    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
    break;
  case 2:
-    /* io mux */
-    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
-    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
-    PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
-    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
    break;
  case 3:
+    GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0
+    GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0
    break;
  case 4:
+    GpioPinSetFunction(1, GPIO_PIN_PA3, 9); //i2c4_scl_m3
+    GpioPinSetFunction(1, GPIO_PIN_PA2, 9); //i2c4_sda_m3
    break;
  case 5:
    break;
+  case 6:
+    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
+    break;
+  case 7:
+    break;
  default:
    break;
  }
@@ -375,4 +378,6 @@ PlatformEarlyInit (
  )
 {
  // Configure various things specific to this platform
+  GpioPinSetFunction(1, GPIO_PIN_PD3, 0); //jdet
+  GpioPinSetFunction(1, GPIO_PIN_PD0, 0); //spk_con
 }
--- a/edk2-rockchip/Platform/Mekotronics/R58-Mini/AcpiTables/AcpiTables.inf
+++ b/edk2-rockchip/Platform/Mekotronics/R58-Mini/AcpiTables/AcpiTables.inf
@@ -32,15 +32,6 @@
  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
  $(RK_COMMON_ACPI_DIR)/Pptt.aslc
-  $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl
-  $(RK_COMMON_ACPI_DIR)/Sata0.asl
-  $(RK_COMMON_ACPI_DIR)/Sata1.asl
-  $(RK_COMMON_ACPI_DIR)/Sata2.asl
-  $(RK_COMMON_ACPI_DIR)/Usb2Host.asl

 [Packages]
  ArmPkg/ArmPkg.dec
@@ -49,6 +40,7 @@
  MdeModulePkg/MdeModulePkg.dec
  MdePkg/MdePkg.dec
  Silicon/Rockchip/RockchipPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec

 [FixedPcd]
  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
@@ -59,3 +51,8 @@
  gArmTokenSpaceGuid.PcdGicDistributorBase
  gArmTokenSpaceGuid.PcdGicRedistributorsBase
  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gRK3588TokenSpaceGuid.PcdI2S0Supported
+  gRK3588TokenSpaceGuid.PcdI2S1Supported
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken
--- a/edk2-rockchip/Platform/Mekotronics/R58-Mini/AcpiTables/Dsdt.asl
+++ b/edk2-rockchip/Platform/Mekotronics/R58-Mini/AcpiTables/Dsdt.asl
@@ -17,17 +17,22 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588  ", 2)
 {
  Scope (\_SB_)
  {
+    include ("DsdtCommon.asl")
+
    include ("Cpu.asl")

+    include ("Pcie.asl")
+    include ("Sata.asl")
    include ("Emmc.asl")
    include ("Sdhc.asl")
+    include ("Dma.asl")
    include ("Gmac0.asl")
-    // include ("Gpio.asl")
-    // include ("I2c.asl")
+    include ("Gpio.asl")
+    include ("I2c.asl")
    include ("Uart.asl")
    // include ("Spi.asl")

-    include ("Usb1Host.asl")
+    include ("Usb2Host.asl")
    include ("Usb3Host0.asl")
    include ("Usb3Host1.asl")
    include ("Usb3Host2.asl")
--- a/edk2-rockchip/Platform/Mekotronics/R58-Mini/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/Mekotronics/R58-Mini/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -196,34 +196,28 @@ I2cIomux (
 {
  switch (id) {
  case 0:
-    /* io mux M2 */
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
+    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
+    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
    break;
  case 1:
-    /* io mux */
-    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
-    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
    break;
  case 2:
-    /* io mux */
-    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
-    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
-    PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
-    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
    break;
  case 3:
    break;
  case 4:
    break;
  case 5:
+    GpioPinSetFunction(1, GPIO_PIN_PB6, 9); //i2c5_scl_m3
+    GpioPinSetFunction(1, GPIO_PIN_PB7, 9); //i2c5_sda_m3
    break;
  case 6:
-    /* io mux M0 */
-    BUS_IOC->GPIO0C_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
-    BUS_IOC->GPIO0D_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
-    PMU2_IOC->GPIO0C_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
+    break;
+  case 7:
    break;
  default:
    break;
--- a/edk2-rockchip/Platform/Mekotronics/R58X/AcpiTables/AcpiTables.inf
+++ b/edk2-rockchip/Platform/Mekotronics/R58X/AcpiTables/AcpiTables.inf
@@ -32,15 +32,6 @@
  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
  $(RK_COMMON_ACPI_DIR)/Pptt.aslc
-  $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl
-  $(RK_COMMON_ACPI_DIR)/Sata0.asl
-  $(RK_COMMON_ACPI_DIR)/Sata1.asl
-  $(RK_COMMON_ACPI_DIR)/Sata2.asl
-  $(RK_COMMON_ACPI_DIR)/Usb2Host.asl

 [Packages]
  ArmPkg/ArmPkg.dec
@@ -49,6 +40,7 @@
  MdeModulePkg/MdeModulePkg.dec
  MdePkg/MdePkg.dec
  Silicon/Rockchip/RockchipPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec

 [FixedPcd]
  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
@@ -59,3 +51,8 @@
  gArmTokenSpaceGuid.PcdGicDistributorBase
  gArmTokenSpaceGuid.PcdGicRedistributorsBase
  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gRK3588TokenSpaceGuid.PcdI2S0Supported
+  gRK3588TokenSpaceGuid.PcdI2S1Supported
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken
--- a/edk2-rockchip/Platform/Mekotronics/R58X/AcpiTables/Dsdt.asl
+++ b/edk2-rockchip/Platform/Mekotronics/R58X/AcpiTables/Dsdt.asl
@@ -13,24 +13,43 @@

 #include "AcpiTables.h"

+#define BOARD_I2S0_TPLG "i2s-jack"
+
+#define BOARD_AUDIO_CODEC_HID "ESSX8388"
+#define BOARD_CODEC_I2C "\\_SB.I2C3"
+#define BOARD_CODEC_I2C_ADDR 0x10
+#define BOARD_CODEC_GPIO "\\_SB.GPI3"
+#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PB2
+
 DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588  ", 2)
 {
  Scope (\_SB_)
  {
+    include ("DsdtCommon.asl")
+
    include ("Cpu.asl")

+    include ("Pcie.asl")
+    include ("Sata.asl")
    include ("Emmc.asl")
    include ("Sdhc.asl")
+    include ("Dma.asl")
    include ("Gmac0.asl")
    include ("Gmac1.asl")
-    // include ("Gpio.asl")
-    // include ("I2c.asl")
+    include ("Gpio.asl")
+    include ("I2c.asl")
    include ("Uart.asl")
    // include ("Spi.asl")

-    include ("Usb1Host.asl")
+    include ("I2s.asl")
+
+    include ("Usb2Host.asl")
    include ("Usb3Host0.asl")
    include ("Usb3Host1.asl")
    include ("Usb3Host2.asl")
+
+    Scope (I2C3) {
+      include ("Es8388.asl")
+    }
  }
 }
--- a/edk2-rockchip/Platform/Mekotronics/R58X/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/Mekotronics/R58X/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -211,34 +211,31 @@ I2cIomux (
 {
  switch (id) {
  case 0:
-    /* io mux M2 */
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
+    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
+    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
    break;
  case 1:
-    /* io mux */
-    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
-    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
    break;
  case 2:
-    /* io mux */
-    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
-    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
-    PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
-    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
    break;
  case 3:
+    GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0
+    GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0
    break;
  case 4:
    break;
  case 5:
+    GpioPinSetFunction(1, GPIO_PIN_PB6, 9); //i2c5_scl_m3
+    GpioPinSetFunction(1, GPIO_PIN_PB7, 9); //i2c5_sda_m3
    break;
  case 6:
-    /* io mux M0 */
-    BUS_IOC->GPIO0C_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
-    BUS_IOC->GPIO0D_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
-    PMU2_IOC->GPIO0C_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
+    break;
+  case 7:
+    break;
  default:
    break;
  }
@@ -383,5 +380,5 @@ PlatformEarlyInit (
  VOID
  )
 {
-
+  GpioPinSetFunction(3, GPIO_PIN_PB2, 0); //jdet
 }
--- a/edk2-rockchip/Platform/Mekotronics/R58X/R58X.dsc
+++ b/edk2-rockchip/Platform/Mekotronics/R58X/R58X.dsc
@@ -63,9 +63,9 @@
  gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588-blueberry-edge-v12-linux"

  # I2C
-  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51 }
-  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6 }
-  gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51, 0x10 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6, 0x3 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE, FALSE }
  gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
  gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 }
  gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) }
@@ -106,7 +106,12 @@
  gRK3588TokenSpaceGuid.PcdGmac0Supported|TRUE
  gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE
  gRK3588TokenSpaceGuid.PcdGmac0TxDelay|0x44
-  gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x42
+  gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x42 
+
+  #
+  # I2S
+  #
+  gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE

 ################################################################################
 #
--- a/edk2-rockchip/Platform/Mixtile/Blade3/AcpiTables/AcpiTables.inf
+++ b/edk2-rockchip/Platform/Mixtile/Blade3/AcpiTables/AcpiTables.inf
@@ -32,15 +32,6 @@
  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
  $(RK_COMMON_ACPI_DIR)/Pptt.aslc
-  $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl
-  $(RK_COMMON_ACPI_DIR)/Sata0.asl
-  $(RK_COMMON_ACPI_DIR)/Sata1.asl
-  $(RK_COMMON_ACPI_DIR)/Sata2.asl
-  $(RK_COMMON_ACPI_DIR)/Usb2Host.asl

 [Packages]
  ArmPkg/ArmPkg.dec
@@ -49,6 +40,7 @@
  MdeModulePkg/MdeModulePkg.dec
  MdePkg/MdePkg.dec
  Silicon/Rockchip/RockchipPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec

 [FixedPcd]
  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
@@ -59,3 +51,8 @@
  gArmTokenSpaceGuid.PcdGicDistributorBase
  gArmTokenSpaceGuid.PcdGicRedistributorsBase
  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gRK3588TokenSpaceGuid.PcdI2S0Supported
+  gRK3588TokenSpaceGuid.PcdI2S1Supported
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken
--- a/edk2-rockchip/Platform/Mixtile/Blade3/AcpiTables/Dsdt.asl
+++ b/edk2-rockchip/Platform/Mixtile/Blade3/AcpiTables/Dsdt.asl
@@ -17,17 +17,22 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588  ", 2)
 {
  Scope (\_SB_)
  {
+    include ("DsdtCommon.asl")
+
    include ("Cpu.asl")

+    include ("Pcie.asl")
+    include ("Sata.asl")
    include ("Emmc.asl")
    include ("Sdhc.asl")
+    include ("Dma.asl")
    // include ("Gmac.asl")
-    // include ("Gpio.asl")
-    // include ("I2c.asl")
+    include ("Gpio.asl")
+    include ("I2c.asl")
    include ("Uart.asl")
    // include ("Spi.asl")

-    include ("Usb1Host.asl")
+    include ("Usb2Host.asl")
    include ("Usb3Host0.asl")
    include ("Usb3Host1.asl")
    include ("Usb3Host2.asl")
--- a/edk2-rockchip/Platform/Mixtile/Blade3/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/Mixtile/Blade3/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -165,27 +165,30 @@ I2cIomux (
 {
  switch (id) {
  case 0:
-    /* io mux M2 */
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
+    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
+    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
    break;
  case 1:
-    /* io mux */
-    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
-    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
+    GpioPinSetFunction(0, GPIO_PIN_PD4, 9); //i2c1_scl_m2
+    GpioPinSetFunction(0, GPIO_PIN_PD5, 9); //i2c1_sda_m2
    break;
  case 2:
-    /* io mux */
-    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
-    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
-    PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
-    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
    break;
  case 3:
    break;
  case 4:
+    GpioPinSetFunction(3, GPIO_PIN_PA6, 9); //i2c4_scl_m0
+    GpioPinSetFunction(3, GPIO_PIN_PA5, 9); //i2c4_sda_m0
    break;
  case 5:
+    GpioPinSetFunction(1, GPIO_PIN_PB6, 9); //i2c5_scl_m3
+    GpioPinSetFunction(1, GPIO_PIN_PB7, 9); //i2c5_sda_m3
+    break;
+  case 6:
+    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
+    break;
+  case 7:
    break;
  default:
    break;
--- a/edk2-rockchip/Platform/OrangePi/OrangePi5/AcpiTables/AcpiTables.inf
+++ b/edk2-rockchip/Platform/OrangePi/OrangePi5/AcpiTables/AcpiTables.inf
@@ -32,15 +32,6 @@
  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
  $(RK_COMMON_ACPI_DIR)/Pptt.aslc
-  $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl
-  $(RK_COMMON_ACPI_DIR)/Sata0.asl
-  $(RK_COMMON_ACPI_DIR)/Sata1.asl
-  $(RK_COMMON_ACPI_DIR)/Sata2.asl
-  $(RK_COMMON_ACPI_DIR)/Usb2Host.asl

 [Packages]
  ArmPkg/ArmPkg.dec
@@ -49,6 +40,7 @@
  MdeModulePkg/MdeModulePkg.dec
  MdePkg/MdePkg.dec
  Silicon/Rockchip/RockchipPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec

 [FixedPcd]
  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
@@ -59,3 +51,8 @@
  gArmTokenSpaceGuid.PcdGicDistributorBase
  gArmTokenSpaceGuid.PcdGicRedistributorsBase
  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gRK3588TokenSpaceGuid.PcdI2S0Supported
+  gRK3588TokenSpaceGuid.PcdI2S1Supported
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken
--- a/edk2-rockchip/Platform/OrangePi/OrangePi5/AcpiTables/Dsdt.asl
+++ b/edk2-rockchip/Platform/OrangePi/OrangePi5/AcpiTables/Dsdt.asl
@@ -13,22 +13,41 @@

 #include "AcpiTables.h"

+#define BOARD_I2S1_TPLG "i2s-jack"
+
+#define BOARD_AUDIO_CODEC_HID "ESSX8388"
+#define BOARD_CODEC_I2C "\\_SB.I2C6"
+#define BOARD_CODEC_I2C_ADDR 0x10
+#define BOARD_CODEC_GPIO "\\_SB.GPI1"
+#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PD5
+
 DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588  ", 2)
 {
  Scope (\_SB_)
  {
+    include ("DsdtCommon.asl")
+
    include ("Cpu.asl")

+    include ("Pcie.asl")
+    include ("Sata.asl")
    // include ("Emmc.asl")
    include ("Sdhc.asl")
+    include ("Dma.asl")
    include ("Gmac1.asl")
-    // include ("Gpio.asl")
-    // include ("I2c.asl")
+    include ("Gpio.asl")
+    include ("I2c.asl")
    include ("Uart.asl")
    // include ("Spi.asl")

-    include ("Usb1Host.asl")
+    include ("I2s.asl")
+
+    include ("Usb2Host.asl")
    include ("Usb3Host0.asl")
    include ("Usb3Host2.asl")
+
+    Scope (I2C6) {
+      include ("Es8388.asl")
+    }
  }
 }
--- a/edk2-rockchip/Platform/OrangePi/OrangePi5/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/OrangePi/OrangePi5/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -177,32 +177,30 @@ I2cIomux (
 {
  switch (id) {
  case 0:
-    /* io mux M2 */
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
+    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
+    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
    break;
  case 1:
-    /* io mux */
-    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
-    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
    break;
  case 2:
-    /* io mux */
-    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
-    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
-    PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
-    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
    break;
  case 3:
    break;
  case 4:
+    GpioPinSetFunction(3, GPIO_PIN_PA6, 9); //i2c4_scl_m0
+    GpioPinSetFunction(3, GPIO_PIN_PA5, 9); //i2c4_sda_m0
    break;
  case 5:
    break;
  case 6:
-    /* io mux M3 */
-    BUS_IOC->GPIO4B_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0090;
-    BUS_IOC->GPIO4B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
+    GpioPinSetFunction(4, GPIO_PIN_PB1, 9); //i2c6_scl_m3
+    GpioPinSetFunction(4, GPIO_PIN_PB0, 9); //i2c6_sda_m3
+    break;
+  case 7:
+    GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0
+    GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0
    break;
  default:
    break;
@@ -329,4 +327,6 @@ PlatformEarlyInit (
  )
 {
  // Configure various things specific to this platform
+  
+  GpioPinSetFunction(1, GPIO_PIN_PD5, 0); //jdet
 }
--- a/edk2-rockchip/Platform/OrangePi/OrangePi5/OrangePi5.dsc
+++ b/edk2-rockchip/Platform/OrangePi/OrangePi5/OrangePi5.dsc
@@ -63,9 +63,9 @@
  gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588s-orangepi-5"

  # I2C
-  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51 }
-  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6 }
-  gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51, 0x10 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6, 0x6 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE, FALSE }
  gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
  gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 }
  gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) }
@@ -99,6 +99,11 @@
  gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE
  gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x42

+  #
+  # I2S
+  #
+  gRK3588TokenSpaceGuid.PcdI2S1Supported|TRUE
+
  #
  # On-Board fan output
  #
--- a/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/AcpiTables/AcpiTables.inf
+++ b/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/AcpiTables/AcpiTables.inf
@@ -32,15 +32,6 @@
  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
  $(RK_COMMON_ACPI_DIR)/Pptt.aslc
-  $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl
-  $(RK_COMMON_ACPI_DIR)/Sata0.asl
-  $(RK_COMMON_ACPI_DIR)/Sata1.asl
-  $(RK_COMMON_ACPI_DIR)/Sata2.asl
-  $(RK_COMMON_ACPI_DIR)/Usb2Host.asl

 [Packages]
  ArmPkg/ArmPkg.dec
@@ -49,6 +40,7 @@
  MdeModulePkg/MdeModulePkg.dec
  MdePkg/MdePkg.dec
  Silicon/Rockchip/RockchipPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec

 [FixedPcd]
  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
@@ -59,3 +51,8 @@
  gArmTokenSpaceGuid.PcdGicDistributorBase
  gArmTokenSpaceGuid.PcdGicRedistributorsBase
  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gRK3588TokenSpaceGuid.PcdI2S0Supported
+  gRK3588TokenSpaceGuid.PcdI2S1Supported
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken
--- a/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/AcpiTables/Dsdt.asl
+++ b/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/AcpiTables/Dsdt.asl
@@ -13,22 +13,41 @@

 #include "AcpiTables.h"

+#define BOARD_I2S0_TPLG "i2s-jack"
+
+#define BOARD_AUDIO_CODEC_HID "ESSX8388"
+#define BOARD_CODEC_I2C "\\_SB.I2C7"
+#define BOARD_CODEC_I2C_ADDR 0x11
+#define BOARD_CODEC_GPIO "\\_SB.GPI1"
+#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PD3
+
 DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588  ", 2)
 {
  Scope (\_SB_)
  {
+    include ("DsdtCommon.asl")
+
    include ("Cpu.asl")

+    include ("Pcie.asl")
+    include ("Sata.asl")
    include ("Emmc.asl")
    include ("Sdhc.asl")
+    include ("Dma.asl")
    // include ("Gmac.asl")
-    // include ("Gpio.asl")
-    // include ("I2c.asl")
+    include ("Gpio.asl")
+    include ("I2c.asl")
    include ("Uart.asl")
    // include ("Spi.asl")

-    include ("Usb1Host.asl")
+    include ("I2s.asl")
+
+    include ("Usb2Host.asl")
    include ("Usb3Host0.asl")
    include ("Usb3Host1.asl")
+
+    Scope (I2C7) {
+      include ("Es8388.asl")
+    }
  }
 }
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Mario Bălănică	0d37e7250e	ACPI: Add broken-cd property for SDMMC Missed this change. The Windows driver needs to be made aware that the internal card detect register cannot be trusted. But card detection still works there, because sdport keeps track of the state based on the GPIO interrupt. Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-07-11 04:03:19 +03:00
Mario Bălănică	416b2fa11b	FydetabDuo: Disable SD card detection There's a trick to boot from SD on this tablet: the card tray has to be opened slightly, just enough so that the card detect pin is released while the card itself still makes contact with the data pins. Given that both states can mean "connected", UEFI should no longer rely on this signal to detect card presence. Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-07-10 20:18:00 +03:00
Mario Bălănică	915093ff4b	FydetabDuo: Disable UHS-I speed modes for SDMMC in ACPI Windows may fail to load with UNMOUNTABLE_BOOT_DEVICE otherwise. I was able to boot mostly fine until today, but now it crashes constantly. It appears there are some signal integrity issues at SDR50/104, no matter the clock rate (tried lowering it to 150, 100 and 50 MHz). Tuning seems to complete okay, but after a CMD18 it starts going haywire with Data/Command CRC errors and can't recover. Tested again on an Indiedroid Nova and the issue does not reproduce. So unfortunately we have to limit the speed here to HS 25 MB/s. Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-07-10 19:41:15 +03:00
Mario Bălănică	19360cf5b2	Update README.md Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-07-09 05:50:16 +03:00
Mario Bălănică	066de1179b	FydetabDuo: Add display support The panel is a 1600x2560 CSOT PNC357DB1-4. Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-07-09 05:22:31 +03:00
Mario Bălănică	9797896a6d	Add MIPI DSI support Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-07-09 05:22:30 +03:00
Mario Bălănică	f8768a8a02	Add initial support for Fydetab Duo The DSI panel is not yet working. Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-07-09 05:22:29 +03:00
Mario Bălănică	c02b333c22	RkSdmmcDxe: Add option for inverted card detect signal It's worth noting that when the detection logic is inverted, the boot ROM assumes the SD card is disconnected and skips booting from it altogether. Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-07-09 05:22:29 +03:00
Mario Bălănică	1b6ef19bf3	RkSdmmcPlatformLib: Ensure JTAG is disabled If the card is not connected at boot, force_jtag in SYS_GRF_SOC_CON6 may remain set. This muxes DAT2/DAT3 over to JTAG instead of SDMMC, preventing SD card operation in 4-bit mode. Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-07-09 05:22:24 +03:00
Mario Bălănică	0bfa31ff0e	Update README.md Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-06-24 03:32:36 +03:00
Mario Bălănică	83e1b9bbea	rkbin: Downgrade SPL back to v1.12 SD card driver in v1.13 throws errors and won't boot anymore. Tested on Indiedroid Nova. Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-06-24 00:16:36 +03:00
Mario Bălănică	9678f643ec	Update to latest rkbin * ATF (BL31) from v1.40 to v1.45 * OP-TEE (BL32) from v1.13 to v1.15 * ddrbin from v1.12 to v1.16 * U-Boot SPL from v1.12 to v1.13 Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-06-24 00:02:48 +03:00
Mario Bălănică	359354e0bb	Enable Arm TRNG service Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-06-23 22:49:05 +03:00
Mario Bălănică	8e7e736365	Update TF-A submodule Adds support for TRNG SMC service. Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-06-23 22:46:44 +03:00
Mario Bălănică	1bb15338fc	Fix networking after EDK2 update Latest EDK2 requires a proper RNG driver in order to use network boot (CVE-2023-45237). We ought to implement one, but for now bypass this check. Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-06-23 04:01:20 +03:00
Mario Bălănică	f0727b8e35	Update to latest EDK2 edk2-stable202405 Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-06-23 01:33:00 +03:00
Mario Bălănică	02d150251c	DwcSdhciDxe: Disable ADMA2 to avoid data corruption This controller has the limitation that a single ADMA2 descriptor cannot cross 128 MB boundaries and must be split. This would require a patch in SdMmcPciHcDxe, but SDMA works fine for the time being. Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-06-22 20:10:08 +03:00
Mario Bălănică	053cf714a7	ACPI: Prepare SD controller support for Windows Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-06-18 21:17:17 +03:00
Mario Bălănică	dd0b22f5fd	ACPI: Add SCMI clock and voltage domain methods Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-06-18 20:59:23 +03:00
Mario Bălănică	bffaee6af4	Update TF-A submodule This enables the upcoming SCMI support in ACPI and SD/MMC clock & voltage control for Windows. Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-06-18 19:49:41 +03:00
Mario Bălănică	de6b6f843e	Switch to open-source TF-A Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-06-18 19:34:52 +03:00
Mario Bălănică	ee52a5a8ce	PlatformLib: Fix overlapping memory map regions Regions should be clearly delimited so attributes don't mix up. Also ensure that the TF-A region containing SCMI shared memory is not added to the UEFI map. This addresses an issue where attributes seem to change at runtime and the mismatch leads to a loss of cache coherency between EL3 and lower level accesses. TF-A maps the shared memory as Device memory, so it needs to remain at least non-cacheable here too (Device is not exactly possible due to unaligned accesses from ArmScmiDxe). This could actually just be normal write-back memory, since it's not shared with any external clients, but whatever. Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-06-18 19:34:51 +03:00
Mario Bălănică	1b9a49f624	RK3588Dxe: Enable M.2 slot power in SATA mode Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-06-18 19:29:56 +03:00
Mario Bălănică	b1c1c2cd13	SdramLib: Fix detection for LPDDR4X and LPDDR5 Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-06-18 19:29:48 +03:00
Jianfeng Liu	1fa01b9ea1	Add support for rock-5-itx (#138 )	2024-04-25 21:15:54 +03:00
silime	a39e76ff86	Platform/ROCK5B: Enable WIFI Bluetooth regulator (#134 )	2024-04-05 17:38:12 +03:00
Ricardo Pardini	956bbdc73b	update DTBs from Armbian rk-6.1-rkr1 (#133 ) Signed-off-by: Ricardo Pardini <ricardo@pardini.net>	2024-04-01 17:29:13 +03:00
Doug Cook	94a242cf05	New platform: AIO-3588q (#130 )	2024-03-26 23:50:10 +02:00
Mario Bălănică	779b6dc5bc	workflows: Update actions	2024-03-16 22:42:39 +02:00
Mario Bălănică	06a6d8843f	Clean-up build.sh Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-03-16 22:42:25 +02:00
Mario Bălănică	3e5a3c8c06	ACPI: Unconditionally mask off PCIe native hot plug control We don't actually support hot plug and this causes lockups in Windows. Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-03-02 00:01:00 +02:00
Mario Bălănică	ba8fbeea98	Rk3588PciHostBridgeLib: Try to avoid a potential bus hang up Some devices that appear to have working CFG0 filtering (my VIA VL805) do not actually like config cycles at B/D/F 01:01.0 and may screw up further accesses (e.g. read 0xFFFFFFFF at valid locations) + eventually hang up the bus after a few more attempts. Checking for mirroring in this case is asking for trouble, but it seems that trying 01:01.0 first and then 01:00.0 avoids the problem in UEFI. OSes that rely on single device ECAM mode in ACPI are still going to hang up the system, since they scan the entire affected bus. Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-02-13 01:53:04 +02:00
Mario Bălănică	4b915e69f5	ACPI: Support PCIe root port and switches in Windows and Linux To deal with the broken ECAM on this platform, reuse some existing OS workarounds: - for Windows: "NXPMX6" OEM ID in FADT and split MCFG entries for root port and main config space. - for Linux: "AMAZON" OEM ID + "GRAVITON" OEM Table ID in MCFG. An "AMZN0001" device with _UID matching the RC segment number returns the root port's DBI address in _CRS. Both workarounds filter device > 0 on primary and secondary buses of RP to hide ghost and duplicate devices. The compatibility mode used can be configured in the setup menu. Default is "Auto (NXPMX6 + Single Device)", which selects the NXPMX6 mode when Windows is booted and the classic single device/bus mode for other OSes, since it's the most compatible one. Also move the PCIe and SATA SSDT definitions in DSDT and patch _STA instead to disable the unnecessary controllers. Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-02-11 21:48:46 +02:00
Mario Bălănică	ccf967ed7a	ACPI: Expose EHCI unconditionally But detect the OS booted and hide the PNP0D20 ID for Windows, so we don't end up binding to the inbox driver package and crashing. The fixed driver package[^1] will bind to the custom RKCP0D20 _HID instead. [^1]: https://github.com/worproject/Rockchip-Windows-Drivers/tree/master/drivers/usb/usbehci_noncoherent Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-02-11 21:48:44 +02:00
Mario Bălănică	4684b3ad73	ACPI: Set MSI not supported flag in FADT This stops Linux from attempting to enable MSI and ultimately failing. Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-02-11 21:48:42 +02:00
Mario Bălănică	0b69d04421	ACPI: Remove "rockchip,rk3399-i2c" compatible Linux does not like the DT properties and kernel panics. Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-02-11 21:48:36 +02:00
Mario Bălănică	4af3a03c11	Drop dependency on string.h Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-01-19 20:39:23 +02:00
Mario Bălănică	21c4983009	ACPI: Support I2S master clock adjustment via _DSM Mux the TX clock source accordingly and initialize MCLK at 256 * 48000Hz to fix playback speed in Windows. RX is not configured yet. Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-01-19 04:19:17 +02:00
Mario Bălănică	2124a8c3de	CruLib: Assorted improvements Lay groundwork to support: - clocks from other CRU instances (e.g. PMU1CRU). - gating and reset. Resets are separate due to them controlling not only clocks but also peripheral blocks. Also: - validate input parameters - fix PMU1CRU definitions Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-01-19 04:19:16 +02:00
Mario Bălănică	4209774c09	RK3588Dxe: Clean up unused code Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-01-19 04:19:16 +02:00
Mario Bălănică	1598d883be	Platform/OPi5: Fix i2c0m2 Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-01-19 04:19:15 +02:00
Mario Bălănică	cc77cee865	Platform/Mekotronics: Fix i2c0_sda_m2 Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-01-13 05:56:50 +02:00
CoolStar	e452f9d179	Platform/RK3588: Enable I2S and codec depending on board (#114 )	2024-01-12 03:22:26 +02:00
Mario Bălănică	72385b183a	PlatformBootManagerLib: Add USB keyboard path to ConIn earlier When a keyboard gets installed after connecting the USB controller handles, ConPlatformDxe will check that its short-form device path exists in the ConIn variable before enabling input from it. This variable is missing at first boot, so adding the path after the keyboard was already ignored means it won't be usable during BDS countdown. Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-01-11 06:01:33 +02:00
Mario Bălănică	bc0a1bc833	Silicon/RK3588: Add option to change serial baud rate within UEFI Firstly, split up the Dw8250 serial lib into "full" and "debug" versions. The full version is only used at SEC phase (PrePi) for setting the specified baud rate, while the debug one is used everywhere else and cannot reinitialize the UART. To read the baud rate NV variable in SEC, introduce BaseVariableLib, which is just a slightly modified FaultTolerantWritePei + VariablePei to not use HOBs and PPIs, since they're not available this early. Previous boot stages (DDR, TF-A, U-Boot SPL) are still hardcoded to output at 1.5 Mbaud. Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-01-10 03:00:05 +02:00
Mario Bălănică	a7806a34ac	Silicon/Rockchip: Fork Dw8250SerialPortLib Before I do anything to it.. Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-01-10 03:00:05 +02:00
Mario Bălănică	601a81a813	Silicon/RK3588: Remove own NvStorage PCDs Use gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorage* everywhere for consistency. This also fixes FTW, since its PCDs were previously set to wrong addresses in the DSC. Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-01-10 02:59:59 +02:00
Molly Sophia	526d9e9a7b	GpioLib: Fix dead loops Signed-off-by: Molly Sophia <mollysophia379@gmail.com>	2024-01-08 04:50:46 +00:00
CoolStar	0da51416c7	Platform/RK3588: Refactor I2cIoMux to use GpioPinSetFunction and add missing controllers (#113 )	2024-01-06 01:35:05 +02:00
root	5974d88a1e	Platform/OPi5Plus: Enable Wi-Fi regulator	2024-01-04 19:56:24 +02:00
SleepWalker	cf562625e5	Platform/NanoPC-T6: Power on 4G/LTE module and fix logo (#111 )	2024-01-04 19:12:34 +02:00
Mario Bălănică	22d22a4338	Silicon/RK3588: Add _DSM for setting GMAC RGMII speed Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>	2024-01-03 23:02:30 +02:00
Doug Cook	dc1d255855	GMAC - add hardware IDs for use by Windows Set GMAC HID to RKCP6543 (arbitrarily-chosen, open to alternatives). Move the PRP0001 id to `_CID`.	2023-12-22 09:11:49 +08:00
shimmyshai00	a6c7ca1fef	Platform/RK3588: Add Firefly ITX-3588J board support (#109 )	2023-12-17 12:01:16 +02:00
CoolStar	05bc33baee	Silicon/RK3588: Adjust I2C for Windows driver, add DMA, and enable in boards	2023-12-08 20:42:18 +08:00
CoolStar	83fe40896f	Silicon/RK3588: Adjust GPIO for Windows driver and enable in boards (#106 )	2023-12-02 17:49:46 +02:00
Doug Cook	9529bc4902	Silicon/RK3588: Fix inconsistent Base System RAM length (#104 ) The Base System RAM section nominally starts at `mSystemMemoryBase` but computes its length as if it starts at `0`. This happens to be fine since `mSystemMemoryBase` actually is `0`, so this doesn't cause any real problems, but it seems inconsistent to use a symbol in one place and an implicitly-hard-coded `0` elsewhere. Fix is to use subtract the value of `mSystemMemoryBase` from the length. Since `mSystemMemoryBase` is `0`, this is a no-op, but it makes the table use consistent logic, and might avoid a future issue if this code is ever copy-pasted somewhere that base is not 0.	2023-11-24 01:02:51 +02:00
Doug Cook	66d22455ef	Silicon/RK3588: Fix COMBO_PHY_MODE_SATA typo (#103 ) Not sure that it matters, but there is an apparent typo in the value given to PIPE_PHY_GRF_PIPE_CON3 for COMBO_PHY_MODE_SATA. The '4' is probably off by one digit. Reset value is 0x0002. Existing SATA-mode value is 0x0407 (pipe_sel=PCIe): - `0` = qsgm=0, pipe_sel=00 (PCIe), reserved=0. - `4` = clkreq=0, rxelecidle=1, clk_ref_src=00. - `0` = reserved=0000. - `7` = txpattern_sata=0, txmargin=1, txdeemph=1, txswing=1. Likely intended value is 0x4007 (pipe_sel=SATA): - `4` = qsgm=0, pipe_sel=10 (SATA), reserved=0. - `0` = clkreq=0, rxelecidle=0, clk_ref_src=00. - `0` = reserved=0000. - `7` = txpattern_sata=0, txmargin=1, txdeemph=1, txswing=1.	2023-11-24 00:54:32 +02:00
Molly Sophia	e3a793c89b	DwHdmiQp: Add initial support for DwHdmi I2CM ...and dump the EDID Signed-off-by: Molly Sophia <mollysophia379@gmail.com>	2023-11-21 11:08:51 +00:00
Molly Sophia	e9f0d3363e	build.sh: Do not use cross_compile on aarch64 system Signed-off-by: Molly Sophia <mollysophia379@gmail.com>	2023-11-07 01:52:58 +00:00
Mario Bălănică	98e1008599	Silicon/RK3588: Fix MCFG when CFG0 TLPs are being correctly filtered Some devices (either single or multi-function) manage to appear only once, so we must expose the original ECAM base in this case, starting from dev 0.	2023-10-12 02:57:41 +03:00