Update README.md

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>

.github/workflows/build.yml

@@ -23,25 +23,33 @@ jobs:
     strategy:
       matrix:
         PLATFORM:
-          - rock-5b
-          - rock-5a
-          - orangepi-5
-          - orangepi-5plus
-          - indiedroid-nova
-          - roc-rk3588s-pc
-          - station-m3
-          - r58x
-          - r58-mini
+          - aio-3588q
+          - blade3
           - edge2
+          - fydetab-duo
+          - h88k
+          - indiedroid-nova
+          - itx-3588j
+          - nanopc-cm3588-nas
+          - nanopc-t6
+          - nanopi-m6
           - nanopi-r6c
           - nanopi-r6s
-          - nanopc-t6
-          - blade3
-          - h88k
+          - orangepi-5
+          - orangepi-5plus
+          - powerstation-6
+          - r58-mini
+          - r58x
+          - roc-rk3588s-pc
+          - rock-5-itx
+          - rock-5a
+          - rock-5b
+          - rock-5bplus
+          - station-m3
         CONFIGURATION: ${{ fromJSON(format('[{0}]', inputs.build-configs || '"Debug"')) }}
     steps:
       - name: Checkout
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4
         with:
           submodules: recursive
 
@@ -59,7 +67,8 @@ jobs:
           gcc-aarch64-linux-gnu \
           libc6-dev-arm64-cross \
           python3 \
-          python3-pyelftools
+          python3-pyelftools \
+          uuid-dev
 
       - name: Get version tag
         id: get_version_tag
@@ -79,19 +88,23 @@ jobs:
       - name: Build platform
         shell: bash
         run: |
-          export BUILD_FLAGS="-D SECURE_BOOT_ENABLE=TRUE"
-          export DEFAULT_KEYS="-D DEFAULT_KEYS=TRUE \
-                               -D PK_DEFAULT_FILE=keys/pk.cer \
-                               -D KEK_DEFAULT_FILE1=keys/ms_kek.cer \
-                               -D DB_DEFAULT_FILE1=keys/ms_db1.cer \
-                               -D DB_DEFAULT_FILE2=keys/ms_db2.cer \
-                               -D DBX_DEFAULT_FILE1=keys/arm64_dbx.bin"
+          export EDK2_SECUREBOOT_FLAGS=" \
+              -D DEFAULT_KEYS=TRUE \
+              -D PK_DEFAULT_FILE=keys/pk.cer \
+              -D KEK_DEFAULT_FILE1=keys/ms_kek.cer \
+              -D DB_DEFAULT_FILE1=keys/ms_db1.cer \
+              -D DB_DEFAULT_FILE2=keys/ms_db2.cer \
+              -D DBX_DEFAULT_FILE1=keys/arm64_dbx.bin \
+              -D SECURE_BOOT_ENABLE=TRUE"
 
-          ./build.sh --device ${{matrix.PLATFORM}} --release ${{matrix.CONFIGURATION}} --build-flags="${BUILD_FLAGS} ${DEFAULT_KEYS}"
+          export EDK2_BUILD_FLAGS=" \
+              ${EDK2_SECUREBOOT_FLAGS}"
+
+          ./build.sh --device ${{matrix.PLATFORM}} --release ${{matrix.CONFIGURATION}} --edk2-flags "${EDK2_BUILD_FLAGS}"
           mv RK3588_NOR_FLASH.img ${{matrix.PLATFORM}}_UEFI_${{matrix.CONFIGURATION}}_${{steps.get_version_tag.outputs.version}}.img
 
       - name: Upload artifact
-        uses: actions/upload-artifact@v3
+        uses: actions/upload-artifact@v4
         with:
           name: ${{matrix.PLATFORM}} UEFI ${{matrix.CONFIGURATION}} image
           path: ./*.img

.github/workflows/release.yml

@@ -17,20 +17,12 @@ jobs:
       contents: write
     steps:
       - name: Download all workflow run artifacts
-        uses: actions/download-artifact@v3
+        uses: actions/download-artifact@v4
 
       - name: Create release
-        uses: softprops/action-gh-release@v1
+        uses: softprops/action-gh-release@v2
         with:
           draft: true
           prerelease: false
           files: "*/*Release*.img"
           fail_on_unmatched_files: true
-          generate_release_notes: true
-          append_body: true
-          body: |
-            ## Usage
-            Flash the board-specific image to SPINOR with rkdevtool / rkdeveloptool or to an EMMC / SD card.
-            If your board is not yet supported, using a similar image may work but beware of potential issues.
-
-            Debug builds can be found in the artifacts of the workflow run for this release.

.gitignore

@@ -6,7 +6,6 @@ workspace
 ramdisk
 .cache
 .vscode
-*.dts
 *.swp
 *.rej
 *.orig

.gitmodules

@@ -10,3 +10,10 @@
 [submodule "misc/rkbin"]
 	path = misc/rkbin
 	url = https://github.com/rockchip-linux/rkbin.git
+[submodule "arm-trusted-firmware"]
+	path = arm-trusted-firmware
+	url = https://github.com/worproject/arm-trusted-firmware
+	branch = rk3588
+[submodule "devicetree/mainline/upstream"]
+	path = devicetree/mainline/upstream
+	url = https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git

README.md

@@ -1,86 +1,124 @@
 # EDK2 UEFI firmware for Rockchip RK3588 platforms
 This repository contains an UEFI firmware implementation based on EDK2 for various RK3588 boards.
 
-## Supported platforms
-- [Radxa ROCK 5B](https://wiki.radxa.com/Rock5/hardware/5b)
-- [Radxa ROCK 5A](https://wiki.radxa.com/Rock5/hardware/5a)
+It delivers a PC-like standardized boot experience, supporting multiple operating systems, such as Windows, Linux, BSD and VMware ESXi.
+
+![EDK2 Front Page](images/edk2-frontpage.png)
+
+# Supported platforms
+Support levels are categorized into two tiers: Platinum and Bronze.
+
+Platinum devices are considered to have the best overall support, based on factors such as:
+- Device Tree and peripherals compatible with mainline Linux. [**Required**]
+- Active interest from the vendor in supporting their hardware.
+- Hardware design choices:
+  - If an Ethernet port is present, Realtek PCIe NIC (for netboot) or RK GMAC. [**Required**]
+  - SPI NOR flash for dedicated firmware storage. [Preferred]
+
+Bronze devices may have limitations such as:
+- Missing one or more required features listed above.
+- Low interest from vendors and/or the community.
+- Lack of proper validation, potentially affecting functionality.
+
+Note that this list is subject to change at any time as devices gain better support or fall behind.
+
+## Platinum
+- [Radxa ROCK 5B](https://radxa.com/products/rock5/5b/)
+- [Radxa ROCK 5A](https://radxa.com/products/rock5/5a/)
+- [Radxa ROCK 5 ITX](https://radxa.com/products/rock5/5itx/)
 - [Orange Pi 5](http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-5.html)
 - [Orange Pi 5 Plus](http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-5-plus.html)
-- [ameriDroid Indiedroid Nova](https://indiedroid.us)
-- [Firefly ROC-RK3588S-PC](https://en.t-firefly.com/product/industry/rocrk3588spc)
-- [StationPC Station M3](https://www.stationpc.com/product/stationm3)
-- [Mekotronics R58X](https://www.mekotronics.com/h-pd-75.html)
-- [Mekotronics R58 Mini](https://www.mekotronics.com/h-pd-76.html)
 - [Khadas Edge2](https://www.khadas.com/edge2)
-- [Mixtile Blade 3](https://www.mixtile.com/blade-3)
+- [BuzzTV P6](https://buzztvglobal.com/products/powerstation-6)
 - [FriendlyELEC NanoPC T6](https://wiki.friendlyelec.com/wiki/index.php/NanoPC-T6)
 - [FriendlyELEC NanoPi R6C](https://wiki.friendlyelec.com/wiki/index.php/NanoPi_R6C)
 - [FriendlyELEC NanoPi R6S](https://wiki.friendlyelec.com/wiki/index.php/NanoPi_R6S)
+- [FriendlyELEC NanoPC CM3588-NAS](https://wiki.friendlyelec.com/wiki/index.php/CM3588_NAS_Kit)
+- [ameriDroid Indiedroid Nova](https://indiedroid.us)
+
+## Bronze
+- [Radxa ROCK 5B+](https://radxa.com/products/rock5/5bp)
+- [Fydetab Duo](https://fydetabduo.com/)
+- [Firefly AIO-3588Q](https://en.t-firefly.com/product/industry/aio3588q)
+- [Firefly ITX-3588J](https://en.t-firefly.com/product/industry/itx3588j)
+- [Firefly ROC-RK3588S-PC](https://en.t-firefly.com/product/industry/rocrk3588spc) / [StationPC Station M3](https://www.stationpc.com/product/stationm3)
+- [Mekotronics R58X](https://www.mekotronics.com/h-pd-75.html)
+- [Mekotronics R58 Mini](https://www.mekotronics.com/h-pd-76.html)
+- [Mixtile Blade 3](https://www.mixtile.com/blade-3)
+- [FriendlyELEC NanoPi M6](https://wiki.friendlyelec.com/wiki/index.php/NanoPi_M6)
 - [Hinlink H88K](http://www.hinlink.com)
 
-## Supported peripherals
-Applicable to all platforms unless otherwise noted.
-
-| Device | Status | Notes |
-| --- | --- | --- |
-| USB 3 / 2.0 / 1.1                  | 🟢 Working     | Host-mode only, USB 3 devices connected to a Type-C port only work in one orientation. |
-| PCIe 3.0 (RK3588)                  | 🟢 Working     | No bifurcation support |
-| PCIe 2.1                           | 🟢 Working     | |
-| SATA                               | 🟢 Working     | |
-| SD/eMMC                            | 🟢 Working     | |
-| HDMI output                        | 🟡 Partial     | Single display with mode limited at 1080p 60 Hz |
-| DisplayPort output (USB-C)         | 🟡 Partial     | Mode fixed at 1080p 60 Hz, only works in one orientation of the Type-C port. |
-| eDP output                         | 🟡 Partial     | Disabled, requires manual configuration depending on the platform and panel. |
-| DSI output                         | 🔴 Not working | |
-| GMAC Ethernet                      | 🔴 Not working | Only brought-up for OS usage |
-| Realtek PCIe Ethernet              | 🟢 Working     | Some platforms don't have MAC addresses set, networking may not work in that case. |
-| UART                               | 🟢 Working     | UART2 console available at 1500000 baud rate |
-| GPIO                               | 🟡 Partial     | Only read, write and alt function supported |
-| I2C                                | 🟢 Working     | |
-| SPI                                | 🟢 Working     | |
-| PWM                                | 🟢 Working     | |
-| SPI NOR Flash                      | 🟢 Working     | |
-| HYM8563 real-time clock            | 🟢 Working     | |
-| Cooling fan                        | 🟢 Working     | Supported on most platforms. Fan connector where present, otherwise available at the GPIO header for 3-pin PWM fans (do *not* connect 2-pin fans there!):<br>* Orange Pi 5: `GPIO4_B2`<br>* Indiedroid Nova: `GPIO4_B4` |
-| Status LED                         | 🟢 Working     | |
-| Voltage regulators (RK806, RK860)  | 🟢 Working     | |
-| FUSB302 USB Type-C Controller      | 🔴 Not working | Required for PD negotiation and connector orientation switching |
-
-## Supported OSes
-### In ACPI mode
+# Supported OSes
+## In ACPI mode
 | OS | Version | Tested/supported hardware | Notes |
 | --- | --- | --- | --- |
-| Windows | 10 (1904x), 11 | [Status](https://github.com/worproject/Rockchip-Windows-Drivers#hardware-support-status) ||
+| Windows | 11 | [Status](https://github.com/worproject/Rockchip-Windows-Drivers#hardware-support-status) ||
 | NetBSD | 10 | Display, UART, USB, PCIe (incl. NVME), SATA, eMMC, GMAC Ethernet ||
 | VMware ESXi Arm Fling | >= 1.12 | Display, USB | * PCIe devices will hang at boot, need to disable in settings or leave the ports empty.<br>* GMAC Ethernet gets detected but does not work. |
 | Linux | tested Ubuntu 22.04, kernel 5.15.0-75-generic | Display, UART, USB, PCIe (incl. NVME & Ethernet), SATA | For full hardware functionality, use a kernel with RK3588 support and switch to Device Tree mode. |
 
-#### Additional limitations when using ACPI
-* Devices behind PCIe switches do not work (e.g. the two NICs on Mixtile Blade 3).
-* GMAC is limited to Gigabit speed (i.e. no 10/100).
+> [!NOTE]
+> ACPI support is only being developed and tested against Windows. There are no plans to further improve functionality for other OSes. Consider using Device Tree instead (where applicable, for instance Linux).
 
-### In Device Tree mode
+## In Device Tree mode
+### Vendor compatibility mode
 | OS | Version | Tested/supported hardware | Notes |
 | --- | --- | --- | --- |
-| Rockchip SDK Linux | 5.10 legacy, tested with [Armbian rk3588-live-iso](https://github.com/amazingfate/rk3588-live-iso) | Platform-dependent, most peripherals work. | If using a different kernel, see [Device Tree configuration](#device-tree-configuration). |
+| Rockchip SDK Linux | Kernel 5.10/6.1<br> Tested with:<br> - [Armbian rk3588-live-iso](https://github.com/amazingfate/rk3588-live-iso) | Platform-dependent, most peripherals work. | If using a different kernel, see [Device Tree configuration](#device-tree-configuration). |
 
-## Getting started
-### 1. Requirements
+### Mainline compatibility mode
+| OS | Version | Tested/supported hardware | Notes |
+| --- | --- | --- | --- |
+| Generic upstream Linux | Kernel 6.10 or newer.<br> Tested with:<br> - Ubuntu 24.10<br> - Fedora Workstation 41 | Platform and kernel version dependent, see [Collabora's RK3588 upstream status](https://gitlab.collabora.com/hardware-enablement/rockchip-3588/notes-for-rockchip-3588/-/blob/main/mainline-status.md). | * Kernels older than 6.13 lack HDMI output. To work around this, see: [Device Tree configuration](#device-tree-configuration). |
+
+> [!NOTE]
+> Mainline support is only available on [Platinum](#platinum) platforms.
+
+# Supported peripherals in UEFI
+
+> [!NOTE]
+> Applicable to all platforms unless otherwise noted.
+>
+> Only devices relevant to the firmware itself (not OS) are listed below.
+
+| Device | Status | Notes |
+| --- | --- | --- |
+| USB 3 / 2.0 / 1.1                     | 🟢 Working     | Host-mode only, USB 3 devices connected to a Type-C port only work in one orientation. |
+| PCIe 3.0 / 2.1                        | 🟢 Working     | |
+| SATA                                  | 🟢 Working     | |
+| SD/eMMC                               | 🟢 Working     | |
+| HDMI output                           | 🟡 Partial     | Single display with mode limited at 1080p 60 Hz |
+| DisplayPort output (USB-C)            | 🟡 Partial     | Mode fixed at 1080p 60 Hz, only works in one orientation of the Type-C port. Some displays may not work regardless. |
+| eDP output                            | 🟡 Partial     | Disabled, requires manual configuration depending on the platform and panel. |
+| DSI output                            | 🟢 Working     | Only enabled on Fydetab Duo. Requires manual configuration depending on the platform and panel. |
+| GMAC Ethernet                         | 🔴 Not working | Only brought-up for OS usage |
+| Realtek PCIe Ethernet                 | 🟢 Working     | Some platforms don't have MAC addresses set, networking may not work in that case. |
+| Low-speed (GPIO/UART/I2C/SPI/PWM)     | 🟢 Working     | UART2 console available at 1500000 baud rate |
+| SPI NOR Flash                         | 🟢 Working     | |
+| HYM8563 real-time clock               | 🟢 Working     | |
+| RNG                                   | 🟢 Working     | |
+| Cooling fan                           | 🟢 Working     | Supported on most platforms. Fan connector where present, otherwise available at the GPIO header for 3-pin PWM fans (do *not* connect 2-pin fans there!):<br>* Orange Pi 5: `GPIO4_B2`<br>* Indiedroid Nova: `GPIO4_B4` |
+| Status LED                            | 🟢 Working     | |
+| Voltage regulators (RK806/RK860)      | 🟢 Working     | |
+| FUSB302 USB Type-C Controller         | 🔴 Not working | Required for PD negotiation and connector orientation switching |
+
+# Getting started
+## 1. Requirements
 * One of the [supported devices](#supported-platforms).
-* Either SPI NOR flash (included with some devices), SD card or eMMC to store the firmware on.
+* Storage for the firmware: SPI NOR flash (included with some devices), SD card or eMMC.
 * Quality power supply that can provide at least 15 W. Depending on the peripherals you use, more may be needed.
 
   Note: on Mixtile Blade 3, a fixed voltage *higher than* 5V must be supplied. The board cannot power any external peripherals if the input voltage is just 5V. USB-PD negotiation is not supported by firmware.
 * HDMI or DisplayPort (USB-C) screen capable of at least 1080p 60Hz.
 * Optionally, if display is not available or for debugging purposes, an UART adapter capable of 1500000 baud rate (e.g. USB CH340, CP2104).
 
-### 2. Download the firmware image
+## 2. Download the firmware image
 The latest version can be obtained from <https://github.com/edk2-porting/edk2-rk3588/releases>.
 
-If your platform is not yet supported, using an image meant for another device is **not** recommended. Although they are generally similar, voltage setup can happen to be different and you may risk damaging the board. External peripherals are unlikely to work either.
+If your platform is not yet supported, using an image meant for another device is **NOT** recommended. Although they are generally similar, voltage setup can happen to be different and you may risk damaging the board. External peripherals are unlikely to work either.
 
-### 3. Flash the firmware
-UEFI can be flashed to either a SPI NOR flash, SD card or eMMC module:
+## 3. Flash the firmware
+UEFI can be flashed to either an SPI NOR flash, SD card or eMMC module:
 * For removable SD or eMMC (easiest), you can simply use balenaEtcher, RPi Imager or dd.
 * For SPI NOR or soldered eMMC, instructions can be found at: <https://wiki.radxa.com/Rock5/install/spi>.
 
@@ -92,40 +130,43 @@ If you wish to have both UEFI and an OS on the same SD or eMMC device: flash UEF
 
 Note: Using SPI NOR (if present) is recommeded, as it leaves the other storage options free for other purposes. Additionally, SD/eMMC will limit the firmware's ability to access its own storage (variable store) when an OS is running. This feature is mostly used by OS installers to create the boot menu options, it is not mandatory.
 
-### 4. Connect peripherals and power on the device
+## 4. Connect peripherals and power on the device
 If the flashing process has been done correctly, you should see the status LED blinking (if present), and shortly after, the platform's boot logo with a progress bar at the bottom on the connected display.
 
 At this stage, you can press <kbd>Esc</kbd> to enter the firmware setup, <kbd>F1</kbd> to launch the UEFI Shell, or, provided you also have an UEFI bootloader/app on a storage device, you can let the system automatically run that, which is the default behavior if no action is taken.
 
-Check the [Supported peripherals](#supported-peripherals) and [Supported OSes](#supported-oses-with-acpi) sections to see what's currently possible with this firmware.
+Check the [Supported OSes](#supported-oses) and [Supported peripherals in UEFI](#supported-peripherals-in-uefi) sections to see what's currently possible with this firmware.
 
 Also check the configuration options described below, some of which may need to be changed depending on the OS used.
 
 If you experience any issues, please see the [Troubleshooting](#troubleshooting) section.
 
-## Configuration settings
-The UEFI provides a few configuration options, like CPU frequency, PCIe/SATA selection for an M.2 port, fan control, etc. These can be viewed and changed using both the UI configuration menu (under `Device Manager` -> `Rockchip Platform Configuration`), as well as the UEFI Shell.
+# Configuration settings
+The UEFI provides a few configuration options, like CPU frequency, PCIe/SATA selection for an M.2 port, fan control, etc. These can be viewed and changed using the UI configuration menu (under `Device Manager` -> `Rockchip Platform Configuration`).
 
-Configuration through the user interface is fairly straightforward and help information is provided on the right side of the menu.
+Configuration through the user interface is fairly straightforward and help/navigation information is provided around the menus.
 
-Configuration through the UEFI shell is more advanced and mostly useful for scripts. See [Setting configuration options via the shell](#setting-configuration-options-via-the-shell).
-
-### Tips
+## Tips
 * CPU clocks are set to 816 MHz (boot default) on platforms without a cooling fan included. If you have adequate cooling, go to the configuration menu -> `CPU Performance` and set all Cluster Presets to `Maximum`.
 
-* If you only wish to boot non-Windows OSes in ACPI mode, go to the configuration menu -> `ACPI / Device Tree` and set `USB 2.0 Support` to `Enabled`, in order to get maximum speed from USB 2.0 ports.
-
-  Booting Windows with this option enabled will cause it to crash.
-
-### Device Tree configuration
+## Device Tree configuration
 For rich Linux support, it is recommended to enable Device Tree mode. You can do so by going to the configuration menu -> `ACPI / Device Tree` and setting `Config Table Mode` to `Device Tree`.
 
-By default, the firmware installs a [DTB compatible with (most) Rockchip SDK Linux 5.10 legacy kernel variants](https://github.com/edk2-porting/edk2-rk3588/tree/master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree).
+The firmware provides two compatibility modes:
+* `Vendor` - compatible with Rockchip SDK Linux 5.10/6.1 kernel only.
+* `Mainline` - compatible with generic upstream Linux 6.10 or newer kernel. This option is under active development and may lack certain features. Therefore, it is always recommended to use the latest kernel and firmware available in order to benefit from better device support.
 
-#### Custom Device Tree Blob (DTB) override and overlays
+[Platinum](#platinum) platforms will have the `Mainline` option enabled by default, while [Bronze](#bronze) ones will fall back to `Vendor`.
+
+> [!TIP]
+> In `Mainline` mode with generic Linux kernels older than 6.13, the HDMI output will not be usable. To use the UEFI-initialized display instead, go to the configuration menu -> `ACPI / Device Tree` and enable `Force UEFI GOP Display`. Note that GPU acceleration cannot work in this mode.
+
+### Custom Device Tree Blob (DTB) override and overlays
 It is also possible to provide a custom DTB and overlays. To enable this, go to the configuration menu -> `ACPI / Device Tree` and set `Support DTB override & overlays` to `Enabled`.
 
-The firmware will now look for overrides in the partition of a selected boot option / OS loader. In most cases this will be the first FAT32 EFI System Partition.
+The firmware will now look for overrides in the partition of a selected boot option / OS loader. In most cases, this will be the first FAT32 EFI System Partition.
+
+**Important:** The `dtb` directory must be placed at the root of the partition. It should not be inside any sub-directory.
 
 * The base DTB must be located at `\dtb\base\<PLATFORM-DT-NAME>.dtb`.
 
@@ -135,25 +176,31 @@ The firmware will now look for overrides in the partition of a selected boot opt
 
   and must have the `.dtbo` extension.
 
-The paths above are relative to the root of the file system. That is, the `dtb` directory must not be placed in a sub-directory.
-
 `<PLATFORM-DT-NAME>` can be:
 | Name                                    | Platform                      |
 | --------------------------------------- | ----------------------------- |
-| `rk3588s-9tripod-linux`                 | Indiedroid Nova               |
-| `roc-rk3588s-pc`                        | ROC-RK3588S-PC / Station M3   |
-| `rk3588-nanopc-t6`                      | NanoPC T6                     |
-| `rk3588s-nanopi-r6c`                    | NanoPi R6C                    |
-| `rk3588s-nanopi-r6s`                    | NanoPi R6S                    |
-| `rk3588-hinlink-h88k`                   | H88K                          |
-| `rk3588s-khadas-edge2`                  | Edge2                         |
-| `rk3588-blueberry-minipc-linux`         | R58 Mini                      |
-| `rk3588-blueberry-edge-v12-linux`       | R58X (v1.2)                   |
-| `rk3588-blade3-v101-linux`              | Blade 3                       |
+| `rk3588-rock-5b`                        | ROCK 5B                       |
+| `rk3588-rock-5bp`                       | ROCK 5B+                      |
+| `rk3588s-rock-5a`                       | ROCK 5A                       |
+| `rk3588-rock-5-itx`                     | ROCK 5 ITX                    |
 | `rk3588s-orangepi-5`                    | Orange Pi 5                   |
 | `rk3588-orangepi-5-plus`                | Orange Pi 5 Plus              |
-| `rk3588s-rock-5a`                       | ROCK 5A                       |
-| `rk3588-rock-5b`                        | ROCK 5B                       |
+| `rk3588s-9tripod-linux`                 | Indiedroid Nova               |
+| `rk3588s-fydetab-duo`                   | Fydetab Duo                   |
+| `rk3588-buzztv-p6`                      | PowerStation 6                |
+| `aio-3588q`                             | Firefly AIO-3588Q             |
+| `itx-3588j`                             | Firefly ITX-3588J             |
+| `roc-rk3588s-pc`                        | ROC-RK3588S-PC / Station M3   |
+| `rk3588-blueberry-edge-v12-linux`       | R58X (v1.2)                   |
+| `rk3588-blueberry-minipc-linux`         | R58 Mini                      |
+| `rk3588s-khadas-edge2`                  | Edge2                         |
+| `rk3588-blade3-v101-linux`              | Blade 3                       |
+| `rk3588-nanopc-t6`                      | NanoPC T6                     |
+| `rk3588-nanopc-cm3588-nas`              | NanoPC CM3588-NAS             |
+| `rk3588s-nanopi-r6c`                    | NanoPi R6C                    |
+| `rk3588s-nanopi-r6s`                    | NanoPi R6S                    |
+| `rk3588s-nanopi-m6`                     | NanoPi M6                     |
+| `rk3588-hinlink-h88k`                   | H88K                          |
 
 In the absence of a custom base DTB override, the overlays are applied on top of the firmware-provided DTB.
 
@@ -165,7 +212,7 @@ If the custom base DTB is invalid, the firmware-provided one will be passed to t
 
 This entire process is logged to the [serial console](#advanced-troubleshooting). There's currently no other way to see potential errors.
 
-## Updating the firmware
+# Updating the firmware
 If the storage is only used for UEFI and nothing else, simply download the latest image and flash it as described in the [Getting started](#getting-started) section.
 
 If it is also used by an OS and has additional partitions, only part of the image needs to be applied. This can be done with the `dd` tool:
@@ -179,12 +226,16 @@ dd if=FIRMWARE.img of=DESTINATION bs=512 skip=64 seek=64 conv=notrunc
 
 Here we skip the GPT and copy the firmware starting at offset 0x8000 (`64` blocks * `512` bytes block size) until its end. See [Flash layout](#flash-layout) for more details.
 
-## Troubleshooting
-First of all, make sure your device can only possibly load the UEFI firmware and nothing else. U-Boot must not present on either SPI NOR, SD or eMMC, otherwise it could take precedence.
+# Troubleshooting
+
+> [!IMPORTANT]
+> First of all, make sure your device can only possibly load the UEFI firmware and nothing else.
+>
+> **U-Boot must not be present on either SPI NOR, SD or eMMC, otherwise it could take precedence and cause issues.**
 
 Below you can find some basic debugging information. If none of this helps, please see the [Advanced troubleshooting](#advanced-troubleshooting) section.
 
-### Meaning of the Status LED
+## Meaning of the Status LED
 If your device has an activity LED, the firmware will blink it in different patterns to indicate the current system status.
 
 1. Immediately after power on, the LED should start pulsing quickly. This indicates that the firmware is initializing.
@@ -199,8 +250,13 @@ If the LED:
 
   Note that it is only expected to stop as described at point 3) above.
 
-### Common issues
-#### Nothing shows up on the screen
+## Recovery
+In case you don't have easy access to the MaskROM button, UEFI provides a boot option for that purpose, accessible either via the Boot Manager or <kbd>F4</kbd> key during splash screen.
+
+Additionally, holding the Recovery (or volume up) button while powering on the device will also enter MaskROM mode.
+
+## Common issues
+### Nothing shows up on the screen
 Make sure you've flashed the firmware correctly and that it is the version designed for your device. In most cases this is the culprit.
 
 Assuming the firmware loads fine:
@@ -210,12 +266,15 @@ Assuming the firmware loads fine:
 
 If you are not able to get any display output, the only way to interact with UEFI is via the [serial console](#advanced-troubleshooting).
 
-#### USB 3 devices do not work
+### Configuration settings do not get saved
+This has been observed in cases where firmware was present on more than one device (SPI NOR, eMMC or SD). This is not a supported scenario, because UEFI will be unable to accurately determine the boot device it belongs to. The solution is to unplug or erase devices that may have other firmware on them.
+
+### USB 3 devices do not work
 * Try a different port.
 * If you're using USB-C, 3.0 devices will only work in one orientation of the connector. Check both.
-* Make sure the power supply and cable are good
+* Make sure the power supply and cable are good.
 
-#### Networking does not work
+### Networking does not work
 * Only Realtek PCIe and USB controllers are supported. Native Gigabit provided by RK3588 isn't.
 
 * Some boards with Realtek NICs do not have a MAC address set at factory and will show-up as being all zeros in UEFI, possibly preventing the adapter from obtaining an IP address.
@@ -258,7 +317,7 @@ If you are not able to get any display output, the only way to interact with UEF
 
   **Note:** the number of eFuses is limited, thus MAC addresses can only be changed a few times.
 
-### Advanced troubleshooting
+## Advanced troubleshooting
 The firmware will log detailed information to the serial console when using a debug version. See the [release notes](https://github.com/edk2-porting/edk2-rk3588/releases) for details on how to obtain this version.
 
 1. The debug image needs to be flashed in place of the existing one.
@@ -269,25 +328,25 @@ The firmware will log detailed information to the serial console when using a de
 
 4. Power on the device.
 
-You should be able to see a lot of debug messages being printed. If that's not the case, double check the connections (swap RX/TX), make sure the adapter is functional and configured correctly.
+You should be able to see many debug messages being printed to the console. If that's not the case, double check the connections (swap RX/TX), make sure the adapter is functional and configured correctly.
 
 The logs should give an insight of what's going on. If you need help analyzing them, feel free to open an issue ticket.
 
-## Reporting issues
+# Reporting issues
 You can open issues related to UEFI at <https://github.com/edk2-porting/edk2-rk3588/issues>.
 
 Please include as many details as possible: expected behavior, what actually happens, steps to reproduce, [serial logs](#advanced-troubleshooting), etc.
 
 Also check the existing issues in case yours might be already reported.
 
-## Building
+# Building
 The firmware can only be built on Linux currently. For Windows use WSL.
 
 1. Install required packages:
 
    For Ubuntu/Debian:
    ```bash
-   sudo apt install git gcc g++ build-essential gcc-aarch64-linux-gnu iasl python3-pyelftools uuid-dev
+   sudo apt install git gcc g++ build-essential gcc-aarch64-linux-gnu acpica-tools python3-pyelftools uuid-dev python-is-python3 device-tree-compiler
    ```
    For Arch Linux:
    ```bash
@@ -308,9 +367,9 @@ The firmware can only be built on Linux currently. For Windows use WSL.
 
 If you get build errors, it is very likely that you're still missing some dependencies. The list of packages above is not complete and depending on the distro you may need to install additional ones. In most cases, looking up the error messages on the internet will point you at the right packages.
 
-## Notes
+# Notes
 
-### Flash layout
+## Flash layout
 | Address    | Size       | Desc                  | File                   |
 | ---------- | ---------- | --------------------- | ---------------------- |
 | 0x00000000 | 0x00004400 | GPT Table             | rk3588_spi_nor_gpt.img |
@@ -324,7 +383,7 @@ The variable store is not included in the flash image, in order to prevent overw
 
 The firmware expects these exact offsets, do not change them.
 
-### Memory Map
+## Memory Map
 | Address    | Size       | Desc                  | File                |
 | ---------- | ---------  | --------------------- | ------------------- |
 | 0x00040000 |            | ATF                   | bl31_0x00040000.bin |
@@ -336,111 +395,14 @@ The firmware expects these exact offsets, do not change them.
 | 0x08400000 |            | OP-TEE                | bl32.bin            |
 | 0xff100000 |            | ATF (PMU_MEM)         | bl31_0xff100000.bin |
 
-### Setting configuration options via the shell
-To configure using the UEFI Shell, use `setvar` command to read/write the UEFI variables with GUID = `10f41c33-a468-42cd-85ee-7043213f73a3`.
-
-The syntax to read a setting is:
-```
-setvar <NAME> -guid 10f41c33-a468-42cd-85ee-7043213f73a3
-```
-
-The syntax to write a setting is:
-```
-setvar <NAME> -guid 10f41c33-a468-42cd-85ee-7043213f73a3 -bs -rt -nv =<VALUE>
-```
-`VALUE` must be in hexadecimal.
-
-For string-type settings, the syntax to write is:
-```
-setvar <NAME> -guid 10f41c33-a468-42cd-85ee-7043213f73a3 -bs -rt -nv =L"<VALUE>" =0x0000
-```
-
-### CPU Performance
-#### Cluster clocks / voltages
-| Variable                          |    NAME                            |  VALUE                       |
-| --------------------------------- |----------------------------------- |----------------------------- |
-| CPU`x` Clock Preset               | `CpuPerf_CPUxClusterClockPreset`   | Boot default = `0x00000000`<br> Min = `0x00000001`<br> Max = `0x00000002`<br> Custom = `0x00000003` |
-| CPU`x` Custom Clock Preset (MHz)  | `CpuPerf_CPUxClusterClockCustom`   | Hex numeric option, 4-bytes<br> See below. |
-| CPU`x` Voltage Mode               | `CpuPerf_CPUxClusterVoltageMode`   | Auto = `0x00000000` (default)<br> Custom = `0x00000001`|
-| CPU`x` Custom Voltage (uV)        | `CpuPerf_CPUxClusterVoltageCustom` | Hex numeric value, 4-bytes<br> See below. |
-
-`x` can be :
-* `L` for LITTLE cluster
-* `B01` for big cluster #0
-* `B23` for big cluster #1
-
-`CpuPerf_CPUxClusterClockCustom` can have one of the following values:
-* All clusters: `408000000`, `600000000`, `816000000`, `1008000000`, `1200000000`, `1416000000`, `1608000000`, `1800000000`
-* Big cluster additional clocks: `2016000000`, `2208000000`, `2256000000`, `2304000000`, `2352000000`, `2400000000`
-
-`CpuPerf_CPUxClusterVoltageCustom` is the cluster voltage in microvolts. Min: `500000`, Max: `1500000`.
-Default value depends on cluster type.
-
-### PCIe/SATA/USB Combo PIPE PHY
-| Variable    |    NAME         |  VALUE                             |
-| ----------- | --------------- | ---------------------------------- |
-| PHY #0 Mode | `ComboPhy0Mode` | Unconnected = `0x00000000`<br> PCIe = `0x00000001`<br> SATA = `0x00000002` |
-| PHY #1 Mode | `ComboPhy1Mode` | Unconnected = `0x00000000`<br> PCIe = `0x00000001`<br> SATA = `0x00000002` |
-| PHY #2 Mode | `ComboPhy2Mode` | Unconnected = `0x00000000`<br> PCIe = `0x00000001`<br> SATA = `0x00000002`<br> USB3 = `0x00000003` |
-
-Default values and supported options depend on the platform. Check documentation and schematics for more details on PHY wiring.
-
-### USB/DP Combo PHY
-| Variable                      |    NAME              |  VALUE                            |
-| ----------------------------- | -------------------- | --------------------------------- |
-| PHY #0 USB 3 SuperSpeed State | `UsbDpPhy0Usb3State` | Enabled = `0x00000001`<br> Disabled = `0x00000000` |
-| PHY #1 USB 3 SuperSpeed State | `UsbDpPhy1Usb3State` | Enabled = `0x00000001`<br> Disabled = `0x00000000` |
-
-### PCI Express 3.0
-| Variable      |    NAME       |  VALUE                            |
-| ------------- | ------------- | --------------------------------- |
-| Support State | `Pcie30State` | Enabled = `0x00000001`<br> Disabled = `0x00000000` |
-
-### ACPI / Device Tree
-| Variable          |    NAME           |  VALUE                            |
-| ----------------- | ----------------- | --------------------------------- |
-| Config Table Mode | `ConfigTableMode` | ACPI = `0x00000001`<br> DeviceTree = `0x00000002`<br> Both = `0x00000003` |
-
-#### ACPI Configuration
-| Variable        |    NAME         |  VALUE                            |
-| --------------- | --------------- | --------------------------------- |
-| USB 2.0 Support | `AcpiUsb2State` | Enabled = `0x00000001`<br> Disabled = `0x00000000` |
-
-#### Device Tree Configuration
-| Variable                        |    NAME               |  VALUE                            |
-| ------------------------------- | --------------------- | --------------------------------- |
-| Support DTB override & overlays | `FdtSupportOverrides` | Enabled = `0x01`<br> Disabled = `0x00` |
-
-### Cooling fan
-| Variable        |    NAME           |  VALUE                            |
-| --------------- | ----------------- | --------------------------------- |
-| On-board Fan    | `CoolingFanState` | Enabled = `0x00000001`<br> Disabled = `0x00000000` |
-| Fan Speed (%)   | `CoolingFanSpeed` | Hex numeric value, 4-bytes<br> Percentage: 0-100 |
-
-**Examples:**
-- To read the 'CPUL Clock Preset' setting :
-```
-setvar CpuPerf_CPULClusterClockPreset -guid 10f41c33-a468-42cd-85ee-7043213f73a3
-```
-
-- To change the 'CPUL Clock Preset' setting to 'Maximum' :
-```
-setvar CpuPerf_CPULClusterClockPreset -guid 10f41c33-a468-42cd-85ee-7043213f73a3 -bs -rt -nv =0x00000002
-```
-
 ## Licenses
 Most of the UEFI code is licensed under the default EDK2 license, which is [BSD-2-Clause-Patent](https://github.com/tianocore/edk2/blob/master/License.txt).
 
-Some non-critical components have been ported from Rockchip's U-Boot fork and are licensed as **GPL-2.0-or-later**:
-* UsbDpPhy
-* DwDpLib
-
-The files in `edk2-rockchip-non-osi` are licensed as **GPL-2.0-only**.
+Some components ported from Linux and Rockchip's U-Boot fork are licensed as **GPL-2.0** (check `SPDX-License-Identifier`).
 
 The license for some of the blobs in the `misc/rkbin/` directory can be found at: <https://github.com/rockchip-linux/rkbin/blob/master/LICENSE>. Note that it also contains binaries built from open-source projects such as U-Boot (SPL), Arm Trusted Firmware and OP-TEE, having a different license.
 
 ## Community
-* Radxa forum: <https://forum.radxa.com/t/windows-uefi-on-rock-5-mega-thread/12924>
 * Hack w/ Rockchip Telegram: <https://t.me/UEFIonRockchip>
 * Windows on R Discord: <https://discord.gg/vjHwptUCa3>
 

build.sh

@@ -1,237 +1,253 @@
 #!/bin/bash
 
 function _help(){
-	echo "Usage: build.sh --device DEV"
-	echo
-	echo "Build edk2 for Rockchip RK35xx platforms."
-	echo
-	echo "Options: "
-	echo "	--device DEV, -d DEV:    build for DEV."
-	echo "	--all, -a:               build all devices."
-	echo "	--gui:                   Enable simple-init GUI."
-	echo "	--release MODE, -r MODE: Release mode for building, default is 'DEBUG', 'RELEASE' alternatively."
-	echo "	--toolchain TOOLCHAIN:   Set toolchain, default is 'GCC'."
-	echo " 	--skip-rootfs-gen:       skip generating SimpleInit rootfs to speed up building."
-	echo "	--clean, -C:             clean workspace and output."
-	echo "	--distclean, -D:         clean up all files that are not in repo."
-	echo "	--outputdir, -O:         output folder."
-	echo "	--build-flags:           flags appended to the EDK2 build process."
-	echo "	--help, -h:              show this help."
-	echo
-	exit "${1}"
+    echo
+    echo "Build EDK2 for Rockchip RK3588 platforms."
+    echo
+    echo "Usage: build.sh [options]"
+    echo
+    echo "Options:"
+    echo "  -d, --device DEV            Build for DEV, or 'all'."
+    echo "  -r, --release MODE          Release mode for building, default is 'DEBUG', 'RELEASE' alternatively."
+    echo "  -t, --toolchain TOOLCHAIN   Set toolchain, default is 'GCC'."
+    echo "  --open-tfa ENABLE           Use open-source TF-A submodule. Default: ${OPEN_TFA}"
+    echo "  -C, --clean                 Clean workspace and output."
+    echo "  -D, --distclean             Clean up all files that are not in repo."
+    echo "  --tfa-flags \"FLAGS\"         Flags appended to open TF-A build process."
+    echo "  --edk2-flags \"FLAGS\"        Flags appended to the EDK2 build process."
+    echo "  -h, --help                  Show this help."
+    echo
+    exit "${1}"
 }
 
-function _error(){ echo "${@}" >&2;exit 1; }
+function _error() { echo "${@}" >&2; exit 1; }
 
-MACHINE_TYPE=`uname -m`
+function _build_idblock() {
+    echo " => Building idblock.bin"
+    pushd ${WORKSPACE}
 
-# Fix-up possible differences in reported arch
-if [ ${MACHINE_TYPE} == 'arm64' ]; then
-	MACHINE_TYPE='aarch64'
-elif [ ${MACHINE_TYPE} == 'amd64' ]; then
-	MACHINE_TYPE='x86_64'
-fi
+    FLASHFILES="FlashHead.bin FlashData.bin FlashBoot.bin"
+    rm -f rk35*_spl_loader_*.bin idblock.bin rk35*_ddr_*.bin rk35*_usbplug*.bin UsbHead.bin ${FLASHFILES}
 
-function _build_idblock(){
-	echo " => Building idblock.bin"
-	pushd ${WORKSPACE}
-	FLASHFILES="FlashHead.bin FlashData.bin FlashBoot.bin"
-	rm -f rk35*_spl_loader_*.bin idblock.bin rk35*_ddr_*.bin rk35*_usbplug*.bin UsbHead.bin ${FLASHFILES}
+    DDRBIN_RKBIN=$(grep '^FlashData' ${ROOTDIR}/misc/rkbin/RKBOOT/${MINIALL_INI} | cut -d = -f 2-)
+    SPL_RKBIN=$(grep '^FlashBoot' ${ROOTDIR}/misc/rkbin/RKBOOT/${MINIALL_INI} | cut -d = -f 2-)
 
-	DDRBIN=$(grep '^FlashData' ${ROOTDIR}/misc/rkbin/RKBOOT/${MINIALL_INI} | cut -d = -f 2-)
-	SPL=$(grep '^FlashBoot' ${ROOTDIR}/misc/rkbin/RKBOOT/${MINIALL_INI} | cut -d = -f 2-)
+    DDRBIN="${ROOTDIR}/misc/rkbin/${DDRBIN_RKBIN}"
 
-	# Create idblock.bin
-	${ROOTDIR}/misc/tools/${MACHINE_TYPE}/mkimage -n rk3588 -T rksd -d ${ROOTDIR}/misc/rkbin/${DDRBIN}:${ROOTDIR}/misc/rkbin/${SPL} idblock.bin
-	popd
-	echo " => idblock.bin build done"
+    #
+    # SPL v1.13 has broken SD card support!
+    # Use v1.12 instead.
+    #
+    # SPL="${ROOTDIR}/misc/rkbin/${SPL_RKBIN}"
+    SPL="${ROOTDIR}/misc/rk3588_spl_v1.12.bin"
+
+    # Create idblock.bin
+    ${ROOTDIR}/misc/tools/${MACHINE_TYPE}/mkimage -n rk3588 -T rksd -d ${DDRBIN}:${SPL} idblock.bin
+
+    popd
+    echo " => idblock.bin build done"
 }
 
-function _build_fit(){
-	echo " => Building FIT"
-	pushd ${WORKSPACE}
-	BL31=$(grep '^PATH=.*_bl31_' ${ROOTDIR}/misc/rkbin/RKTRUST/${TRUST_INI} | cut -d = -f 2-)
-	BL32=$(grep '^PATH=.*_bl32_' ${ROOTDIR}/misc/rkbin/RKTRUST/${TRUST_INI} | cut -d = -f 2-)
-	rm -f bl31_0x*.bin ${WORKSPACE}/BL33_AP_UEFI.Fv ${SOC_L}_${DEVICE}_EFI.its
+function _build_fit() {
+    echo " => Building FIT"
+    pushd ${WORKSPACE}
 
-	${ROOTDIR}/misc/extractbl31.py ${ROOTDIR}/misc/rkbin/${BL31}
-	cp ${ROOTDIR}/misc/rkbin/${BL32} ${WORKSPACE}/bl32.bin
-	cp ${ROOTDIR}/misc/${SOC_L}_spl.dtb ${WORKSPACE}/${DEVICE}.dtb
-	cp ${WORKSPACE}/Build/${PLATFORM_NAME}/${_MODE}_${TOOLCHAIN}/FV/BL33_AP_UEFI.Fv ${WORKSPACE}/
-	cat ${ROOTDIR}/misc/uefi_${SOC_L}.its | sed "s,@DEVICE@,${DEVICE},g" > ${SOC_L}_${DEVICE}_EFI.its
-	${ROOTDIR}/misc/tools/${MACHINE_TYPE}/mkimage -f ${SOC_L}_${DEVICE}_EFI.its -E ${DEVICE}_EFI.itb
+    BL31_RKBIN=$(grep '^PATH=.*_bl31_' ${ROOTDIR}/misc/rkbin/RKTRUST/${TRUST_INI} | cut -d = -f 2-)
+    BL32_RKBIN=$(grep '^PATH=.*_bl32_' ${ROOTDIR}/misc/rkbin/RKTRUST/${TRUST_INI} | cut -d = -f 2-)
 
-	popd
-	echo " => FIT build done"
+    BL31="${ROOTDIR}/misc/rkbin/${BL31_RKBIN}"
+    BL32="${ROOTDIR}/misc/rkbin/${BL32_RKBIN}"
+
+    if [ ${OPEN_TFA} == 1 ]; then
+        BL31="${ROOTDIR}/arm-trusted-firmware/build/${TFA_PLAT}/${RELEASE_TYPE,,}/bl31/bl31.elf"
+    fi
+
+    rm -f bl31_0x*.bin ${WORKSPACE}/BL33_AP_UEFI.Fv ${SOC_L}_${DEVICE}_EFI.its
+
+    ${ROOTDIR}/misc/extractbl31.py ${BL31}
+    if [ ! -f bl31_0x000f0000.bin ]; then
+        # Not used but FIT expects it.
+        touch bl31_0x000f0000.bin
+    fi
+
+    cp ${BL32} ${WORKSPACE}/bl32.bin
+    cp ${ROOTDIR}/misc/${SOC_L}_spl.dtb ${WORKSPACE}/${DEVICE}.dtb
+    cp ${WORKSPACE}/Build/${PLATFORM_NAME}/${RELEASE_TYPE}_${TOOLCHAIN}/FV/BL33_AP_UEFI.Fv ${WORKSPACE}/
+    cat ${ROOTDIR}/misc/uefi_${SOC_L}.its | sed "s,@DEVICE@,${DEVICE},g" > ${SOC_L}_${DEVICE}_EFI.its
+    ${ROOTDIR}/misc/tools/${MACHINE_TYPE}/mkimage -f ${SOC_L}_${DEVICE}_EFI.its -E ${DEVICE}_EFI.itb
+
+    popd
+    echo " => FIT build done"
 }
 
-function _pack(){
-	_build_idblock
-	_build_fit
+function _pack_image() {
+    _build_idblock
+    _build_fit
 
-	echo " => Building 8MB NOR FLASH IMAGE"
-	cp ${WORKSPACE}/Build/${PLATFORM_NAME}/${_MODE}_${TOOLCHAIN}/FV/NOR_FLASH_IMAGE.fd ${WORKSPACE}/RK3588_NOR_FLASH.img
+    echo " => Building 8MB NOR FLASH IMAGE"
+    cp ${WORKSPACE}/Build/${PLATFORM_NAME}/${RELEASE_TYPE}_${TOOLCHAIN}/FV/NOR_FLASH_IMAGE.fd ${WORKSPACE}/RK3588_NOR_FLASH.img
 
-	# might be GPT table? size:0x4400
-	dd if=${ROOTDIR}/misc/rk3588_spi_nor_gpt.img of=${WORKSPACE}/RK3588_NOR_FLASH.img
-	# idblock at 0x8000
-	dd if=${WORKSPACE}/idblock.bin of=${WORKSPACE}/RK3588_NOR_FLASH.img bs=1K seek=32
-	# FIT Image at 0x100000
-	dd if=${WORKSPACE}/${DEVICE}_EFI.itb of=${WORKSPACE}/RK3588_NOR_FLASH.img bs=1K seek=1024
-	cp ${WORKSPACE}/RK3588_NOR_FLASH.img ${ROOTDIR}/
+    # GPT at 0x0, size:0x4400
+    dd if=${ROOTDIR}/misc/rk3588_spi_nor_gpt.img of=${WORKSPACE}/RK3588_NOR_FLASH.img
+    # idblock at 0x8000
+    dd if=${WORKSPACE}/idblock.bin of=${WORKSPACE}/RK3588_NOR_FLASH.img bs=1K seek=32
+    # FIT Image at 0x100000
+    dd if=${WORKSPACE}/${DEVICE}_EFI.itb of=${WORKSPACE}/RK3588_NOR_FLASH.img bs=1K seek=1024
+    cp ${WORKSPACE}/RK3588_NOR_FLASH.img ${ROOTDIR}/
 }
 
 function _build(){
-	local DEVICE="${1}"
-	shift
-	[ -d "${WORKSPACE}/Conf" ]||mkdir -p "${WORKSPACE}/Conf"
-	source "${ROOTDIR}/edk2/edksetup.sh"
-	[ -d "${WORKSPACE}" ]||mkdir "${WORKSPACE}"
-	set -x
-	make -C "${ROOTDIR}/edk2/BaseTools"||exit "$?"
+    local DEVICE="${1}"; shift
 
-	EXT=""
+    #
+    # Grab platform parameters
+    #
+    if [ -f "configs/${DEVICE}.conf" ]
+    then source "configs/${DEVICE}.conf"
+    else _error "Device configuration not found"
+    fi
+    if [ -f "configs/${SOC}.conf" ]
+    then source "configs/${SOC}.conf"
+    else _error "SoC configuration not found"
+    fi
+    typeset -l SOC_L="$SOC"
 
-	if [ -f "configs/${DEVICE}.conf" ]
-	then source "configs/${DEVICE}.conf"
-	else _error "Device configuration not found"
-	fi
-	if [ -f "configs/${SOC}.conf" ]
-	then source "configs/${SOC}.conf"
-	else _error "SoC configuration not found"
-	fi
-	typeset -l SOC_L="$SOC"
+    rm -f "${OUTDIR}/RK35*_NOR_FLASH.img"
 
-	# based on the instructions from edk2-platform
-	rm -f "${OUTDIR}/RK35*_NOR_FLASH.img"
+    #
+    # Build TF-A
+    #
+    if [ ${OPEN_TFA} == 1 ]; then
+        pushd arm-trusted-firmware
 
-	case "${MODE}" in
-		RELEASE) _MODE=RELEASE;;
-		*) _MODE=DEBUG;;
-	esac
+        if [ ${RELEASE_TYPE} == "DEBUG" ]; then
+            DEBUG=1
+        else
+            DEBUG=0
+        fi
 
-	build \
-		-s \
-		-n 0 \
-		-a AARCH64 \
-		-t "${TOOLCHAIN}" \
-		-p "${ROOTDIR}/${DSC_FILE}" \
-		-b "${_MODE}" \
-		-D FIRMWARE_VER="${GITCOMMIT}" \
-		-D ENABLE_SIMPLE_INIT="${BUILD_GUI}" \
-		-D CONFIG_SOC="${SOC}" \
-		${BUILD_FLAGS} \
-		||return "$?"
+        make PLAT=${TFA_PLAT} DEBUG=${DEBUG} all ${TFA_FLAGS}
 
-	_pack
-	set +x
+        popd
+    fi
 
-	echo "Build done: RK3588_NOR_FLASH.img"
+    #
+    # Build EDK2
+    #
+    [ -d "${WORKSPACE}/Conf" ] || mkdir -p "${WORKSPACE}/Conf"
+
+    export GCC_AARCH64_PREFIX="${CROSS_COMPILE}"
+    export CLANG38_AARCH64_PREFIX="${CROSS_COMPILE}"
+    export PACKAGES_PATH="${ROOTDIR}/edk2:${ROOTDIR}/edk2-platforms:${ROOTDIR}/edk2-rockchip:${ROOTDIR}/devicetree:${ROOTDIR}/edk2-non-osi:${ROOTDIR}"
+
+    make -C "${ROOTDIR}/edk2/BaseTools"
+    source "${ROOTDIR}/edk2/edksetup.sh"
+
+    build \
+        -s \
+        -n 0 \
+        -a AARCH64 \
+        -t "${TOOLCHAIN}" \
+        -p "${ROOTDIR}/${DSC_FILE}" \
+        -b "${RELEASE_TYPE}" \
+        -D FIRMWARE_VER="${GIT_COMMIT}" \
+        --pcd gRockchipTokenSpaceGuid.PcdFitImageFlashAddress=0x100000 \
+        ${EDK2_FLAGS}
+
+    #
+    # Compile final image
+    #
+    _pack_image
+
+    echo "Build done: RK3588_NOR_FLASH.img"
 }
 
-function _clean(){ rm --one-file-system --recursive --force "${OUTDIR}"/workspace "${OUTDIR}"/RK3588_*.img "${OUTDIR}"/uefi-*.img*; }
+function _clean() { rm --one-file-system --recursive --force "${OUTDIR}"/workspace "${OUTDIR}"/RK3588_*.img; }
+function _distclean() { if [ -d .git ]; then git clean -xdf; else _clean; fi; }
 
-function _distclean(){ if [ -d .git ];then git clean -xdf;else _clean;fi; }
-
-OUTDIR="${PWD}"
-ROOTDIR="$(realpath "$(dirname "$0")")"
-cd "${ROOTDIR}"||exit 1
+#
+# Default variables
+#
 typeset -l DEVICE
-typeset -u MODE
+typeset -u RELEASE_TYPE
 DEVICE=""
-MODE=DEBUG
+RELEASE_TYPE=DEBUG
+TOOLCHAIN=GCC
+OPEN_TFA=1
+TFA_FLAGS=""
+EDK2_FLAGS=""
 CLEAN=false
 DISTCLEAN=false
-TOOLCHAIN=GCC
-BUILD_FLAGS=""
-export ROOTDIR OUTDIR
-export GEN_ROOTFS=true
-export BUILD_GUI=false
-OPTS="$(getopt -o t:d:haCDO:r -l toolchain:,device:,help,all,skip-rootfs-gen,gui,clean,distclean,outputdir:,release:,build-flags: -n 'build.sh' -- "$@")"||exit 1
+OUTDIR="${PWD}"
+
+#
+# Get options
+#
+OPTS=$(getopt -o "d:r:t:CDh" -l "device:,release:,toolchain:,open-tfa:,tfa-flags:,edk2-flags:,clean,distclean,help" -n build.sh -- "${@}") || _help $?
 eval set -- "${OPTS}"
-while true
-do	case "${1}" in
-		-d|--device) DEVICE="${2}";shift 2;;
-		-a|--all) DEVICE=all;shift;;
-		-C|--clean) CLEAN=true;shift;;
-		-D|--distclean) DISTCLEAN=true;shift;;
-		-O|--outputdir) OUTDIR="${2}";shift 2;;
-		--skip-rootfs-gen) GEN_ROOTFS=false;shift;;
-		--gui) BUILD_GUI=true;shift;;
-		-r|--release) MODE="${2}";shift 2;;
-		-t|--toolchain) TOOLCHAIN="${2}";shift 2;;
-		--build-flags) BUILD_FLAGS="${2}";shift 2;;
-		-h|--help) _help 0;shift;;
-		--) shift;break;;
-		*) _help 1;;
-	esac
+while true; do
+    case "${1}" in
+        -d|--device) DEVICE="${2}"; shift 2 ;;
+        -r|--release) RELEASE_TYPE="${2}"; shift 2 ;;
+        -t|--toolchain) TOOLCHAIN="${2}"; shift 2 ;;
+        --open-tfa) OPEN_TFA="${2}"; shift 2 ;;
+        --tfa-flags) TFA_FLAGS="${2}"; shift 2 ;;
+        --edk2-flags) EDK2_FLAGS="${2}"; shift 2 ;;
+        -C|--clean) CLEAN=true; shift ;;
+        -D|--distclean) DISTCLEAN=true; shift ;;
+        -h|--help) _help 0; shift ;;
+        --) shift; break ;;
+        *) break ;;
+    esac
 done
-if "${DISTCLEAN}";then _distclean;exit "$?";fi
-if "${CLEAN}";then _clean;exit "$?";fi
-[ -z "${DEVICE}" ]&&_help 1
-
-if ! [ -f edk2/edksetup.sh ] && ! [ -f ../edk2/edksetup.sh ]
-then
-	set -e
-	echo "SKIP Updating submodules"
-	set +e
+if [[ -n "${@}" ]]; then
+    echo "Invalid additional arguments '${@}'"
+    _help 1
 fi
 
-for i in "${SIMPLE_INIT}" ./simple-init ../simple-init
-do
-	if [ -n "${i}" ]&&[ -f "${i}/SimpleInit.inc" ]
-	then
-		_SIMPLE_INIT="$(realpath "${i}")"
-		break
-	fi
-done
+if "${DISTCLEAN}"; then _distclean; exit "$?"; fi
+if "${CLEAN}"; then _clean; exit "$?"; fi
 
-[ -n "${_SIMPLE_INIT}" ]||[ ${BUILD_GUI} == false ]||error "SimpleInit not found, please see README.md"
-[ -f "configs/${DEVICE}.conf" ]||[ "${DEVICE}" == "all" ]||_error "Device configuration not found"
+[ -z "${DEVICE}" ] && _help 1
+[ -f "configs/${DEVICE}.conf" ] || [ "${DEVICE}" == "all" ] || _error "Device configuration not found"
+
+#
+# Get machine architecture
+#
+MACHINE_TYPE=$(uname -m)
+
+# Fix-up possible differences in reported arch
+if [ ${MACHINE_TYPE} == 'arm64' ]; then
+    MACHINE_TYPE='aarch64'
+elif [ ${MACHINE_TYPE} == 'amd64' ]; then
+    MACHINE_TYPE='x86_64'
+fi
+
+if [ ${MACHINE_TYPE} != 'aarch64' ]; then
+    export CROSS_COMPILE="${CROSS_COMPILE:-aarch64-linux-gnu-}"
+fi
+
+GIT_COMMIT="$(git describe --tags --always)" || GIT_COMMIT="unknown"
 
-export CROSS_COMPILE="${CROSS_COMPILE:-aarch64-linux-gnu-}"
-export GCC_AARCH64_PREFIX="${CROSS_COMPILE}"
-export CLANG38_AARCH64_PREFIX="${CROSS_COMPILE}"
-# export PACKAGES_PATH="$_EDK2:$_EDK2_PLATFORMS:$_SIMPLE_INIT:$PWD"
-export PACKAGES_PATH="${ROOTDIR}/edk2:${ROOTDIR}/edk2-platforms:${ROOTDIR}/edk2-rockchip:${ROOTDIR}/edk2-rockchip-non-osi:${ROOTDIR}/edk2-non-osi:${ROOTDIR}:${_SIMPLE_INIT}"
 export WORKSPACE="${OUTDIR}/workspace"
-GITCOMMIT="$(git describe --tags --always)"||GITCOMMIT="unknown"
-export GITCOMMIT
+[ -d "${WORKSPACE}" ] || mkdir "${WORKSPACE}"
+
+ROOTDIR="$(realpath "$(dirname "$0")")"
+cd "${ROOTDIR}" || exit 1
+
+# Exit on first error
 set -e
 
-if "${BUILD_GUI}"
-then
-	mkdir -p "${_SIMPLE_INIT}/build" "${_SIMPLE_INIT}/root/usr/share/locale"
-	for i in "${_SIMPLE_INIT}/po/"*.po
-	do
-		[ -f "${i}" ]||continue
-		_name="$(basename "$i" .po)"
-		_path="${_SIMPLE_INIT}/root/usr/share/locale/${_name}/LC_MESSAGES"
-		mkdir -p "${_path}"
-		msgfmt -o "${_path}/simple-init.mo" "${i}"
-	done
-
-	if "${GEN_ROOTFS}"
-	then
-		bash "${_SIMPLE_INIT}/scripts/gen-rootfs-source.sh" \
-			"${_SIMPLE_INIT}" \
-			"${_SIMPLE_INIT}/build"
-	fi
-fi
-
 if [ "${DEVICE}" == "all" ]
 then
-	E=0
-	for i in configs/*.conf
-	do
-		DEV="$(basename "$i" .conf)"
-		if [ "${DEV}" != "RK3588" ]&&[ "${DEV}" != "RK3568" ]
-		then
-			echo "Building ${DEV}"
-			_build "${DEV}"||E="$?"
-		fi
-	done
-	exit "${E}"
+    for i in configs/*.conf; do
+        DEV="$(basename "$i" .conf)"
+        if [ "${DEV}" != "RK3588" ]
+        then
+            echo "Building ${DEV}"
+            _build "${DEV}"
+        fi
+    done
 else
-	_build "${DEVICE}"
+    _build "${DEVICE}"
 fi

configs/RK3588.conf

@@ -1,2 +1,3 @@
 MINIALL_INI=RK3588MINIALL.ini
 TRUST_INI=RK3588TRUST.ini
+TFA_PLAT=rk3588_reference_pmic

configs/aio-3588q.conf

@@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc
+PLATFORM_NAME=AIO-3588Q
+SOC=RK3588

configs/fydetab-duo.conf

@@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/FydeInnovations/FydetabDuo/FydetabDuo.dsc
+PLATFORM_NAME=FydetabDuo
+SOC=RK3588

configs/itx-3588j.conf

@@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.dsc
+PLATFORM_NAME=ITX-3588J
+SOC=RK3588

configs/nanopc-cm3588-nas.conf

@@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/NanoPC-CM3588-NAS.dsc
+PLATFORM_NAME=NanoPC-CM3588-NAS
+SOC=RK3588

configs/nanopi-m6.conf

@@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/FriendlyElec/NanoPi-M6/NanoPi-M6.dsc
+PLATFORM_NAME=NanoPi-M6
+SOC=RK3588

configs/powerstation-6.conf

@@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/BuzzTV/PowerStation6/PowerStation6.dsc
+PLATFORM_NAME=PowerStation6
+SOC=RK3588

configs/rock-5-itx.conf

@@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/Radxa/ROCK5ITX/ROCK5ITX.dsc
+PLATFORM_NAME=ROCK5ITX
+SOC=RK3588

configs/rock-5bplus.conf

@@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/Radxa/ROCK5BPlus/ROCK5BPlus.dsc
+PLATFORM_NAME=ROCK5BPlus
+SOC=RK3588

devicetree/mainline/README.md

@@ -0,0 +1,2 @@
+# Rockchip Mainline Device Trees
+New board files, small additions and fixes reusing existing bindings are accepted here, but only as a stopgap until they get merged upstream.

devicetree/mainline/rk3588-buzztv-p6.dts

@@ -0,0 +1,950 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024, Mario Bălănică <mariobalanica02@gmail.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3588.dtsi"
+
+/ {
+	model = "BuzzTV P6";
+	compatible = "buzztv,p6", "rockchip,rk3588";
+
+	aliases {
+		ethernet0 = &gmac1;
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	hdmi0-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi0_con_in: endpoint {
+				remote-endpoint = <&hdmi0_out_con>;
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_pins>;
+
+		green_led: led-0 {
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+
+		red_led: led-1 {
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	ir-receiver {
+		compatible = "gpio-ir-receiver";
+		gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&ir_receiver_pin>;
+	};
+
+	vcc12v_dcin: regulator-vcc12v-dcin {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc5v0_sys: regulator-vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc5v0_usb: regulator-vcc5v0-usb {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc5v0_host: regulator-vcc5v0-host {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_host";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+
+	vbus5v0_typec: regulator-vbus5v0-typec {
+		compatible = "regulator-fixed";
+		regulator-name = "vbus5v0_typec";
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&typec5v_pwren>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+
+	vcc3v3_pcie30: regulator-vcc3v3-pcie30 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie30";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie3_vcc3v3_en>;
+		startup-delay-us = <5000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc_3v3_sd_s0: regulator-vcc-3v3-sd-s0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_sd_s0";
+		regulator-boot-on;
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		enable-active-high;
+		gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sd_s0_pwr>;
+		vin-supply = <&vcc_3v3_s3>;
+	};
+
+	vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v1_nldo_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+};
+
+&combphy1_ps {
+	status = "okay";
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu_s0>;
+	status = "okay";
+};
+
+&hdmi0 {
+	status = "okay";
+};
+
+&hdmi0_in {
+	hdmi0_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi0>;
+	};
+};
+
+&hdmi0_out {
+	hdmi0_out_con: endpoint {
+		remote-endpoint = <&hdmi0_con_in>;
+	};
+};
+
+&hdptxphy_hdmi0 {
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0m2_xfer>;
+	status = "okay";
+
+	vdd_cpu_big0_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big0_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_cpu_big1_s0: regulator@43 {
+		compatible = "rockchip,rk8603", "rockchip,rk8602";
+		reg = <0x43>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big1_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1m2_xfer>;
+	status = "okay";
+
+	vdd_npu_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_npu_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <950000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c6 {
+	status = "okay";
+
+	fusb302: typec-portc@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usbc0_int>;
+		vbus-supply = <&vbus5v0_typec>;
+
+		usb_con: connector {
+			compatible = "usb-c-connector";
+			data-role = "dual";
+			label = "USB-C";
+			power-role = "source";
+			source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					usbc0_orien_sw: endpoint {
+						remote-endpoint = <&usbdp_phy0_orientation_switch>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					usbc0_role_sw: endpoint {
+						remote-endpoint = <&dwc3_0_role_switch>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					dp_altmode_mux: endpoint {
+						remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
+					};
+				};
+			};
+		};
+	};
+
+	hym8563: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-output-names = "hym8563";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hym8563_int>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+		wakeup-source;
+	};
+};
+
+/* RTL8852BE */
+&pcie2x1l0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_0_rst>;
+	reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&pcie30phy {
+	/*
+	 * pcie3x4 is limited to 3x2 and requires x2 x2 PHY bifurcation to work.
+	 * pcie3x2, however, is unused and needs to remain disabled.
+	 */
+	data-lanes = <1 1 2 2>;
+	status = "okay";
+};
+
+/* M.2 M key */
+&pcie3x4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie3_rst>;
+	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie30>;
+	status = "okay";
+};
+
+&gmac1 {
+	clock_in_out = "output";
+	phy-handle = <&rgmii_phy1>;
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1_miim
+		     &gmac1_tx_bus2
+		     &gmac1_rx_bus2
+		     &gmac1_rgmii_clk
+		     &gmac1_rgmii_bus>;
+	rx_delay = <0x00>;
+	tx_delay = <0x43>;
+	status = "okay";
+};
+
+&mdio1 {
+	/* RTL8211F */
+	rgmii_phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-id001c.c916";
+		reg = <0x1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&rtl8211f_rst>;
+		reset-assert-us = <20000>;
+		reset-deassert-us = <100000>;
+		reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&pinctrl {
+	hym8563 {
+		hym8563_int: hym8563-int {
+			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	leds {
+		led_pins: led-pins {
+			rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>,
+					<3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	ir-receiver {
+		ir_receiver_pin: ir-receiver-pin {
+			rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie2 {
+		pcie2_0_rst: pcie2-0-rst {
+			rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie3 {
+		pcie3_rst: pcie3-rst {
+			rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie3_vcc3v3_en: pcie3-vcc3v3-en {
+			rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	rtl8211f {
+		rtl8211f_rst: rtl8211f-rst {
+			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb-typec {
+		usbc0_int: usbc0-int {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		typec5v_pwren: typec5v-pwren {
+			rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sdmmc {
+		sd_s0_pwr: sd-s0-pwr {
+			rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	bluetooth {
+		bt_reset: bt-reset {
+			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_host_wake: bt-host-wake {
+			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_dev_wake: bt-dev-wake {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&saradc {
+	vref-supply = <&avcc_1v8_s0>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	no-sdio;
+	no-sd;
+	non-removable;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	status = "okay";
+};
+
+&sdmmc {
+	max-frequency = <200000000>;
+	no-sdio;
+	no-mmc;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc_3v3_sd_s0>;
+	vqmmc-supply = <&vccio_sd_s0>;
+	status = "okay";
+};
+
+&spi2 {
+	status = "okay";
+	assigned-clocks = <&cru CLK_SPI2>;
+	assigned-clock-rates = <200000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+	num-cs = <1>;
+
+	pmic@0 {
+		compatible = "rockchip,rk806";
+		spi-max-frequency = <1000000>;
+		reg = <0x0>;
+
+		interrupt-parent = <&gpio0>;
+		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+			    <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+
+		system-power-controller;
+
+		vcc1-supply = <&vcc5v0_sys>;
+		vcc2-supply = <&vcc5v0_sys>;
+		vcc3-supply = <&vcc5v0_sys>;
+		vcc4-supply = <&vcc5v0_sys>;
+		vcc5-supply = <&vcc5v0_sys>;
+		vcc6-supply = <&vcc5v0_sys>;
+		vcc7-supply = <&vcc5v0_sys>;
+		vcc8-supply = <&vcc5v0_sys>;
+		vcc9-supply = <&vcc5v0_sys>;
+		vcc10-supply = <&vcc5v0_sys>;
+		vcc11-supply = <&vcc_2v0_pldo_s3>;
+		vcc12-supply = <&vcc5v0_sys>;
+		vcc13-supply = <&vcc_1v1_nldo_s3>;
+		vcc14-supply = <&vcc_1v1_nldo_s3>;
+		vcca-supply = <&vcc5v0_sys>;
+
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		rk806_dvs1_null: dvs1-null-pins {
+			pins = "gpio_pwrctrl1";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs2_null: dvs2-null-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs3_null: dvs3-null-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun0";
+		};
+
+		regulators {
+			vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_gpu_s0";
+				regulator-enable-ramp-delay = <400>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_cpu_lit_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_log_s0: dcdc-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <750000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_log_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_vdenc_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_ddr_s0: dcdc-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <900000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_ddr_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			vdd2_ddr_s3: dcdc-reg6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vdd2_ddr_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_2v0_pldo_s3: dcdc-reg7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_2v0_pldo_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <2000000>;
+				};
+			};
+
+			vcc_3v3_s3: dcdc-reg8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc_3v3_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vddq_ddr_s0: dcdc-reg9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vddq_ddr_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s3: dcdc-reg10 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avcc_1v8_s0: pldo-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "avcc_1v8_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s0: pldo-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avdd_1v2_s0: pldo-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-name = "avdd_1v2_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3_s0: pldo-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vcc_3v3_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd_s0: pldo-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vccio_sd_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			pldo6_s3: pldo-reg6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "pldo6_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_0v75_s3: nldo-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "vdd_0v75_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_ddr_pll_s0: nldo-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-name = "vdd_ddr_pll_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			avdd_0v75_s0: nldo-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "avdd_0v75_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v85_s0: nldo-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-name = "vdd_0v85_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v75_s0: nldo-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "vdd_0v75_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-0 = <&uart2m0_xfer>;
+	status = "okay";
+};
+
+&uart9 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart9m0_xfer>, <&uart9m0_rtsn>, <&uart9m0_ctsn>;
+	uart-has-rtscts;
+	status = "okay";
+
+	bluetooth {
+		compatible = "realtek,rtl8852bs-bt", "realtek,rtl8822cs-bt";
+		enable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+		host-wake-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+		device-wake-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_reset>, <&bt_host_wake>, <&bt_dev_wake>;
+	};
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	status = "okay";
+};
+
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&u2phy2 {
+	status = "okay";
+};
+
+&u2phy2_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&usbdp_phy0 {
+	mode-switch;
+	orientation-switch;
+	sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
+	sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usbdp_phy0_orientation_switch: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_orien_sw>;
+		};
+
+		usbdp_phy0_dp_altmode_mux: endpoint@1 {
+			reg = <1>;
+			remote-endpoint = <&dp_altmode_mux>;
+		};
+	};
+};
+
+&usbdp_phy1 {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+/* Front USB Type-C port */
+&usb_host0_xhci {
+	usb-role-switch;
+	status = "okay";
+
+	port {
+		dwc3_0_role_switch: endpoint {
+			remote-endpoint = <&usbc0_role_sw>;
+		};
+	};
+};
+
+/* Front USB 2.0 port */
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+/* Front USB 3.0 port */
+&usb_host1_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi0_in_vp0>;
+	};
+};

devicetree/vendor/README.md

@@ -0,0 +1,20 @@
+# Rockchip Vendor BSP Device Trees
+## Sources
+* <https://github.com/armbian/linux-rockchip/tree/f3fb30ac9de06b41fb621d17bc53603f1f48ac90/arch/arm64/boot/dts/rockchip>
+  * Updated to `rk-6.1-rkr1` branch, currently called `vendor` branch in armbian/build
+
+* roc-rk3588s-pc: <https://gitlab.com/firefly-linux/kernel/-/tree/b8646da2122f45a2c02082d949427b80d2e89b1f/arch/arm64/boot/dts/rockchip>
+
+* itx-3588j: <https://gitlab.com/firefly-linux/kernel/-/tree/e14c28295dd7ee8f807899e9b0b7da5f79742e4f/arch/arm64/boot/dts/rockchip>
+  (note: in the dtb given here, the builtin bootargs in the source above were commented out
+   before building. Not sure if that was a necessary step - SS)
+
+* rk3588-firefly-aio-3588q: <https://gitlab.com/firefly-linux/kernel/-/tree/fa0e053fd911339b825407cb6d4b167fad7cdc49/arch/arm64/boot/dts/rockchip>
+
+* rk3588-rock-5b-plus: <https://github.com/radxa/kernel/blob/3b95df6d8bf567857b69e5266f1cb0651a6cfb3e/arch/arm64/boot/dts/rockchip/>
+
+* rk3588s-fydetab-duo: <https://github.com/Linux-for-Fydetab-Duo/linux-rockchip/tree/14294048d2a0deb7f38c890329aded87038d3299/arch/arm64/boot/dts/rockchip>
+  (note: dtb taken from the `noble` branch which is based on the rockchip 6.1 rkr3 bsp kernel)
+
+## License
+SPDX-License-Identifier: GPL-2.0-only

edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/README.md

@@ -1,8 +0,0 @@
-# Rockchip Platform Device Trees
-## Sources
-* <https://github.com/armbian/linux-rockchip/tree/a8384552a2e009797aa5b3e9a046d30e8d2e5d3c/arch/arm64/boot/dts/rockchip>
-
-* roc-rk3588s-pc: <https://gitlab.com/firefly-linux/kernel/-/tree/b8646da2122f45a2c02082d949427b80d2e89b1f/arch/arm64/boot/dts/rockchip>
-
-## License
-SPDX-License-Identifier: GPL-2.0-only

edk2-rockchip/Platform/Ameridroid/IndiedroidNova/AcpiTables/AcpiTables.inf

@@ -32,15 +32,6 @@
   $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
   $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
   $(RK_COMMON_ACPI_DIR)/Pptt.aslc
-  $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl
-  $(RK_COMMON_ACPI_DIR)/Sata0.asl
-  $(RK_COMMON_ACPI_DIR)/Sata1.asl
-  $(RK_COMMON_ACPI_DIR)/Sata2.asl
-  $(RK_COMMON_ACPI_DIR)/Usb2Host.asl
 
 [Packages]
   ArmPkg/ArmPkg.dec
@@ -49,6 +40,7 @@
   MdeModulePkg/MdeModulePkg.dec
   MdePkg/MdePkg.dec
   Silicon/Rockchip/RockchipPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
 
 [FixedPcd]
   gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
@@ -59,3 +51,8 @@
   gArmTokenSpaceGuid.PcdGicDistributorBase
   gArmTokenSpaceGuid.PcdGicRedistributorsBase
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gRK3588TokenSpaceGuid.PcdI2S0Supported
+  gRK3588TokenSpaceGuid.PcdI2S1Supported
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken

edk2-rockchip/Platform/Ameridroid/IndiedroidNova/AcpiTables/Dsdt.asl

@@ -13,22 +13,41 @@
 
 #include "AcpiTables.h"
 
+#define BOARD_I2S0_TPLG "i2s-jack"
+
+#define BOARD_AUDIO_CODEC_HID "ESSX8388"
+#define BOARD_CODEC_I2C "\\_SB.I2C7"
+#define BOARD_CODEC_I2C_ADDR 0x11
+#define BOARD_CODEC_GPIO "\\_SB.GPI4"
+#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PA7
+
 DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588  ", 2)
 {
   Scope (\_SB_)
   {
+    include ("DsdtCommon.asl")
+
     include ("Cpu.asl")
 
+    include ("Pcie.asl")
+    include ("Sata.asl")
     include ("Emmc.asl")
     include ("Sdhc.asl")
+    include ("Dma.asl")
     // include ("Gmac.asl")
-    // include ("Gpio.asl")
-    // include ("I2c.asl")
+    include ("Gpio.asl")
+    include ("I2c.asl")
     include ("Uart.asl")
     // include ("Spi.asl")
 
-    include ("Usb1Host.asl")
+    include ("I2s.asl")
+
+    include ("Usb2Host.asl")
     include ("Usb3Host0.asl")
     include ("Usb3Host2.asl")
+
+    Scope (I2C7) {
+      include ("Es8388.asl")
+    }
   }
 }

edk2-rockchip/Platform/Ameridroid/IndiedroidNova/DeviceTree/Mainline.inf

@@ -0,0 +1,21 @@
+#/** @file
+#
+#  Copyright (c) 2024, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = DeviceTree-Mainline
+  FILE_GUID                      = 84492e97-a10f-49a7-85e9-025d1966b343
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+
+[Sources]
+  devicetree/mainline/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts
+
+[Packages]
+  MdePkg/MdePkg.dec
+  Silicon/Rockchip/RockchipPkg.dec

edk2-rockchip/Platform/Ameridroid/IndiedroidNova/DeviceTree/Vendor.inf

@@ -0,0 +1,17 @@
+#/** @file
+#
+#  Copyright (c) 2024, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = DeviceTree-Vendor
+  FILE_GUID                      = d58b4028-43d8-4e97-87d4-4e3716136580
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+
+[Binaries]
+  BIN|devicetree/vendor/rk3588s-9tripod-linux.dtb

edk2-rockchip/Platform/Ameridroid/IndiedroidNova/IndiedroidNova.Modules.fdf.inc

@@ -1,6 +1,6 @@
 ## @file
 #
-#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+#  Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -10,9 +10,8 @@
   INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf
 
   # Device Tree Support
-  FILE FREEFORM = gDtPlatformDefaultDtbFileGuid {
-    SECTION RAW = Platform/Rockchip/DeviceTree/rk3588s-9tripod-linux.dtb
-  }
+  INF RuleOverride = DTB $(PLATFORM_DIRECTORY)/DeviceTree/Vendor.inf
+  INF RuleOverride = DTB $(PLATFORM_DIRECTORY)/DeviceTree/Mainline.inf
 
   # Splash screen logo
   INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf

edk2-rockchip/Platform/Ameridroid/IndiedroidNova/IndiedroidNova.dsc

@@ -1,7 +1,7 @@
 ## @file
 #
 #  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
-#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+#  Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -65,9 +65,9 @@
   gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588s-9tripod-linux"
 
   # I2C
-  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51 }
-  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6 }
-  gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51, 0x11 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6, 0x7 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE, FALSE }
   gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
   gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 }
   gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) }
@@ -93,6 +93,11 @@
   gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE
   gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 }
 
+  #
+  # I2S
+  #
+  gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE
+
   #
   # On-Board fan output
   #
@@ -107,5 +112,9 @@
   # ACPI Support
   $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf
 
+  # Device Tree Support
+  $(PLATFORM_DIRECTORY)/DeviceTree/Vendor.inf
+  $(PLATFORM_DIRECTORY)/DeviceTree/Mainline.inf
+
   # Splash screen logo
   $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf

edk2-rockchip/Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -1,10 +1,12 @@
 /** @file
 *
 *  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+*  Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
 *
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
 *
 **/
+
 #include <Base.h>
 #include <Library/DebugLib.h>
 #include <Library/IoLib.h>
@@ -13,6 +15,7 @@
 #include <Library/Rk3588Pcie.h>
 #include <Library/PWMLib.h>
 #include <Soc.h>
+#include <VarStoreData.h>
 
 static struct regulator_init_data rk806_init_data[] = {
   /* Master PMIC */
@@ -145,32 +148,32 @@ I2cIomux (
 {
   switch (id) {
   case 0:
-    /* io mux M2 */
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
+    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
+    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
     break;
   case 1:
-    /* io mux */
-    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
-    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
     break;
   case 2:
-    /* io mux */
-    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
-    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
-    PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
-    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
     break;
   case 3:
     break;
   case 4:
+    GpioPinSetFunction(1, GPIO_PIN_PA3, 9); //i2c4_scl_m3
+    GpioPinSetFunction(1, GPIO_PIN_PA2, 9); //i2c4_sda_m3
     break;
   case 5:
+    GpioPinSetFunction(3, GPIO_PIN_PC7, 9); //i2c5_scl_m0
+    GpioPinSetFunction(3, GPIO_PIN_PD0, 9); //i2c5_sda_m0
     break;
   case 6:
-    /* io mux M3 */
-    BUS_IOC->GPIO4B_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0090;
-    BUS_IOC->GPIO4B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
+    GpioPinSetFunction(4, GPIO_PIN_PB1, 9); //i2c6_scl_m3
+    GpioPinSetFunction(4, GPIO_PIN_PB0, 9); //i2c6_sda_m3
+    break;
+  case 7:
+    GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0
+    GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0
     break;
   default:
     break;
@@ -285,6 +288,29 @@ PlatformSetStatusLed (
   // No controllable LEDs on this platform
 }
 
+CONST EFI_GUID *
+EFIAPI
+PlatformGetDtbFileGuid (
+  IN UINT32 CompatMode
+  )
+{
+  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+    0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
+  };
+  STATIC CONST EFI_GUID MainlineDtbFileGuid = {       // DeviceTree/Mainline.inf
+    0x84492e97, 0xa10f, 0x49a7, { 0x85, 0xe9, 0x02, 0x5d, 0x19, 0x66, 0xb3, 0x43 }
+  };
+
+  switch (CompatMode) {
+    case FDT_COMPAT_MODE_VENDOR:
+      return &VendorDtbFileGuid;
+    case FDT_COMPAT_MODE_MAINLINE:
+      return &MainlineDtbFileGuid;
+  }
+
+  return NULL;
+}
+
 VOID
 EFIAPI
 PlatformEarlyInit (
@@ -292,4 +318,5 @@ PlatformEarlyInit (
   )
 {
   // Configure various things specific to this platform
+  GpioPinSetFunction(4, GPIO_PIN_PA7, 0); //jdet
 }

edk2-rockchip/Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.inf

@@ -1,8 +1,11 @@
+#/** @file
 #
 #  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#  Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
+#**/
 
 [Defines]
   INF_VERSION                    = 0x00010019
@@ -11,7 +14,6 @@
   MODULE_TYPE                    = BASE
   VERSION_STRING                 = 1.0
   LIBRARY_CLASS                  = RockchipPlatformLib
-  RKPLATLIB_COMMON_DIR           = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon
 
 [Packages]
   EmbeddedPkg/EmbeddedPkg.dec
@@ -32,4 +34,3 @@
 
 [Sources.common]
   RockchipPlatformLib.c
-  $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c

edk2-rockchip/Platform/BuzzTV/Drivers/LogoDxe/Logo.c

@@ -0,0 +1,144 @@
+/** @file
+  Logo DXE Driver, install Edkii Platform Logo protocol.
+
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+  Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Protocol/HiiDatabase.h>
+#include <Protocol/GraphicsOutput.h>
+#include <Protocol/HiiImageEx.h>
+#include <Protocol/PlatformLogo.h>
+#include <Protocol/HiiPackageList.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+
+typedef struct {
+  EFI_IMAGE_ID                          ImageId;
+  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
+  INTN                                  OffsetX;
+  INTN                                  OffsetY;
+} LOGO_ENTRY;
+
+STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
+STATIC EFI_HII_HANDLE            mHiiHandle;
+STATIC LOGO_ENTRY                mLogos[] = {
+  {
+    IMAGE_TOKEN (IMG_LOGO),
+    EdkiiPlatformLogoDisplayAttributeCenter,
+    0,
+    0
+  }
+};
+
+/**
+  Load a platform logo image and return its data and attributes.
+
+  @param This              The pointer to this protocol instance.
+  @param Instance          The visible image instance is found.
+  @param Image             Points to the image.
+  @param Attribute         The display attributes of the image returned.
+  @param OffsetX           The X offset of the image regarding the Attribute.
+  @param OffsetY           The Y offset of the image regarding the Attribute.
+
+  @retval EFI_SUCCESS      The image was fetched successfully.
+  @retval EFI_NOT_FOUND    The specified image could not be found.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GetImage (
+  IN     EDKII_PLATFORM_LOGO_PROTOCOL          *This,
+  IN OUT UINT32                                *Instance,
+     OUT EFI_IMAGE_INPUT                       *Image,
+     OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
+     OUT INTN                                  *OffsetX,
+     OUT INTN                                  *OffsetY
+  )
+{
+  UINT32 Current;
+
+  if (Instance == NULL || Image == NULL ||
+      Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Current = *Instance;
+  if (Current >= ARRAY_SIZE (mLogos)) {
+    return EFI_NOT_FOUND;
+  }
+
+  (*Instance)++;
+  *Attribute = mLogos[Current].Attribute;
+  *OffsetX   = mLogos[Current].OffsetX;
+  *OffsetY   = mLogos[Current].OffsetY;
+
+  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
+                        mLogos[Current].ImageId, Image);
+}
+
+STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+  GetImage
+};
+
+/**
+  Entrypoint of this module.
+
+  This function is the entrypoint of this module. It installs the Edkii
+  Platform Logo protocol.
+
+  @param  ImageHandle       The firmware allocated handle for the EFI image.
+  @param  SystemTable       A pointer to the EFI System Table.
+
+  @retval EFI_SUCCESS       The entry point is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeLogo (
+  IN EFI_HANDLE               ImageHandle,
+  IN EFI_SYSTEM_TABLE         *SystemTable
+  )
+{
+  EFI_STATUS                  Status;
+  EFI_HII_PACKAGE_LIST_HEADER *PackageList;
+  EFI_HII_DATABASE_PROTOCOL   *HiiDatabase;
+  EFI_HANDLE                  Handle;
+
+  Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
+                  (VOID **) &HiiDatabase);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
+                  (VOID **) &mHiiImageEx);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Retrieve HII package list from ImageHandle
+  //
+  Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
+                  (VOID **) &PackageList, ImageHandle, NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR,
+      "HII Image Package with logo not found in PE/COFF resource section\n"));
+    return Status;
+  }
+
+  //
+  // Publish HII package list to HII Database.
+  //
+  Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
+                          &mHiiHandle);
+  if (!EFI_ERROR (Status)) {
+    Handle = NULL;
+    Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
+                    &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
+  }
+  return Status;
+}

edk2-rockchip/Platform/BuzzTV/Drivers/LogoDxe/Logo.idf

@@ -0,0 +1,10 @@
+// @file
+// Platform Logo image definition file.
+//
+// Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+// Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+
+#image IMG_LOGO Logo.bmp

edk2-rockchip/Platform/BuzzTV/Drivers/LogoDxe/LogoDxe.inf

@@ -0,0 +1,48 @@
+## @file
+#  The default logo bitmap picture shown on setup screen.
+#
+#  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+#  Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = LogoDxe
+  FILE_GUID                      = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = InitializeLogo
+#
+#  This flag specifies whether HII resource section is generated into PE image.
+#
+  UEFI_HII_RESOURCE_SECTION      = TRUE
+
+[Sources]
+  Logo.bmp
+  Logo.c
+  Logo.idf
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  DebugLib
+
+[Protocols]
+  gEfiHiiDatabaseProtocolGuid        ## CONSUMES
+  gEfiHiiImageExProtocolGuid         ## CONSUMES
+  gEfiHiiPackageListProtocolGuid     ## PRODUCES CONSUMES
+  gEdkiiPlatformLogoProtocolGuid     ## PRODUCES
+
+[Depex]
+  gEfiHiiDatabaseProtocolGuid AND
+  gEfiHiiImageExProtocolGuid

edk2-rockchip/Platform/BuzzTV/PowerStation6/AcpiTables/AcpiTables.inf

@@ -0,0 +1,58 @@
+#/** @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2019-2021, ARM Limited. All rights reserved.
+#  Copyright (c) Microsoft Corporation. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+  RK_COMMON_ACPI_DIR             = Silicon/Rockchip/RK3588/AcpiTables
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+
+[Sources]
+  Dsdt.asl
+  $(RK_COMMON_ACPI_DIR)/Madt.aslc
+  $(RK_COMMON_ACPI_DIR)/Fadt.aslc
+  $(RK_COMMON_ACPI_DIR)/Gtdt.aslc
+  $(RK_COMMON_ACPI_DIR)/Spcr.aslc
+  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
+  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
+  $(RK_COMMON_ACPI_DIR)/Pptt.aslc
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Rockchip/RockchipPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gRK3588TokenSpaceGuid.PcdI2S0Supported
+  gRK3588TokenSpaceGuid.PcdI2S1Supported
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken

edk2-rockchip/Platform/BuzzTV/PowerStation6/AcpiTables/Dsdt.asl

@@ -0,0 +1,38 @@
+/** @file
+ *
+ *  Differentiated System Definition Table (DSDT)
+ *
+ *  Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ *  Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
+ *  Copyright (c) Microsoft Corporation. All rights reserved.
+ *  Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include "AcpiTables.h"
+
+DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588  ", 2)
+{
+  Scope (\_SB_)
+  {
+    include ("DsdtCommon.asl")
+
+    include ("Cpu.asl")
+
+    include ("Pcie.asl")
+    include ("Sata.asl")
+    include ("Emmc.asl")
+    include ("Sdhc.asl")
+    include ("Dma.asl")
+    include ("Gmac1.asl")
+    include ("Gpio.asl")
+    include ("I2c.asl")
+    include ("Uart.asl")
+
+    include ("Usb2Host.asl")
+    include ("Usb3Host0.asl")
+    include ("Usb3Host1.asl")
+  }
+}

edk2-rockchip/Platform/BuzzTV/PowerStation6/DeviceTree/Mainline.inf

@@ -0,0 +1,21 @@
+#/** @file
+#
+#  Copyright (c) 2024, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = DeviceTree-Mainline
+  FILE_GUID                      = 84492e97-a10f-49a7-85e9-025d1966b343
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+
+[Sources]
+  devicetree/mainline/rk3588-buzztv-p6.dts
+
+[Packages]
+  MdePkg/MdePkg.dec
+  Silicon/Rockchip/RockchipPkg.dec

edk2-rockchip/Platform/BuzzTV/PowerStation6/DeviceTree/Vendor.inf

@@ -0,0 +1,17 @@
+#/** @file
+#
+#  Copyright (c) 2024, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = DeviceTree-Vendor
+  FILE_GUID                      = d58b4028-43d8-4e97-87d4-4e3716136580
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+
+[Binaries]
+  BIN|devicetree/vendor/rk3588-buzztv-p6-android.dtb

edk2-rockchip/Platform/BuzzTV/PowerStation6/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -0,0 +1,387 @@
+/** @file
+*
+*  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+*  Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Base.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/GpioLib.h>
+#include <Library/RK806.h>
+#include <Library/Rk3588Pcie.h>
+#include <Soc.h>
+#include <VarStoreData.h>
+
+static struct regulator_init_data rk806_init_data[] = {
+  /* Master PMIC */
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
+  //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 837500),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+
+  /* No dual PMICs on this platform */
+};
+
+VOID
+EFIAPI
+SdmmcIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux (microSD socket) */
+  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+
+  /* vcc_3v3_sd_s0 */
+  GpioPinWrite (4, GPIO_PIN_PA5, TRUE);
+  GpioPinSetDirection (4, GPIO_PIN_PA5, GPIO_PIN_OUTPUT);
+}
+
+VOID
+EFIAPI
+SdhciEmmcIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux */
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+}
+
+#define NS_CRU_BASE         0xFD7C0000
+#define CRU_CLKSEL_CON59    0x03EC
+#define CRU_CLKSEL_CON78    0x0438
+
+VOID
+EFIAPI
+Rk806SpiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
+  PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+}
+
+VOID
+EFIAPI
+Rk806Configure (
+  VOID
+  )
+{
+  UINTN RegCfgIndex;
+
+  RK806Init();
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
+    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+}
+
+VOID
+EFIAPI
+SetCPULittleVoltage (
+  IN UINT32 Microvolts
+  )
+{
+  struct regulator_init_data Rk806CpuLittleSupply =
+        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+
+  RK806RegulatorInit(Rk806CpuLittleSupply);
+}
+
+VOID
+EFIAPI
+NorFspiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
+             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
+#define FSPI_M1
+#if defined(FSPI_M0)
+   /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
+#elif defined(FSPI_M1)
+  /*FSPI M1*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
+#else
+  /*FSPI M2*/
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
+#endif
+}
+
+VOID
+EFIAPI
+GmacIomux (
+  IN UINT32 Id
+  )
+{
+  switch (Id) {
+    case 1:
+      /* gmac1 iomux */
+      BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111;
+      BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+      BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+      BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011;
+      BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100;
+
+      /* phy1 reset */
+      GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+GmacIoPhyReset (
+  UINT32   Id,
+  BOOLEAN  Enable
+  )
+{
+  switch (Id) {
+    case 1:
+      /* phy1 reset */
+      GpioPinWrite (3, GPIO_PIN_PB7, !Enable);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+NorFspiEnableClock (
+  UINT32 *CruBase
+  )
+{
+  UINTN BaseAddr = (UINTN) CruBase;
+
+  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+}
+
+VOID
+EFIAPI
+I2cIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
+    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
+    break;
+  case 1:
+    GpioPinSetFunction(0, GPIO_PIN_PD4, 9); //i2c1_scl_m2
+    GpioPinSetFunction(0, GPIO_PIN_PD5, 9); //i2c1_sda_m2
+    break;
+  case 2:
+    break;
+  case 3:
+    break;
+  case 4:
+    break;
+  case 5:
+    break;
+  case 6:
+    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
+    break;
+  case 7:
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+UsbPortPowerEnable (
+  VOID
+  )
+{
+  DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n"));
+
+  /* vcc5v0-host */
+  GpioPinWrite(4, GPIO_PIN_PB0, TRUE);
+  GpioPinSetDirection (4, GPIO_PIN_PB0, GPIO_PIN_OUTPUT);
+}
+
+VOID
+EFIAPI
+Usb2PhyResume (
+  VOID
+  )
+{
+  MmioWrite32(0xfd5d0008, 0x20000000);
+  MmioWrite32(0xfd5d4008, 0x20000000);
+  MmioWrite32(0xfd5d8008, 0x20000000);
+  MmioWrite32(0xfd5dc008, 0x20000000);
+  MmioWrite32(0xfd7f0a10, 0x07000700);
+  MmioWrite32(0xfd7f0a10, 0x07000000);
+}
+
+VOID
+EFIAPI
+PcieIoInit (
+  UINT32 Segment
+  )
+{
+  switch(Segment) {
+    case PCIE_SEGMENT_PCIE30X4: // M.2 M Key
+      /* reset */
+      GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
+      /* vcc3v3_pcie30 */
+      GpioPinSetDirection (2, GPIO_PIN_PC5, GPIO_PIN_OUTPUT);
+      break;
+    case PCIE_SEGMENT_PCIE20L0: // RTL8852BE
+      /* reset */
+      GpioPinSetDirection (1, GPIO_PIN_PB4, GPIO_PIN_OUTPUT);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+PciePowerEn (
+  UINT32 Segment,
+  BOOLEAN Enable
+  )
+{
+  switch(Segment) {
+    case PCIE_SEGMENT_PCIE30X4:
+      GpioPinWrite (2, GPIO_PIN_PC5, Enable);
+      break;
+    case PCIE_SEGMENT_PCIE20L0:
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+PciePeReset (
+  UINT32 Segment,
+  BOOLEAN Enable
+  )
+{
+  switch(Segment) {
+    case PCIE_SEGMENT_PCIE30X4:
+      GpioPinWrite (4, GPIO_PIN_PB6, !Enable);
+      break;
+    case PCIE_SEGMENT_PCIE20L0:
+      GpioPinWrite (1, GPIO_PIN_PB4, !Enable);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+PwmFanIoSetup (
+  VOID
+  )
+{
+}
+
+VOID
+EFIAPI
+PwmFanSetSpeed (
+  IN UINT32 Percentage
+  )
+{
+}
+
+VOID
+EFIAPI
+PlatformInitLeds (
+  VOID
+  )
+{
+  /* Status indicator */
+  GpioPinWrite (3, GPIO_PIN_PD0, TRUE);
+  GpioPinSetDirection (3, GPIO_PIN_PD0, GPIO_PIN_OUTPUT);
+
+  GpioPinWrite (3, GPIO_PIN_PD1, TRUE);
+  GpioPinSetDirection (3, GPIO_PIN_PD1, GPIO_PIN_OUTPUT);
+}
+
+VOID
+EFIAPI
+PlatformSetStatusLed (
+  IN BOOLEAN Enable
+  )
+{
+  GpioPinWrite (3, GPIO_PIN_PD0, !Enable);
+  GpioPinWrite (3, GPIO_PIN_PD1, !Enable);
+}
+
+CONST EFI_GUID *
+EFIAPI
+PlatformGetDtbFileGuid (
+  IN UINT32 CompatMode
+  )
+{
+  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+    0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
+  };
+  STATIC CONST EFI_GUID MainlineDtbFileGuid = {       // DeviceTree/Mainline.inf
+    0x84492e97, 0xa10f, 0x49a7, { 0x85, 0xe9, 0x02, 0x5d, 0x19, 0x66, 0xb3, 0x43 }
+  };
+
+  switch (CompatMode) {
+    case FDT_COMPAT_MODE_VENDOR:
+      return &VendorDtbFileGuid;
+    case FDT_COMPAT_MODE_MAINLINE:
+      return &MainlineDtbFileGuid;
+  }
+
+  return NULL;
+}
+
+VOID
+EFIAPI
+PlatformEarlyInit (
+  VOID
+  )
+{
+  // Configure various things specific to this platform
+}

edk2-rockchip/Platform/BuzzTV/PowerStation6/Library/RockchipPlatformLib/RockchipPlatformLib.inf

@@ -0,0 +1,35 @@
+#/** @file
+#
+#  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#  Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = RockchipPlatformLib
+  FILE_GUID                      = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RockchipPlatformLib
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  SerialPortLib
+  CruLib
+  GpioLib
+
+[Sources.common]
+  RockchipPlatformLib.c

edk2-rockchip/Platform/BuzzTV/PowerStation6/PowerStation6.Modules.fdf.inc

@@ -0,0 +1,17 @@
+## @file
+#
+#  Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+  # ACPI Support
+  INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf
+
+  # Device Tree Support
+  INF RuleOverride = DTB $(PLATFORM_DIRECTORY)/DeviceTree/Vendor.inf
+  INF RuleOverride = DTB $(PLATFORM_DIRECTORY)/DeviceTree/Mainline.inf
+
+  # Splash screen logo
+  INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf

edk2-rockchip/Platform/BuzzTV/PowerStation6/PowerStation6.dsc

@@ -0,0 +1,119 @@
+## @file
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = PowerStation6
+  PLATFORM_VENDOR                = BuzzTV
+  PLATFORM_GUID                  = 27b93a89-b2e0-4e50-b8a3-8c6616e9f3b0
+  PLATFORM_VERSION               = 0.2
+  DSC_SPECIFICATION              = 0x00010019
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  VENDOR_DIRECTORY               = Platform/$(PLATFORM_VENDOR)
+  PLATFORM_DIRECTORY             = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = Silicon/Rockchip/RK3588/RK3588.fdf
+  RK_PLATFORM_FVMAIN_MODULES     = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc
+
+  #
+  # HYM8563 RTC support
+  # I2C location configured by PCDs below.
+  #
+  DEFINE RK_RTC8563_ENABLE = TRUE
+
+  #
+  # RK3588-based platform
+  #
+!include Silicon/Rockchip/RK3588/RK3588Platform.dsc.inc
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+
+[LibraryClasses.common]
+  RockchipPlatformLib|$(PLATFORM_DIRECTORY)/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform.
+#
+################################################################################
+
+[PcdsFixedAtBuild.common]
+  # SMBIOS platform config
+  gRockchipTokenSpaceGuid.PcdPlatformName|"PowerStation 6"
+  gRockchipTokenSpaceGuid.PcdPlatformVendorName|"BuzzTV"
+  gRockchipTokenSpaceGuid.PcdFamilyName|"PowerStation"
+  gRockchipTokenSpaceGuid.PcdProductUrl|"https://buzztvglobal.com/products/powerstation-6"
+  gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588-buzztv-p6"
+
+  # I2C
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) }
+  gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
+  gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6
+
+  #
+  # CPU Performance default values
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX)
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX)
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX)
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY support flags and default values
+  #
+  # The PCIe 3x4 controller exposed at the M.2 M key slot is limited
+  # to 3x2 and requires x2 x2 PHY bifurcation to work.
+  # The dedicated 3x2 controller is unused and needs to remain disabled.
+  #
+  gRK3588TokenSpaceGuid.PcdPcie30PhyModeDefault|$(PCIE30_PHY_MODE_NANBNB)
+  gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_PCIE)
+
+  #
+  # USB/DP Combo PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdUsbDpPhy1Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 }
+  gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x0 }
+
+  #
+  # GMAC
+  #
+  gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x43
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform.
+#
+################################################################################
+[Components.common]
+  # ACPI Support
+  $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf
+
+  # Device Tree Support
+  $(PLATFORM_DIRECTORY)/DeviceTree/Vendor.inf
+  $(PLATFORM_DIRECTORY)/DeviceTree/Mainline.inf
+
+  # Splash screen logo
+  $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf

edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.Modules.fdf.inc

@@ -0,0 +1,16 @@
+## @file
+#
+#  Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+  # ACPI Support
+  INF RuleOverride = ACPITABLE Platform/Firefly/AIO-3588Q/AcpiTables/AcpiTables.inf
+
+  # Device Tree Support
+  INF RuleOverride = DTB Platform/Firefly/AIO-3588Q/DeviceTree/Vendor.inf
+
+  # Splash screen logo
+  INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf

edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc

@@ -0,0 +1,31 @@
+## @file
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = AIO-3588Q
+  PLATFORM_VENDOR                = Firefly
+  PLATFORM_GUID                  = 400f8259-7664-47df-b375-8ba262e4867e
+  PLATFORM_VERSION               = 0.2
+  DSC_SPECIFICATION              = 0x00010019
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  VENDOR_DIRECTORY               = Platform/$(PLATFORM_VENDOR)
+  PLATFORM_DIRECTORY             = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+
+  #
+  # Platform based on AIO-3588Q board
+  #
+!include Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc.inc

edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc.inc

@@ -0,0 +1,137 @@
+## @file
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  FLASH_DEFINITION               = Silicon/Rockchip/RK3588/RK3588.fdf
+  RK_PLATFORM_FVMAIN_MODULES     = Platform/Firefly/AIO-3588Q/AIO-3588Q.Modules.fdf.inc
+
+  #
+  # HYM8563 RTC support
+  # I2C location configured by PCDs below.
+  #
+  DEFINE RK_RTC8563_ENABLE = TRUE
+
+  #
+  # PCA9555 GPIO extender support
+  # I2C location configured by PCDs below.
+  #
+  DEFINE RK_PCA9555_ENABLE = TRUE
+
+  #
+  # RK3588-based platform
+  #
+!include Silicon/Rockchip/RK3588/RK3588Platform.dsc.inc
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+
+[LibraryClasses.common]
+  RockchipPlatformLib|Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform.
+#
+################################################################################
+
+[PcdsFixedAtBuild.common]
+  # SMBIOS platform config
+  gRockchipTokenSpaceGuid.PcdPlatformName|"AIO-3588Q"
+  gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Firefly"
+  gRockchipTokenSpaceGuid.PcdFamilyName|"AIO"
+  gRockchipTokenSpaceGuid.PcdProductUrl|"https://en.t-firefly.com/product/core/icore3588q"
+  gRockchipTokenSpaceGuid.PcdDeviceTreeName|"aio-3588q"
+
+  # I2C
+  # i2c0: pc9202@3c, rk8602@42, rk8603@43
+  # i2c1: rk8602@42 (npu)
+  # i2c3: es8388@11, XC7160b@1b, gc2053b@37, gc2093b@7e
+  # i2c6: pca9555@20, pca9555@21, fusb302@22, hym8563@51
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{           0x42,  0x43,  0x42,  0x11,  0x51, 0x20,  0x21,  0x22  }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{               0x0,   0x0,   0x1,   0x3,   0x6,  0x6,   0x6,   0x6   }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{     0x0,  0x0 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) }
+  gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
+  gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6
+  gRockchipTokenSpaceGuid.PcdPca9555Address|0x21
+  gRockchipTokenSpaceGuid.PcdPca9555Bus|0x6
+
+  #
+  # CPU Performance default values
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE)
+  gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_PCIE)
+  gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3)
+
+  #
+  # USB/DP Combo PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 }
+  gRK3588TokenSpaceGuid.PcdUsbDpPhy1Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x2, 0x3 }
+
+  #
+  # GMAC
+  #
+  gRK3588TokenSpaceGuid.PcdGmac0Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdGmac0TxDelay|0x47
+  gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x4f
+
+  #
+  # I2S
+  #
+  gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE
+
+  #
+  # On-Board fan output
+  #
+  gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform.
+#
+################################################################################
+[Components.common]
+  # ACPI Support
+  Platform/Firefly/AIO-3588Q/AcpiTables/AcpiTables.inf
+
+  # Device Tree Support
+  Platform/Firefly/AIO-3588Q/DeviceTree/Vendor.inf
+
+  # Splash screen logo
+  $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf
+
+  # Hack to enable use of PCA9555 during PCIe initialization.
+  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+    <LibraryClasses>
+      RockchipPlatformLib|Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLibPcaDepex.inf
+  }

edk2-rockchip/Platform/Firefly/AIO-3588Q/AcpiTables/AcpiTables.inf

@@ -0,0 +1,58 @@
+#/** @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2019-2021, ARM Limited. All rights reserved.
+#  Copyright (c) Microsoft Corporation. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+  RK_COMMON_ACPI_DIR             = Silicon/Rockchip/RK3588/AcpiTables
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+
+[Sources]
+  Dsdt.asl
+  $(RK_COMMON_ACPI_DIR)/Madt.aslc
+  $(RK_COMMON_ACPI_DIR)/Fadt.aslc
+  $(RK_COMMON_ACPI_DIR)/Gtdt.aslc
+  $(RK_COMMON_ACPI_DIR)/Spcr.aslc
+  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
+  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
+  $(RK_COMMON_ACPI_DIR)/Pptt.aslc
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Rockchip/RockchipPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gRK3588TokenSpaceGuid.PcdI2S0Supported
+  gRK3588TokenSpaceGuid.PcdI2S1Supported
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken

edk2-rockchip/Platform/Firefly/AIO-3588Q/AcpiTables/Dsdt.asl

@@ -0,0 +1,55 @@
+/** @file
+ *
+ *  Differentiated System Definition Table (DSDT)
+ *
+ *  Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ *  Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
+ *  Copyright (c) Microsoft Corporation. All rights reserved.
+ *  Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include "AcpiTables.h"
+
+#define BOARD_I2S0_TPLG "i2s-jack"
+
+#define BOARD_AUDIO_CODEC_HID "ESSX8388"
+#define BOARD_CODEC_I2C "\\_SB.I2C3"
+#define BOARD_CODEC_I2C_ADDR 0x11
+#define BOARD_CODEC_GPIO "\\_SB.GPI1"
+#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PC4
+
+DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588  ", 2)
+{
+  Scope (\_SB_)
+  {
+    include ("DsdtCommon.asl")
+
+    include ("Cpu.asl")
+
+    include ("Pcie.asl")
+    include ("Sata.asl")
+    include ("Emmc.asl")
+    include ("Sdhc.asl")
+    include ("Dma.asl")
+    include ("Gmac0.asl")
+    include ("Gmac1.asl")
+    include ("Gpio.asl")
+    include ("I2c.asl")
+    include ("Uart.asl")
+    // include ("Spi.asl")
+
+    include ("I2s.asl")
+
+    include ("Usb2Host.asl")
+    include ("Usb3Host0.asl")
+    include ("Usb3Host1.asl")
+    include ("Usb3Host2.asl")
+
+    Scope (I2C3) {
+      include ("Es8388.asl")
+    }
+  }
+}

edk2-rockchip/Platform/Firefly/AIO-3588Q/DeviceTree/Vendor.inf

@@ -0,0 +1,17 @@
+#/** @file
+#
+#  Copyright (c) 2024, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = DeviceTree-Vendor
+  FILE_GUID                      = d58b4028-43d8-4e97-87d4-4e3716136580
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+
+[Binaries]
+  BIN|devicetree/vendor/rk3588-firefly-aio-3588q.dtb

edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -0,0 +1,481 @@
+/** @file
+*
+*  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+*  Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Base.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/GpioLib.h>
+#include <Library/RK806.h>
+#include <Library/Rk3588Pcie.h>
+#include <Library/PWMLib.h>
+#include <Soc.h>
+#include <VarStoreData.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/Pca9555.h>
+
+static struct regulator_init_data rk806_init_data[] = {
+  /* Master PMIC */
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
+ // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+
+  /* No dual PMICs on this platform */
+};
+
+EFI_STATUS
+EFIAPI
+GetPca9555Protocol (
+  IN OUT PCA95XX_PROTOCOL        **Pca95xxProtocl
+  )
+{
+  EFI_HANDLE          *HandleBuffer;
+  EFI_STATUS           Status;
+  UINTN                HandleCount;
+
+  /* Locate Handles of all PCA95XX_PROTOCOL producers */
+  Status = gBS->LocateHandleBuffer (ByProtocol,
+                  &gPca95xxProtocolGuid,
+                  NULL,
+                  &HandleCount,
+                  &HandleBuffer);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "%a: Unable to locate handles\n", __FUNCTION__));
+    return Status;
+  }
+
+  DEBUG ((DEBUG_INFO,
+          "%a: got %d PCA95XX_PROTOCOLs\n",
+          __FUNCTION__,
+          HandleCount));
+
+  /*
+   * Open Pca95xxProtocl. With EFI_OPEN_PROTOCOL_GET_PROTOCOL attribute
+   * the consumer is not obliged to call CloseProtocol.
+   */
+  Status = gBS->OpenProtocol (HandleBuffer[0],
+                  &gPca95xxProtocolGuid,
+                  (VOID **)Pca95xxProtocl,
+                  HandleBuffer[0],
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+
+  return Status;
+}
+
+VOID
+EFIAPI
+SdmmcIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux (microSD socket) */
+  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+}
+
+VOID
+EFIAPI
+SdhciEmmcIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux */
+  /* Do not override, set by earlier boot stages. */
+}
+
+#define NS_CRU_BASE         0xFD7C0000
+#define CRU_CLKSEL_CON59    0x03EC
+#define CRU_CLKSEL_CON78    0x0438
+
+VOID
+EFIAPI
+Rk806SpiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
+  PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+}
+
+VOID
+EFIAPI
+Rk806Configure (
+  VOID
+  )
+{
+  UINTN RegCfgIndex;
+
+  RK806Init();
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
+    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+}
+
+VOID
+EFIAPI
+SetCPULittleVoltage (
+  IN UINT32 Microvolts
+  )
+{
+  struct regulator_init_data Rk806CpuLittleSupply =
+        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+
+  RK806RegulatorInit(Rk806CpuLittleSupply);
+}
+
+VOID
+EFIAPI
+NorFspiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  /* Do not override, set by earlier boot stages. */
+}
+
+VOID
+EFIAPI
+GmacIomux (
+  IN UINT32 Id
+  )
+{
+  switch (Id) {
+    case 0:
+      /* gmac0 iomux */
+      BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100; // GMAC0_RXD2, GMAC0_RXD3
+      BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111; // GMAC0_RXCLK, GMAC0_TXD2, GMAC0_TXD3, GMAC0_TXCLK
+      BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100; // GMAC0_TXD0, GMAC0_TXD1
+      BUS_IOC->GPIO2C_IOMUX_SEL_L = (0x0FFFUL << 16) | 0x0111; // GMAC0_TXEN, GMAC0_RXD0, GMAC0_RXD1
+      BUS_IOC->GPIO4C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100; // GMAC0_RXDV_CRS, GMAC0_MCLKINOUT
+      BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011; // GMAC0_MDC, GMAC0_MDIO
+
+      /* phy0 reset */
+      GpioPinSetDirection (3, GPIO_PIN_PC7, GPIO_PIN_OUTPUT);
+      break;
+    case 1:
+      /* gmac1 iomux */
+      BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111; /* GMAC1_MCLKINOUT, GMAC1_TXEN, GMAC1_TXD1 */
+      BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111; /* GMAC1_RXD3, GMAC1_RXD2, GMAC1_TXD3, GMAC1_TXD2 */
+      BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; /* GMAC1_TXD0, GMAC1_RXDV_CRS, GMAC1_RXD1 */
+      BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011; /* GMAC1_RXD0, GMAC1_RXCLK, GMAC1_TXCLK */
+      BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100; /* GMAC1_MDIO, GMAC1_MDC */
+
+      /* phy1 reset */
+      GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+GmacIoPhyReset (
+  UINT32   Id,
+  BOOLEAN  Enable
+  )
+{
+  switch (Id) {
+    case 0:
+      /* phy0 reset */
+      GpioPinWrite (3, GPIO_PIN_PC7, !Enable);
+      break;
+    case 1:
+      /* phy1 reset */
+      GpioPinWrite (3, GPIO_PIN_PB7, !Enable);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+NorFspiEnableClock (
+  UINT32 *CruBase
+  )
+{
+  UINTN BaseAddr = (UINTN) CruBase;
+
+  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+}
+
+VOID
+EFIAPI
+I2cIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); // I2C0_SCL_M2
+    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); // I2C0_SDA_M2
+    break;
+  case 1:
+    GpioPinSetFunction(0, GPIO_PIN_PD4, 9); // I2C1_SCL_M2
+    GpioPinSetFunction(0, GPIO_PIN_PD5, 9); // I2C1_SDA_M2
+    break;
+  case 3:
+    GpioPinSetFunction(1, GPIO_PIN_PC1, 9); // I2C3_SCL_M0
+    GpioPinSetFunction(1, GPIO_PIN_PC0, 9); // I2C3_SDA_M0
+    break;
+  case 6:
+    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); // I2C6_SCL_M0
+    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); // I2C6_SDA_M0
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+UsbPortPowerEnable (
+  VOID
+  )
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+  PCA95XX_PROTOCOL *Pca95xxProtocol;
+
+  /* On Firefly AIO-3588Q this is controlled via the PCA9555. */
+  Status = GetPca9555Protocol(&Pca95xxProtocol);
+  if (EFI_ERROR(Status)) {
+    DEBUG ((DEBUG_ERROR, "UsbPortPowerEnable failed to get PCA9555! (%d)\n", Status));
+  } else {
+    /* USB-C */
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      12, /* vbus5v0_typec_pwr_en */
+      GPIO_MODE_OUTPUT_0
+    );
+
+    gBS->Stall(1200000);
+
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      12, /* vbus5v0_typec_pwr_en */
+      GPIO_MODE_OUTPUT_1
+    );
+
+    /* other USB stuff */
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      5, /* vcc5v0_host */
+      GPIO_MODE_OUTPUT_1
+    );
+
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      4, /* vcc_hub_reset */
+      GPIO_MODE_OUTPUT_1
+    );
+
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      6, /* vcc_hub3_reset */
+      GPIO_MODE_OUTPUT_1
+    );
+
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      7, /* vcc5v0_host3 */
+      GPIO_MODE_OUTPUT_1
+    );
+  }
+}
+
+VOID
+EFIAPI
+Usb2PhyResume (
+  VOID
+  )
+{
+  MmioWrite32(0xfd5d0008, 0x20000000);
+  MmioWrite32(0xfd5d4008, 0x20000000);
+  MmioWrite32(0xfd5d8008, 0x20000000);
+  MmioWrite32(0xfd5dc008, 0x20000000);
+  MmioWrite32(0xfd7f0a10, 0x07000700);
+  MmioWrite32(0xfd7f0a10, 0x07000000);
+}
+
+VOID
+EFIAPI
+PcieIoInit (
+  UINT32 Segment
+  )
+{
+  switch (Segment) {
+  case PCIE_SEGMENT_PCIE30X4:
+    GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT); // PCIE30X4_PERSTN_M1
+    GpioPinSetDirection (4, GPIO_PIN_PC6, GPIO_PIN_OUTPUT); // vcc3v3_pcie30
+    break;
+  case PCIE_SEGMENT_PCIE20L0:
+    GpioPinSetDirection (1, GPIO_PIN_PB4, GPIO_PIN_OUTPUT);
+    break;
+  case PCIE_SEGMENT_PCIE20L1:
+    break;
+  case PCIE_SEGMENT_PCIE20L2:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+PciePowerEn (
+  UINT32 Segment,
+  BOOLEAN Enable
+  )
+{
+  switch (Segment) {
+  case PCIE_SEGMENT_PCIE30X4:
+    GpioPinWrite (4, GPIO_PIN_PC6, Enable); // vcc3v3_pcie30
+    break;
+  case PCIE_SEGMENT_PCIE20L0:
+    break;
+  case PCIE_SEGMENT_PCIE20L1:
+    break;
+  case PCIE_SEGMENT_PCIE20L2:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+PciePeReset (
+  UINT32 Segment,
+  BOOLEAN Enable
+  )
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+  PCA95XX_PROTOCOL *Pca95xxProtocol;
+
+  switch (Segment) {
+  case PCIE_SEGMENT_PCIE30X4:
+    GpioPinWrite (4, GPIO_PIN_PB6, !Enable); // PCIE30X4_PERSTN_M1
+    break;
+  case PCIE_SEGMENT_PCIE20L0:
+    GpioPinWrite (1, GPIO_PIN_PB4, !Enable);
+    break;
+  case PCIE_SEGMENT_PCIE20L1:
+    break;
+  case PCIE_SEGMENT_PCIE20L2:
+    Status = GetPca9555Protocol(&Pca95xxProtocol);
+    if (EFI_ERROR(Status)) {
+      DEBUG ((DEBUG_ERROR, "PciePeReset(L2) failed to get PCA9555! (%d)\n", Status));
+    } else {
+      Pca95xxProtocol->GpioProtocol.Set(
+        &Pca95xxProtocol->GpioProtocol,
+        14, /* PCA_IO1_6 */
+        Enable ? GPIO_MODE_OUTPUT_0 : GPIO_MODE_OUTPUT_1
+      );
+    }
+    break;
+  }
+}
+
+PWM_DATA pwm_data = {
+  .ControllerID = PWM_CONTROLLER3,
+  .ChannelID = PWM_CHANNEL3,
+  .PeriodNs = 50000,
+  .DutyNs = 50000,
+  .Polarity = FALSE,
+}; // PWM15
+
+VOID
+EFIAPI
+PwmFanIoSetup (
+  VOID
+  )
+{
+  GpioPinSetFunction (1, GPIO_PIN_PC6, 0xB); // PWM15_IR_M2
+  RkPwmSetConfig (&pwm_data);
+  RkPwmEnable (&pwm_data);
+}
+
+VOID
+EFIAPI
+PwmFanSetSpeed (
+  IN UINT32 Percentage
+  )
+{
+  pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100;
+  RkPwmSetConfig (&pwm_data);
+}
+
+VOID
+EFIAPI
+PlatformInitLeds (
+  VOID
+  )
+{
+  GpioPinWrite (3, GPIO_PIN_PB2, FALSE);
+  GpioPinSetDirection (3, GPIO_PIN_PB2, GPIO_PIN_OUTPUT);
+}
+
+VOID
+EFIAPI
+PlatformSetStatusLed (
+  IN BOOLEAN Enable
+  )
+{
+  GpioPinWrite (3, GPIO_PIN_PB2, Enable);
+}
+
+CONST EFI_GUID *
+EFIAPI
+PlatformGetDtbFileGuid (
+  IN UINT32 CompatMode
+  )
+{
+  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+    0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
+  };
+
+  switch (CompatMode) {
+    case FDT_COMPAT_MODE_VENDOR:
+      return &VendorDtbFileGuid;
+  }
+
+  return NULL;
+}
+
+VOID
+EFIAPI
+PlatformEarlyInit (
+  VOID
+  )
+{
+  GpioPinSetDirection (4, GPIO_PIN_PB0, GPIO_PIN_OUTPUT); // headphone enable
+  GpioPinWrite (4, GPIO_PIN_PB0, TRUE);
+  GpioPinSetFunction (1, GPIO_PIN_PC4, 0); // headphone detect
+}

edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.inf

@@ -0,0 +1,39 @@
+#/** @file
+#
+#  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#  Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = RockchipPlatformLib
+  FILE_GUID                      = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RockchipPlatformLib
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  SerialPortLib
+  CruLib
+  GpioLib
+  PWMLib
+
+[Protocols]
+  gPca95xxProtocolGuid
+
+[Sources.common]
+  RockchipPlatformLib.c

edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLibPcaDepex.inf

@@ -0,0 +1,43 @@
+#/** @file
+#
+#  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#  Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = RockchipPlatformLib
+  FILE_GUID                      = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RockchipPlatformLib
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  SerialPortLib
+  CruLib
+  GpioLib
+  PWMLib
+
+[Protocols]
+  gPca95xxProtocolGuid
+
+[Sources.common]
+  RockchipPlatformLib.c
+
+# Hack to enable use of PCA9555 during PCIe initialization.
+[Depex]
+  gPca95xxProtocolGuid

edk2-rockchip/Platform/Firefly/ITX-3588J/AcpiTables/AcpiTables.inf

@@ -0,0 +1,58 @@
+#/** @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2019-2021, ARM Limited. All rights reserved.
+#  Copyright (c) Microsoft Corporation. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+  RK_COMMON_ACPI_DIR             = Silicon/Rockchip/RK3588/AcpiTables
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+
+[Sources]
+  Dsdt.asl
+  $(RK_COMMON_ACPI_DIR)/Madt.aslc
+  $(RK_COMMON_ACPI_DIR)/Fadt.aslc
+  $(RK_COMMON_ACPI_DIR)/Gtdt.aslc
+  $(RK_COMMON_ACPI_DIR)/Spcr.aslc
+  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
+  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
+  $(RK_COMMON_ACPI_DIR)/Pptt.aslc
+  
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Rockchip/RockchipPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gRK3588TokenSpaceGuid.PcdI2S0Supported
+  gRK3588TokenSpaceGuid.PcdI2S1Supported
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken

edk2-rockchip/Platform/Firefly/ITX-3588J/AcpiTables/Dsdt.asl

@@ -0,0 +1,41 @@
+/** @file
+ *
+ *  Differentiated System Definition Table (DSDT)
+ *
+ *  Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ *  Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
+ *  Copyright (c) Microsoft Corporation. All rights reserved.
+ *  Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include "AcpiTables.h"
+
+DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588  ", 2)
+{
+  Scope (\_SB_)
+  {
+    include ("DsdtCommon.asl")
+
+    include ("Cpu.asl")
+
+    include ("Pcie.asl")
+    include ("Sata.asl")
+    include ("Emmc.asl")
+    include ("Sdhc.asl")
+    include ("Dma.asl")
+    include ("Gmac0.asl")
+    include ("Gmac1.asl")
+    include ("Gpio.asl")
+    include ("I2c.asl")
+    include ("Uart.asl")
+    // include ("Spi.asl")
+
+    include ("Usb2Host.asl")
+    include ("Usb3Host0.asl")
+    include ("Usb3Host1.asl")
+    include ("Usb3Host2.asl")
+  }
+}

edk2-rockchip/Platform/Firefly/ITX-3588J/DeviceTree/Vendor.inf

@@ -0,0 +1,17 @@
+#/** @file
+#
+#  Copyright (c) 2024, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = DeviceTree-Vendor
+  FILE_GUID                      = d58b4028-43d8-4e97-87d4-4e3716136580
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+
+[Binaries]
+  BIN|devicetree/vendor/itx-3588j.dtb

edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.Modules.fdf.inc

@@ -0,0 +1,17 @@
+## @file
+#
+#  Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
+#  Copyright (c) 2023, Shimrra Shai <shimmyshai00@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+  # ACPI Support
+  INF RuleOverride = ACPITABLE Platform/Firefly/ITX-3588J/AcpiTables/AcpiTables.inf
+
+  # Device Tree Support
+  INF RuleOverride = DTB Platform/Firefly/ITX-3588J/DeviceTree/Vendor.inf
+
+  # Splash screen logo
+  INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf

edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.dsc

@@ -0,0 +1,34 @@
+## @file
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+#  Copyright (c) 2023, Shimrra Shai <shimmyshai00@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = ITX-3588J
+  PLATFORM_VENDOR                = Firefly
+  PLATFORM_GUID                  = db88a604-ec99-4d39-84d4-af4fa5b5e757
+  PLATFORM_VERSION               = 0.2
+  DSC_SPECIFICATION              = 0x00010019
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  VENDOR_DIRECTORY               = Platform/$(PLATFORM_VENDOR)
+  PLATFORM_DIRECTORY             = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+
+  #
+  # Platform based on ITX-3588J board
+  #
+!include Platform/Firefly/ITX-3588J/ITX-3588J.dsc.inc
+
+  

edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.dsc.inc

@@ -0,0 +1,122 @@
+## @file
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
+#  Copyright (c) 2023, Shimrra Shai <shimmyshai00@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  FLASH_DEFINITION               = Silicon/Rockchip/RK3588/RK3588.fdf
+  RK_PLATFORM_FVMAIN_MODULES     = Platform/Firefly/ITX-3588J/ITX-3588J.Modules.fdf.inc
+
+  #
+  # HYM8563 RTC support
+  # I2C location configured by PCDs below.
+  #
+  DEFINE RK_RTC8563_ENABLE = TRUE
+
+  #
+  # PCA9555 GPIO extender support
+  # I2C location configured by PCDs below.
+  #
+  DEFINE RK_PCA9555_ENABLE = TRUE
+
+  #
+  # RK3588-based platform
+  #
+!include Silicon/Rockchip/RK3588/RK3588Platform.dsc.inc
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+
+[LibraryClasses.common]
+  RockchipPlatformLib|Platform/Firefly/ITX-3588J/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform.
+#
+################################################################################
+
+[PcdsFixedAtBuild.common]
+  # SMBIOS platform config
+  gRockchipTokenSpaceGuid.PcdPlatformName|"ITX-3588J"
+  gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Firefly"
+  gRockchipTokenSpaceGuid.PcdFamilyName|"ITX"
+  gRockchipTokenSpaceGuid.PcdProductUrl|"https://en.t-firefly.com/product/industry/itx3588j"
+  gRockchipTokenSpaceGuid.PcdDeviceTreeName|"itx-3588j"
+
+  # I2C
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51, 0x21, 0x22 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6, 0x6, 0x6 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE, FALSE, FALSE }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) }
+  gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
+  gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6
+  gRockchipTokenSpaceGuid.PcdPca9555Address|0x21
+  gRockchipTokenSpaceGuid.PcdPca9555Bus|0x6
+
+  #
+  # CPU Performance default values
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_SATA)
+  gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_PCIE)
+  gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3)
+
+  #
+  # USB/DP Combo PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdUsbDpPhy1Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x2, 0x3 }
+
+  #
+  # GMAC
+  #
+  gRK3588TokenSpaceGuid.PcdGmac0Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdGmac0TxDelay|0x45
+  gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x42
+
+  #
+  # On-Board fan output
+  #
+  gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform.
+#
+################################################################################
+[Components.common]
+  # ACPI Support
+  Platform/Firefly/ITX-3588J/AcpiTables/AcpiTables.inf
+
+  # Device Tree Support
+  Platform/Firefly/ITX-3588J/DeviceTree/Vendor.inf
+
+  # Splash screen logo
+  $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf

edk2-rockchip/Platform/Firefly/ITX-3588J/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -0,0 +1,532 @@
+/** @file
+*
+*  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+*  Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Base.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/GpioLib.h>
+#include <Library/RK806.h>
+#include <Library/Rk3588Pcie.h>
+#include <Library/PWMLib.h>
+#include <Soc.h>
+#include <VarStoreData.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/Pca9555.h>
+
+static struct regulator_init_data rk806_init_data[] = {
+  /* Master PMIC */
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
+ // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+
+  /* No dual PMICs on this platform */
+};
+
+EFI_STATUS
+EFIAPI
+GetPca9555Protocol (
+  IN OUT PCA95XX_PROTOCOL        **Pca95xxProtocl
+  )
+{
+  EFI_HANDLE          *HandleBuffer;
+  EFI_STATUS           Status;
+  UINTN                HandleCount;
+  UINTN                Index;
+
+  /* Locate Handles of all PCA95XX_PROTOCOL producers */
+  Status = gBS->LocateHandleBuffer (ByProtocol,
+                  &gPca95xxProtocolGuid,
+                  NULL,
+                  &HandleCount,
+                  &HandleBuffer);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "%a: Unable to locate handles\n", __FUNCTION__));
+    return Status;
+  }
+
+  DEBUG ((DEBUG_INFO,
+          "%a: got %d PCA95XX_PROTOCOLs\n",
+          __FUNCTION__,
+          HandleCount));
+
+  /*
+   * Open Pca95xxProtocl. With EFI_OPEN_PROTOCOL_GET_PROTOCOL attribute
+   * the consumer is not obliged to call CloseProtocol.
+   */
+  Status = gBS->OpenProtocol (HandleBuffer[0],
+                  &gPca95xxProtocolGuid,
+                  (VOID **)Pca95xxProtocl,
+                  HandleBuffer[0],
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+
+  return Status;
+}
+
+VOID
+EFIAPI
+SdmmcIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux (microSD socket) */
+  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+}
+
+VOID
+EFIAPI
+SdhciEmmcIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux */
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+}
+
+#define NS_CRU_BASE         0xFD7C0000
+#define CRU_CLKSEL_CON59    0x03EC
+#define CRU_CLKSEL_CON78    0x0438
+
+VOID
+EFIAPI
+Rk806SpiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
+  PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+}
+
+VOID
+EFIAPI
+Rk806Configure (
+  VOID
+  )
+{
+  UINTN RegCfgIndex;
+
+  RK806Init();
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
+    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+}
+
+VOID
+EFIAPI
+SetCPULittleVoltage (
+  IN UINT32 Microvolts
+  )
+{
+  struct regulator_init_data Rk806CpuLittleSupply =
+        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+
+  RK806RegulatorInit(Rk806CpuLittleSupply);
+}
+
+VOID
+EFIAPI
+NorFspiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
+             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
+#define FSPI_M1
+#if defined(FSPI_M0)
+   /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
+#elif defined(FSPI_M1)
+  /*FSPI M1*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
+#else
+  /*FSPI M2*/
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
+#endif
+}
+
+VOID
+EFIAPI
+GmacIomux (
+  IN UINT32 Id
+  )
+{
+  switch (Id) {
+    case 0:
+      /* gmac0 iomux */
+      BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+      BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+      BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+      BUS_IOC->GPIO2C_IOMUX_SEL_L = (0x0FFFUL << 16) | 0x0111;
+      BUS_IOC->GPIO4C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100;
+      BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011;
+
+      /* phy0 reset */
+      GpioPinSetDirection (3, GPIO_PIN_PC7, GPIO_PIN_OUTPUT);
+      break;
+    case 1:
+      /* gmac1 iomux */
+      BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111; /* GMAC1_MCLKINOUT, GMAC1_TXEN, GMAC1_TXD1 */
+      BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111; /* GMAC1_RXD3, GMAC1_RXD2, GMAC1_TXD3, GMAC1_TXD2 */
+      BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; /* GMAC1_TXD0, GMAC1_RXDV_CRS, GMAC1_RXD1 */
+      BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011; /* GMAC1_RXD0, GMAC1_RXCLK, GMAC1_TXCLK */
+      BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100; /* GMAC1_MDIO, GMAC1_MDC */
+
+      /* phy1 reset */
+      GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+GmacIoPhyReset (
+  UINT32   Id,
+  BOOLEAN  Enable
+  )
+{
+  switch (Id) {
+    case 0:
+      /* phy0 reset */
+      GpioPinWrite (3, GPIO_PIN_PC7, !Enable);
+      break;
+    case 1:
+      /* phy1 reset */
+      GpioPinWrite (3, GPIO_PIN_PB7, !Enable);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+NorFspiEnableClock (
+  UINT32 *CruBase
+  )
+{
+  UINTN BaseAddr = (UINTN) CruBase;
+
+  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+}
+
+VOID
+EFIAPI
+I2cIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    /* io mux M2 */
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
+    break;
+  case 1:
+    /* io mux */
+    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
+    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
+    break;
+  case 2:
+    /* io mux */
+    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
+    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
+    PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
+    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    break;
+  case 3:
+    break;
+  case 4:
+    break;
+  case 5:
+    break;
+  case 6:
+    /* io mux M0 */
+    BUS_IOC->GPIO0C_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
+    BUS_IOC->GPIO0D_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
+    PMU2_IOC->GPIO0C_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+UsbPortPowerEnable (
+  VOID
+  )
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+  PCA95XX_PROTOCOL *Pca95xxProtocol;
+
+  /* On Firefly ITX-3588J this is controlled via the PCA9555. */
+  Status = GetPca9555Protocol(&Pca95xxProtocol);
+  if (EFI_ERROR(Status)) {
+    DEBUG ((DEBUG_ERROR, "Failed to get PCA9555! (%d)\n", Status));
+  } else {
+    /* USB-C */
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      12, /* vbus5v0_typec_pwr_en */
+      GPIO_MODE_OUTPUT_0
+    );
+
+    gBS->Stall(1200000);
+
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      12, /* vbus5v0_typec_pwr_en */
+      GPIO_MODE_OUTPUT_1
+    );
+
+    /* other USB stuff */
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      5, /* vcc5v0_host */
+      GPIO_MODE_OUTPUT_1
+    );
+
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      4, /* vcc_hub_reset */
+      GPIO_MODE_OUTPUT_1
+    );
+
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      6, /* vcc_hub3_reset */
+      GPIO_MODE_OUTPUT_1
+    );
+
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      7, /* vcc5v0_host3 */
+      GPIO_MODE_OUTPUT_1
+    );
+  }
+}
+
+VOID
+EFIAPI
+Usb2PhyResume (
+  VOID
+  )
+{
+  MmioWrite32(0xfd5d0008, 0x20000000);
+  MmioWrite32(0xfd5d4008, 0x20000000);
+  MmioWrite32(0xfd5d8008, 0x20000000);
+  MmioWrite32(0xfd5dc008, 0x20000000);
+  MmioWrite32(0xfd7f0a10, 0x07000700);
+  MmioWrite32(0xfd7f0a10, 0x07000000);
+}
+
+VOID
+EFIAPI
+PcieIoInit (
+  UINT32 Segment
+  )
+{
+  /* Set reset and power IO to gpio output mode */
+  if(Segment == PCIE_SEGMENT_PCIE30X4) {
+    /* reset */
+    GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
+    /* vcc3v3_pcie30 */
+    GpioPinSetDirection (2, GPIO_PIN_PC5, GPIO_PIN_OUTPUT);
+  }
+}
+
+VOID
+EFIAPI
+PciePowerEn (
+  UINT32 Segment,
+  BOOLEAN Enable
+  )
+{
+  if(Segment == PCIE_SEGMENT_PCIE30X4) {
+    /* vcc3v3_pcie30 */
+    GpioPinWrite (2, GPIO_PIN_PC5, Enable);
+  }
+}
+
+VOID
+EFIAPI
+PciePeReset (
+  UINT32 Segment,
+  BOOLEAN Enable
+  )
+{
+  if(Segment == PCIE_SEGMENT_PCIE30X4) {
+    GpioPinWrite (4, GPIO_PIN_PB6, !Enable);
+  }
+}
+
+PWM_DATA pwm_data = {
+  .ControllerID = PWM_CONTROLLER2,
+  .ChannelID = PWM_CHANNEL3,
+  .PeriodNs = 50000,
+  .DutyNs = 50000,
+  .Polarity = TRUE,
+}; // PWM2_CH3
+
+VOID
+EFIAPI
+PwmFanIoSetup (
+  VOID
+  )
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+  PCA95XX_PROTOCOL *Pca95xxProtocol;
+
+  Status = GetPca9555Protocol(&Pca95xxProtocol);
+  if (EFI_ERROR(Status)) {
+    DEBUG ((DEBUG_ERROR, "Failed to get PCA9555! (%d)\n", Status));
+  } else {
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      11, /* vcc_fan_pwr_en */
+      GPIO_MODE_OUTPUT_1
+    );
+  }
+}
+
+VOID
+EFIAPI
+PwmFanSetSpeed (
+  IN UINT32 Percentage
+  )
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+  PCA95XX_PROTOCOL *Pca95xxProtocol;
+
+  Status = GetPca9555Protocol(&Pca95xxProtocol);
+  if (EFI_ERROR(Status)) {
+    DEBUG ((DEBUG_ERROR, "Failed to get PCA9555! (%d)\n", Status));
+  } else {
+    /* (SS) NB: (TBA?) It doesn't *appear* we can regulate the fan speed,
+     *      only power up/down, but I could be wrong
+     */
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      11, /* vcc_fan_pwr_en */
+      (Percentage > 0) ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTPUT_0
+    );
+  }
+}
+
+VOID
+EFIAPI
+PlatformInitLeds (
+  VOID
+  )
+{
+  /* Activate power LED only */
+  GpioPinWrite (1, GPIO_PIN_PB3, TRUE);
+  GpioPinSetDirection (1, GPIO_PIN_PB3, GPIO_PIN_OUTPUT);
+
+#if 0
+  /* Red off, Green for status, Blue for power */
+  GpioPinWrite (3, GPIO_PIN_PB2, FALSE);
+  GpioPinSetDirection (3, GPIO_PIN_PB2, GPIO_PIN_OUTPUT);
+  GpioPinWrite (3, GPIO_PIN_PC0, FALSE);
+  GpioPinSetDirection (3, GPIO_PIN_PC0, GPIO_PIN_OUTPUT);
+  GpioPinWrite (1, GPIO_PIN_PD5, TRUE);
+  GpioPinSetDirection (1, GPIO_PIN_PD5, GPIO_PIN_OUTPUT);
+#endif
+}
+
+VOID
+EFIAPI
+PlatformSetStatusLed (
+  IN BOOLEAN Enable
+  )
+{
+  /* (SS) does not seem to work and causes errors on I2C complaining
+   * about something being too high
+   */
+#if 0
+  EFI_STATUS Status = EFI_SUCCESS;
+  PCA95XX_PROTOCOL *Pca95xxProtocol;
+
+  /* On Firefly ITX-3588J this is controlled via the PCA9555. */
+  Status = GetPca9555Protocol(&Pca95xxProtocol);
+  if (EFI_ERROR(Status)) {
+    DEBUG ((DEBUG_ERROR, "Failed to get PCA9555! (%d)\n", Status));
+  } else {
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      3, /* user_led */
+      Enable ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTPUT_0
+    );
+  }
+#endif
+}
+
+CONST EFI_GUID *
+EFIAPI
+PlatformGetDtbFileGuid (
+  IN UINT32 CompatMode
+  )
+{
+  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+    0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
+  };
+
+  switch (CompatMode) {
+    case FDT_COMPAT_MODE_VENDOR:
+      return &VendorDtbFileGuid;
+  }
+
+  return NULL;
+}
+
+VOID
+EFIAPI
+PlatformEarlyInit (
+  VOID
+  )
+{
+
+}

edk2-rockchip/Platform/Firefly/ITX-3588J/Library/RockchipPlatformLib/RockchipPlatformLib.inf

@@ -0,0 +1,39 @@
+#/** @file
+#
+#  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#  Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = RockchipPlatformLib
+  FILE_GUID                      = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RockchipPlatformLib
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  SerialPortLib
+  CruLib
+  GpioLib
+  PWMLib
+
+[Protocols]
+  gPca95xxProtocolGuid
+
+[Sources.common]
+  RockchipPlatformLib.c

edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/AcpiTables.inf

@@ -32,15 +32,6 @@
   $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
   $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
   $(RK_COMMON_ACPI_DIR)/Pptt.aslc
-  $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl
-  $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl
-  $(RK_COMMON_ACPI_DIR)/Sata0.asl
-  $(RK_COMMON_ACPI_DIR)/Sata1.asl
-  $(RK_COMMON_ACPI_DIR)/Sata2.asl
-  $(RK_COMMON_ACPI_DIR)/Usb2Host.asl
 
 [Packages]
   ArmPkg/ArmPkg.dec
@@ -49,6 +40,7 @@
   MdeModulePkg/MdeModulePkg.dec
   MdePkg/MdePkg.dec
   Silicon/Rockchip/RockchipPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
 
 [FixedPcd]
   gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
@@ -59,3 +51,8 @@
   gArmTokenSpaceGuid.PcdGicDistributorBase
   gArmTokenSpaceGuid.PcdGicRedistributorsBase
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gRK3588TokenSpaceGuid.PcdI2S0Supported
+  gRK3588TokenSpaceGuid.PcdI2S1Supported
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken

edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/Dsdt.asl

@@ -13,22 +13,41 @@
 
 #include "AcpiTables.h"
 
+#define BOARD_I2S0_TPLG "i2s-jack"
+
+#define BOARD_AUDIO_CODEC_HID "ESSX8388"
+#define BOARD_CODEC_I2C "\\_SB.I2C3"
+#define BOARD_CODEC_I2C_ADDR 0x11
+#define BOARD_CODEC_GPIO "\\_SB.GPI1"
+#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PA6
+
 DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588  ", 2)
 {
   Scope (\_SB_)
   {
+    include ("DsdtCommon.asl")
+
     include ("Cpu.asl")
 
+    include ("Pcie.asl")
+    include ("Sata.asl")
     include ("Emmc.asl")
     include ("Sdhc.asl")
+    include ("Dma.asl")
     include ("Gmac1.asl")
-    // include ("Gpio.asl")
-    // include ("I2c.asl")
+    include ("Gpio.asl")
+    include ("I2c.asl")
     include ("Uart.asl")
     // include ("Spi.asl")
 
-    include ("Usb1Host.asl")
+    include ("I2s.asl")
+
+    include ("Usb2Host.asl")
     include ("Usb3Host0.asl")
     include ("Usb3Host2.asl")
+
+    Scope (I2C3) {
+      include ("Es8388.asl")
+    }
   }
 }

edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/DeviceTree/Vendor.inf

@@ -0,0 +1,17 @@
+#/** @file
+#
+#  Copyright (c) 2024, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = DeviceTree-Vendor
+  FILE_GUID                      = d58b4028-43d8-4e97-87d4-4e3716136580
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+
+[Binaries]
+  BIN|devicetree/vendor/roc-rk3588s-pc.dtb

edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -1,10 +1,12 @@
 /** @file
 *
 *  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+*  Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
 *
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
 *
 **/
+
 #include <Base.h>
 #include <Library/DebugLib.h>
 #include <Library/IoLib.h>
@@ -13,6 +15,7 @@
 #include <Library/Rk3588Pcie.h>
 #include <Library/PWMLib.h>
 #include <Soc.h>
+#include <VarStoreData.h>
 #include <Library/UefiBootServicesTableLib.h>
 
 static struct regulator_init_data rk806_init_data[] = {
@@ -197,28 +200,33 @@ I2cIomux (
 {
   switch (id) {
   case 0:
-    /* io mux M2 */
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
-    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
+    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
+    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
     break;
   case 1:
-    /* io mux */
-    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
-    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
     break;
   case 2:
-    /* io mux */
-    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
-    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
-    PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
-    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
     break;
   case 3:
+    GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0
+    GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0
     break;
   case 4:
+    GpioPinSetFunction(1, GPIO_PIN_PA3, 9); //i2c4_scl_m3
+    GpioPinSetFunction(1, GPIO_PIN_PA2, 9); //i2c4_sda_m3
     break;
   case 5:
     break;
+  case 6:
+    GpioPinSetFunction(4, GPIO_PIN_PB1, 9); //i2c6_scl_m3
+    GpioPinSetFunction(4, GPIO_PIN_PB0, 9); //i2c6_sda_m3
+    break;
+  case 7:
+    GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0
+    GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0
+    break;
   default:
     break;
   }
@@ -353,11 +361,29 @@ PlatformSetStatusLed (
   GpioPinWrite (3, GPIO_PIN_PC0, Enable);
 }
 
+CONST EFI_GUID *
+EFIAPI
+PlatformGetDtbFileGuid (
+  IN UINT32 CompatMode
+  )
+{
+  STATIC CONST EFI_GUID VendorDtbFileGuid = {         // DeviceTree/Vendor.inf
+    0xd58b4028, 0x43d8, 0x4e97, { 0x87, 0xd4, 0x4e, 0x37, 0x16, 0x13, 0x65, 0x80 }
+  };
+
+  switch (CompatMode) {
+    case FDT_COMPAT_MODE_VENDOR:
+      return &VendorDtbFileGuid;
+  }
+
+  return NULL;
+}
+
 VOID
 EFIAPI
 PlatformEarlyInit (
   VOID
   )
 {
-
+  GpioPinSetFunction(1, GPIO_PIN_PA6, 0); //jdet
 }