6a4d27706a
x86: fix the pause instruction reported by @maijin in issue #298
2015-04-02 12:32:33 +08:00
d505d6d461
x86: initialize cs_x86.{xop_cc, eflags}
2015-04-01 01:30:34 +08:00
87d754dc3a
Merge branch 'next' of https://github.com/aquynh/capstone into next
2015-03-30 08:25:20 +08:00
228ec96de5
x86: LEA instruction should not access the second operand. bug reported by @chaplja
2015-03-30 08:24:12 +08:00
19ee2d10b3
inttypes.h fix
2015-03-29 21:16:38 +08:00
efffe787d1
Add new API and start to provide access information for instruction operands
...
- New API cs_regs_access() that provide registers being read & modified by instruction
- New field cs_x86_op.access provides access info (READ, WRITE) for each operand
- New field cs_x86.eflags provides EFLAGS affected by instruction
- Extend cs_detail.{regs_read, regs_write} from uint8_t to uint16_t type
2015-03-25 15:02:13 +08:00
75e94a06c9
arm: fix some instructions in insn_ops[] where GPRwithAPSR & addr_offset_non should be considered for register access. issue reported by @derrekr
2015-03-23 00:56:03 +08:00
5e5b1f5366
core: rename operand access symbols from CS_OP_* to CS_AC_*
2015-03-23 00:09:20 +08:00
6a77cc7463
arm: some fixes for insn_ops[] where some registers should be considered for accessing. issue reported by @derrek
2015-03-22 23:24:30 +08:00
c79a8a03c4
arm: fix lots of issues with insn_op[], and move it to a separate file ARMMappingInsnOp.inc
2015-03-22 13:39:54 +08:00
5b93f59afe
x86: more fix for lots of OP_NOREG in insn_ops[]. also renamed it to OP_IGNORE
2015-03-21 01:35:14 +08:00
1271684973
x86: print interrupt number of INT instruction in positive form. bug reported by @pancake
2015-03-20 22:36:08 +08:00
8bb1f04bb8
x86: fix lots of issues with insn_op[], and move it to a separate file X86MappingInsnOp.inc
2015-03-20 17:18:01 +08:00
f97067924c
arm64: use symbol rather than constant (128) for calculating group name in AArch64_group_name()
2015-03-16 11:49:33 +07:00
a6fb47bdf0
Merge branch 'AArch64Details' of https://github.com/DavidCallahan/capstone into test3
2015-03-16 11:43:50 +07:00
9092e5295f
Change AArch64 GRP_JUMP to use a static table implementation
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Added support for GRP_CALL and GRP_RETURN to AArch64
2015-03-15 18:01:48 -07:00
2c1b7f1398
x86: fix Immediate operand size when first register operand is embedded in mnemonic (CMP8i8). bug reported by @joelpx
2015-03-14 10:17:17 +08:00
21bf9cee90
Merge branch 'next' of https://github.com/aquynh/capstone into next
2015-03-12 18:17:24 +08:00
681070ccf4
Merge pull request #279 from radare/arm64-priv
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add ARM64_GRP_PRIVILEGE group and tag some instructions
2015-03-12 17:42:14 +08:00
ba7bf10dbb
Merge pull request #278 from radare/arm-priv
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add ARM_GRP_PRIVILEGE group and tag some instructions
2015-03-12 17:41:52 +08:00
b8ffb86b02
ppc: fix a bug in QPX mode & add some QPX alias instructions.
2015-03-12 16:52:31 +08:00
0cc0543486
ppc: add missing groups to group_name_maps[]. bug reported by Coverity
2015-03-12 00:30:44 +08:00
e17124356e
arm: add the missing Virtualization group to group_name_maps[]. bug reported by Coverity
2015-03-12 00:26:08 +08:00
09218a2dfd
x86: remove unsed field @prefixLocations of InternalInstruction struct
2015-03-11 11:29:33 +08:00
bcb75a2194
x86: F2 can be a part of instruction encoding, but not a prefix
2015-03-11 11:15:27 +08:00
8c212fd25e
ppc: add the missing Q0 register to reg_name_maps[]. bug reported by Coverity
2015-03-11 10:29:08 +08:00
fcde1e190a
Merge branch 'next' of https://github.com/aquynh/capstone into next
2015-03-11 10:28:49 +08:00
21b0bdd0e1
Fix indent issue
2015-03-11 00:40:14 +01:00
dae7c3ee9f
add ARM64_GRP_PRIVILEGE group and tag some instructions
2015-03-11 00:23:22 +01:00
cf74a14b43
add ARM_GRP_PRIVILEGE group and tag some instructions
2015-03-11 00:13:53 +01:00
6791b268c4
arm: revert the last change on OperandInfo* in ARMGenInstrInfo.inc
2015-03-10 16:52:22 +08:00
dfd1c0b44e
arm: get rid of some useless variables in ARMGenInstrInfo.inc. this saves at lease 50KB
2015-03-10 15:21:22 +08:00
a7837a4ae3
sparc, systemz, xcore: getInstruction() should return boolean instead of DecodeStatus
2015-03-10 15:20:20 +08:00
037e01f942
core: remove unused Subregister indices for Sparc, PPC, SystemZ & Mips
2015-03-09 21:36:02 +08:00
914066be07
x86: CLI & STI are privileged instructions. issue reported by @pancake
2015-03-09 10:01:58 +08:00
0423562c42
x86: RDTSC is not a privilege instructions, but all VM instructions are
2015-03-09 09:57:51 +08:00
4dd0dcb9d4
add CS_GRP_PRIVILEGE group, and also add X86_GRP_PRIVILEGE group for bunch of X86 privileged instructions
2015-03-09 00:04:45 +08:00
bb5dccedfa
core: put insns[] into separate .inc files to make it easier to manage
2015-03-08 10:54:32 +08:00
d3d574ed05
x86: XCHG* do not implicitly access *AX registers (reduce mode)
2015-03-08 05:00:17 +08:00
8b8d762580
x86: XCHG* do not implicitly access *AX registers
2015-03-08 04:58:18 +08:00
e0329ddde3
arm: printModImmOperand() should print Imm as unsigned number in some special cases
2015-03-08 00:29:20 +08:00
8e343885be
arm: update insn_ops[]
2015-03-07 16:38:35 +08:00
78699e0ff8
x86: update insn_ops[]
2015-03-07 16:33:49 +08:00
e4ca35d561
x86: delete the fiction instruction X86_INS_VPCOM
2015-03-07 16:05:06 +08:00
7a94483452
x86: remove another fiction instruction VCMP
2015-03-07 14:37:59 +08:00
e402e021b8
x86: remove unreal instruction VPCMP
2015-03-07 14:33:40 +08:00
3c626fbb98
mips: add register operands when detail = ON in the newly added function printRegisterList()
2015-03-07 13:56:41 +08:00
a81bf4247c
x86: add new field @xop_cc to struct @cs_x86
2015-03-07 13:37:32 +08:00
6bb255bb12
mips: remove mode CS_MODE_MIPSGP64
2015-03-07 09:47:11 +08:00
ad42f16b14
mips: remove the confusing mode CS_MODE_MIPSGP64
2015-03-07 00:48:06 +08:00
Nguyen Anh Quynh