1084f3afda
mips: properly support modes MIPS32R6 & CS_MODE_MIPSGP64
2014-10-29 22:20:38 +08:00
d91f964d40
* Fixed bug in Thumb2 pop caused by me incorrectly assuming that
...
ARM_SP == 13, ARM_LR == 14, and ARM_PC == 15, which is not the case
* updated CMakeLists to include building arm regression test
* added explicit casts for 64 bit visual studio 2012 build to get around
truncation warnings from size_t conversion
2014-10-23 12:04:23 -04:00
11f8e7c596
arm: B, BL, BX, BLX, BXJ belong to ARM_GRP_JUMP group. issue reported by @nanomad
2014-10-21 17:35:34 +08:00
85cfb1839c
x86: get rid of redundant X86_INS_LOCK/REP/RENE. issue reported by Pancake
2014-10-18 05:53:32 +08:00
5c0d9a4ade
Add '4*cri+cond' to operand list
2014-10-17 14:52:03 +02:00
79e253c516
Remove CS_MODE_N64
...
- This mode is for the so-called MIPS "N64" ABI; it has nothing to do with the Nintendo 64 game platform.
- N64, O64, et al. are just different ABIs for the 64-bit MIPS architecture, so we replace CS_MODE_N64 with the existing CS_MODE_64
2014-10-12 16:03:12 -07:00
c64d6292fc
mips: remove MIPS_REG_PC register. reviewed by Jay Oster
2014-10-10 21:11:50 +08:00
8bf5fa60ad
arm: remove dead code
2014-10-07 07:56:01 +08:00
b0cc71da59
bindings: update java/ocaml/python after the last change in Arm's core
2014-10-06 21:01:32 +08:00
8fb2eab459
arm: some operands can get subtracted from base register, thus have '-' sign associated. this adds subtracted field into cs_arm_op to provide this info. issue reported by Yegor Derevenets
2014-10-06 20:27:25 +08:00
f2b699a716
Don't add cr0 to the operand list as it's not displayed by the disassembly
2014-10-02 20:53:55 +02:00
e96935ed68
ppc: remove duplicate op_addReg() in printAliasInstrEx()
2014-10-02 17:09:22 +08:00
a90b047d9f
x86: simplify printPCRelImm() in calculating absolute address. also fix the issue on AT&T syntax
2014-10-02 12:04:35 +08:00
ea3c089591
some simple optimizations for speed. this improves performance about 5%
2014-10-02 10:17:55 +08:00
a92d2cba1d
x86: properly calculate absolute addresses of relative CALL & JMP. thanks Pedro for valuable helps
2014-10-01 22:10:22 +08:00
df92a7f346
mips: BC0F is relative branch instruction. bug reported by Pancake
2014-10-01 21:25:18 +08:00
48eb13c33c
ppc: add detail for alias instructions introduced in the latest change by @kratolp
2014-10-01 21:18:55 +08:00
6b731a097f
fix conflicts when merging
2014-10-01 21:05:51 +08:00
630bcd6d4e
ppc: c99
2014-10-01 21:02:30 +08:00
70fa90fbfe
ppc: coding style
2014-10-01 18:21:02 +08:00
73835104a4
Merge branch 'next' of https://github.com/aquynh/capstone into next
...
Conflicts:
arch/PowerPC/PPCInstPrinter.c
2014-10-01 11:54:14 +02:00
a3f0aef79a
PPC: Fix absolute/relative offset for branch instruction
...
PPC: Fix non handling of bc instruction that uses the CTR
2014-10-01 11:39:15 +02:00
c96f1b06b2
x86: fix Out-of-bounds read error in is16BitEquivalent(). issue reported by Coverity
2014-10-01 14:35:29 +08:00
9bf1b87a66
mips: fix out-of-bounds read error in Mips_reg_name(). issue reported by Coverity
2014-10-01 14:32:15 +08:00
e135056f17
fix a negative array index read in PPC_alias_insn(). issue reported by Coverity
2014-10-01 14:23:35 +08:00
9d54544288
mips: verify if RegDecoder can get NULL value. issue reported by Coverity
2014-10-01 14:16:07 +08:00
7e644f0fea
ppc: initialize needComma to false. issue reported by Coverity
2014-10-01 14:13:48 +08:00
9235fdc504
arm: The Thumb2 ldrexd and strexd instructions are not defined for M-class architectures
2014-09-30 07:44:50 +08:00
6756eddee5
ppc: alias instructions handled by printAliasInstrEx() miss CR* registers in detail mode. fixed
2014-09-29 23:32:14 +08:00
ca44c4897d
ppc: coding style for PPCInstPrinter.c
2014-09-29 17:58:20 +08:00
27767e8c08
merge PR of @kratolp
2014-09-29 17:54:05 +08:00
d7e42b7d36
rename all the constants marking ending from _MAX to _ENDING. this also updates Java/Python/Ocaml bindings accordingly
2014-09-29 17:15:25 +08:00
f0221a2aeb
* Fix pcc branch offset in a better way
...
* Update PPC branch alias function to print cri register
* Fix immediate branch offset sign extension for bd type branch instruction
2014-09-29 10:59:12 +02:00
d442fbc06e
arm: t2BXJ also belongs to groups ARM_GRP_NOTMCLASS & ARM_GRP_PREV8
2014-09-26 10:38:29 +08:00
54f8cef449
mips: add JR.HB & JALR.HB instructions. also update Ocaml/Python/Java bindings
2014-09-24 22:53:54 +08:00
7ac7d4e245
mips: on BEQZL, printAlias() should return instruction string. also cleanup some redundant code
2014-09-24 22:29:03 +08:00
240e1c75be
mips: print absolute target address for relative branch instructions: BEQL, BGEZALL, BGEZL, BGTZL, BLEZL, BLTZALL, BLTZL, BNEL, BNEZL, BEQZL, BC1F, BC1FL, BC1TL
2014-09-24 18:16:23 +08:00
5691dd4637
mips: fixed & added new instructions. also updated Ocaml/Python/Java bindings
2014-09-24 18:03:47 +08:00
4e87675c54
arm: relative branch should not be negative. bug reported by @acez
2014-09-23 16:49:12 +08:00
a4da8951e7
x86: relative CALL should print out absolute addresses. bug reported by @acez
2014-09-23 15:24:19 +08:00
ced9d24e35
Workaround missing <inttypes.h> on MSVC 2010
2014-09-21 17:27:11 +02:00
7e57e79800
ppc: handle branch condition for alias instructions. this also updates Python & Java bindings
2014-09-21 13:04:50 +08:00
9d6383973f
ppc: move our own alias instructions to PPCInstPrinter.c to isolate them from auto-gen code of LLVM
2014-09-20 12:02:19 +08:00
d37b0df762
merge PR of @kratolp
2014-09-20 11:27:07 +08:00
1738a3e6bf
sparc: handle some alias instructions & more details for some special instructions. update Python & Java bindings accordingly with new instructions & registers
2014-09-17 00:01:04 +08:00
05d4b83391
Extend sign of the branch destination operand
2014-09-16 17:15:50 +02:00
87736c1e5e
Update alias of PPC branch instructions
2014-09-16 17:13:39 +02:00
eaecfa4925
ppc: add PPC_INS_BNE for alias instruction BNE
2014-09-16 23:13:14 +08:00
36567558b7
mips: cleanup
2014-09-15 15:25:19 +08:00
41de05ca50
x86: correct x86_16_bit_eq_tbl[] & x86_16_bit_eq_lookup[]. idea & code provided by @obs1dium
2014-09-15 15:24:05 +08:00
72bbcacb88
x86: temporarily solve conflicts caused by the last merge
2014-09-15 14:17:49 +08:00
f46ef2e0fe
ppc: alias instruction for 'gBC 4, 2, target' to 'bne target'. issue reported by @kratolp
2014-09-15 12:12:10 +08:00
1f196d12ea
x86: CALLpcrel32 should be outputed as 'callq' in 64bit mode in AT&T syntax. ported from upstream
2014-09-10 00:00:55 +08:00
9728200d1d
x86: cpuid, xsetbv, xgetbv involve 32bit registers, not 64bit registers.
2014-09-09 11:30:20 +08:00
721d07f6b2
ppc: support alias instructions. update Python & Java bindings accordingly
2014-09-04 12:03:31 +08:00
04d9f8ee17
arm: update core with a lot more details provided in detail mode now. update Python & Java bindings to reflect the core's changes
2014-09-01 23:27:24 +08:00
e0eb06b7ab
mips: correct mapping instruction string to instruction ID for alias instructions BAL & BEQZ. bug reported by Pancake
2014-08-29 22:40:38 +08:00
4f0d7048cd
arm64: vector_index = 0 is valid. this changed invalid value of vector_index to -1
2014-08-29 15:11:23 +08:00
eda85064ee
mips: add BC1T & BLTZAL to the list of relative branch instructions. thanks @hlide for the input.
2014-08-29 09:58:07 +08:00
d1a9090eab
mips: relative branch address calculated current IP added to the relative offset. thanks Pancake, Jay Oster, hlide & jvoisin for helping
2014-08-28 11:36:57 +08:00
0c07cc9b06
zero-out instruction details, mnemonic & op_str so cs_insn doesnt have garbage in Diet mode
2014-08-27 22:31:54 +08:00
934e180e54
x86: more update to the core
2014-08-27 21:59:25 +08:00
4c95022c74
fix warnings on unused variables when compiling in Diet mode
2014-08-27 18:33:38 +08:00
5426fe0cec
arm64: change headerguard for AArch64AddressingModes.h
2014-08-27 15:17:40 +08:00
c44acedc79
x86: properly zero-out x86.operands[]
2014-08-27 10:38:40 +08:00
8a429c25ff
Merge branch 'v3' of https://github.com/aquynh/capstone into v3
2014-08-26 23:53:54 +08:00
9be1f93f88
fixed warnings in MSVC x64 compilation
2014-08-26 23:51:12 +08:00
0693809980
fixed compile errors on visual studio (variable declarations in C have to be in the top of the function)
2014-08-26 23:50:53 +08:00
5df81b4ab9
fix a c99 warning
2014-08-26 16:49:28 +08:00
f41dc3222a
Merge branch 'v3' of https://github.com/aquynh/capstone into v3
2014-08-26 16:42:55 +08:00
4b6b15fcb1
fix more MSVC warnings
2014-08-26 15:57:04 +08:00
07c92ec20a
fix warnings reported by MSVC
2014-08-26 15:35:11 +08:00
ed1234a892
xcore: update core
2014-08-26 14:11:09 +08:00
a7792ae488
systemz: update core. also update Python & Java bindings
2014-08-26 12:14:25 +08:00
14b684e07d
last commit missed a check
2014-08-25 23:45:52 +08:00
b1e87e3e31
arm, mips, ppc, spac, x86: printAliasInstr() should handle \t (besides space) as separate char between mnemonic & operands
2014-08-25 23:27:33 +08:00
8027adad6c
arm64: refine output of some instructions to make them match available test suites
2014-08-25 23:20:59 +08:00
62af137a81
arm64: printAliasInstr() should handle \t (besides space) as separate char between mnemonic & operands
2014-08-25 22:30:10 +08:00
c286b346c6
Merge branch 'arm64' into v3
2014-08-25 17:01:53 +08:00
0efef5dd48
solve some conflicts when merging -next into -v3
2014-08-25 17:01:45 +08:00
46a74e53b7
arm64: update core. this added a lot more details to cs_arm64_op struct
2014-08-25 16:47:12 +08:00
ffb6b23c7d
x86: add SMAP group for CLAC/STAC instructions
2014-08-22 14:47:29 +07:00
663829431e
x86: return proper error if cs_option() enables AT&T syntax but AT&T support is opt-out at compile time
2014-08-20 14:02:14 +08:00
a65e77baee
Merge branch 'no_att' of https://github.com/obs1dium/capstone into next
2014-08-20 13:50:29 +08:00
1ce5dea3e0
ppc: fix an unused variable warning
2014-08-20 11:51:46 +08:00
2725a3fea8
X86GenInstrInfo size reduction
2014-08-19 20:12:39 +02:00
b7e2ff451f
x86.operands array wasn't fully cleared
2014-08-17 21:46:30 +02:00
86e845056d
renamed CAPSTONE_NO_ATT to CAPSTONE_X86_ATT_DISABLE, added options to makefile, cmake, compile.txt
2014-08-17 20:59:05 +02:00
4f412c4483
Selectively disable AT&T syntax in non-diet mode to reduce library size
2014-08-17 19:38:20 +02:00
a726402513
sparc: update core. this added/removed some instructions & groups. updated Python & Java bindings accordingly
2014-08-15 18:29:17 +08:00
2124b8a9c9
mips: indentations
2014-08-15 16:37:03 +08:00
159ddbd99f
ppc: add new groups to group_name_maps[]
2014-08-15 16:35:12 +08:00
64f36d9759
change '2013>' to 2013-2014
2014-08-15 13:53:44 +08:00
91a64776a8
ppc: fix a mistake on interpreting CR registers by deleting CR8 -> CR31
2014-08-15 13:48:11 +08:00
dd3deec1e9
ppc: update core. this added new instructions, groups & registers. updated Python & Java bindings accordingly
2014-08-15 13:26:12 +08:00
0f0eb9851a
mips: update core. this added bunch of new instructions & groups. updated Python & Java bindings accordingly
2014-08-14 18:26:39 +08:00
7c089fd6c6
arm: add new mode CS_MODE_MCLASS for Cortex-M series. updated Python & Java bindings accordingly
2014-08-13 23:08:40 +08:00
b52f11f636
arm: update core. this added a new instruction UDF. also updated Python+Java bindings accordingly
2014-08-13 22:38:15 +08:00
0b690387b3
x86: update core with upstream. this added bunch of new instructions & groups. also updated Python & Java bindings after the core change
2014-08-13 13:01:50 +08:00
4db4d9bdd7
xcore: fix an warning of unused array when DIET mode is enable
2014-08-13 00:29:51 +08:00
590f23af54
arm: do not need to initialize local variable opcode in DecodeRegListOperand()
2014-07-31 21:23:51 +08:00
0c235e15ab
arm: some simple improvements & cleanups
2014-07-31 21:16:54 +08:00
26dfbc6677
fix indentation introduced by the latest merge. also move test_arm_regression.c into suite/arm/ and add Makefile for it
2014-07-31 18:24:51 +08:00
5d8067822b
Merge branch 'next' of https://github.com/flyingsymbols/capstone into arm
2014-07-31 15:36:13 +08:00
48eb7a6614
x86: INTO is invalid in 64bit mode. bug reported by Pancake & Ange Albertini
2014-07-21 23:08:52 +08:00
298d413bbc
* added a test file to suite for testing invalid and valid instruction sequences
...
* fixed and added a test for a thumb-2 invalid sequence that was incorrectly allowed before these changes (pop.w with sp argument included)
* fixed and added a test for a blx from thumb to ARM that had its immediate argument incorrect (misaligned)
* eliminated some warnings by explicitly casting so I could turn on
treat warnings as errors locally
General notes:
* probably worth turning on treat all warnings as errors in the msvc project files, had a subtle bug that resulted from a missing declaration causing differences in dll and static compilation modes
( code was working incorrectly in dll form because of missing declaration in arch/ARM/ARMMapping.h for new function ARM_blx_to_arm_mode. Something about the linking was confusing ld when making the dll, and the resulting offsets were wonky (e.g. the added ble test would show up as #0x1fc instead of #0x1fe like it should have )
* the invalid pop was being treated as a soft fail which then gets coerced
to a success because it is != MCDisassembler_Fail in Thumb_getInstruction
what are the semantics of a soft fail? Maybe we should be able to set up
whether or not we want a soft fail to be a real fail in the csh struct?
2014-07-15 04:33:40 -04:00
55cd996add
sparc: initialize detail->sparc in Sparc_getInstruction. bug reported by Ben Nagy
2014-07-09 13:08:17 +08:00
e1fc8a83ba
sparc: initialize detail->sparc in Sparc_getInstruction. bug reported by Ben Nagy
2014-07-09 13:07:45 +08:00
4d2eba7f43
systemz: initialize detail->sysz in SystemZ_getInstruction. bug reported by Ben Nagy
2014-07-09 11:27:09 +08:00
39d6b2f066
systemz: initialize detail->sysz in SystemZ_getInstruction. bug reported by Ben Nagy
2014-07-09 11:26:53 +08:00
650f96ce43
add new API cs_group_name() to return group name in string, given the group id
2014-07-08 08:59:27 +08:00
bb8bbaa930
x86: test reg, [mem] -> test [mem], reg. bug reported by Gabriel Quadros
2014-07-04 09:48:58 +08:00
dbdb61a9cf
x86: regs_write[] of RDTSC & RDTSCP depend on @mode
2014-07-02 12:45:02 +08:00
9f6ed7155a
x86: add @rex to cs_x86 struct. updated python & java binding for this change
2014-07-01 10:13:28 +08:00
32e2c6c9c7
x86: address-size prefix should override RIP relative address in x64 mode. bug reported by @hlide
2014-06-30 07:58:33 +08:00
ed6b8c5a96
x86: address-size prefix should override RIP relative address in x64 mode. bug reported by @hlide
2014-06-30 07:57:29 +08:00
656ebc9625
x86: handle RIP relative addressing in 64bit mode properly. bug reported by @hlide
2014-06-30 02:01:42 +08:00
af6db2afe8
x86: handle RIP relative addressing in 64bit mode properly. bug reported by @hlide
2014-06-30 02:01:04 +08:00
7ef3700550
x86: SHL reg, 1 has one too many operands. bug reported by Sean Heelan
2014-06-27 21:54:45 +08:00
1a66fecdbc
x86: support avx_sae & avx_rm in cs_x86 struct. this also updates Python & Java bindings following the core's change
2014-06-26 12:09:15 +08:00
12e6e31389
x86: rename zero_opmask of cs_x86_op to avx_zero_opmask
2014-06-26 11:27:24 +08:00
92a3d4c079
x86: add AVX's zero_opmask to cs_x86_op struct. updated Python & Java bindings for this change
2014-06-25 23:10:39 +08:00
f1ec52628e
x86: provide size for X86_OP_IMM operand. thank Gabriel Quadros for some suggestions
2014-06-25 22:03:18 +08:00
e1aba1703f
x86: fix all {cc} instructions to have correct instruction ID
2014-06-25 21:06:44 +08:00
4c5eabc32b
x86: support SSE_CC & AVX_CC in cs_x86 struct. this also updates Python & Java bindings
2014-06-24 23:50:41 +08:00
0d716450fc
x86: add avx_bcast to cs_x86_op to support AVX512 instructions. this also updates Python & Java binding
2014-06-24 22:51:56 +08:00
bb6440c5ef
x86: extend cs_x86.opcode to 4 bytes to contain EVEX opcode. this also updates Python binding following this interface change
2014-06-24 21:46:54 +08:00
15b746fe4f
x86: op_addReg() & op_addImm() only work when detail mode is ON
2014-06-24 16:13:37 +08:00
c74ec28691
x86: LEA for 16bit register should have pointer size of word, not dword. bug reported by Gabriel Quadros
2014-06-24 15:49:26 +08:00
14ba46bfab
x86: add segment to x86_op_mem struct. this fixes a bug in generating detail for instructions with segment override. bug reported by Sean Heelan.
2014-06-24 14:32:01 +08:00
eb2f3fb85a
x86: properly reset prefixPresent for prefix0/1 group
2014-06-20 11:15:58 +08:00
1e688d4ff9
x86: do not use markup in AT&T syntax
2014-06-18 14:28:55 +08:00
46291c139f
Merge branch 'next' into opsize
2014-06-18 14:21:49 +08:00
44db3c37fa
x86: support CS_OPT_MODE for dynamically changing mode at run-time
2014-06-18 14:18:47 +08:00
cff03629ac
arm64: assign NULL to char pointer, not zero. bug reported by Coverity
2014-06-18 14:04:42 +08:00
1085073f8f
x86: remove disp_size, imm_size, op_size. add size to each operand. thanks Gabriel Quadros for some nice ideas
2014-06-18 12:16:24 +08:00
73eb5d5486
arm: op_addImm() is called only when detail mode is ON
2014-06-17 18:08:29 +08:00
cae09bf543
replace offset_of with offsetof from stddef.h
2014-06-17 14:58:39 +08:00
ebe2443b9b
arm: some special instructions need to have numerical operand added manually in printInstruction()
2014-06-17 13:56:01 +08:00
eccb9da7a8
arm64: zeroout a whole cs_arm64 struct of MCI in *getInstruction().
2014-06-17 13:34:25 +08:00
73bbbb3800
arm: add ASRS, LSRS, VCLE, VCLT instructions. update Python & Java bindings at the same time
2014-06-17 13:29:54 +08:00
8693fcdc99
arm: correct operand setup for REG type in printAddrMode3OffsetOperand()
2014-06-17 13:28:33 +08:00
2a461ed422
arm: zeroout a whole cs_arm struct in *getInstruction(). this makes sure operand of REG type has shift type = 0 by default
2014-06-17 13:27:38 +08:00
9cf88119fb
x86: InternalInstruction@xAcquireRelease should be initialized to 0 (FALSE)
2014-06-16 18:32:34 +08:00
495295ecd4
MCInst_Init() is arch-independent
2014-06-16 15:54:32 +08:00
215e76b223
ppc: use MCInst_insert0() instead of MCInst_insert() to avoid malloc/free
2014-06-16 14:47:43 +08:00
d06f3d662b
xcore: use CreateImm0() & CreateReg0() to create MCOperand* to avoid using malloc/free
2014-06-16 14:35:08 +08:00
88fca42a5f
xcore: use SStream_concat0() instead of SStream_concat() for simple string processing whenever possible
2014-06-16 14:30:19 +08:00
7062988855
systemz: use CreateImm0() & CreateReg0() to create MCOperand* to avoid using malloc/free
2014-06-16 13:09:15 +08:00
bddd215099
systemz: use SStream_concat0() instead of SStream_concat() for simple string processing whenever possible
2014-06-16 13:02:41 +08:00
3d3b6cec01
sparc: use CreateImm0() & CreateReg0() to create MCOperand* to avoid using malloc/free
2014-06-16 12:57:02 +08:00
9b91de0ae3
sparc: use SStream_concat0() instead of SStream_concat() for simple string processing whenever possible
2014-06-16 12:51:07 +08:00
7f945d3655
ppc: use CreateImm0() & CreateReg0() to create MCOperand* to avoid using malloc/free
2014-06-16 12:34:02 +08:00
7f15f67544
ppc: use SStream_concat0() instead of SStream_concat() for simple string processing whenever possible
2014-06-16 12:11:50 +08:00
f08b83ddba
mips: use CreateImm0() & CreateReg0() to create MCOperand* to avoid using malloc/free
2014-06-16 12:04:25 +08:00
0c764d4a70
mips: use SStream_concat0() instead of SStream_concat() for simple string processing whenever possible
2014-06-16 11:53:08 +08:00
d489a679f4
arm64: use CreateImm0() & CreateReg0() to create MCOperand* to avoid using malloc/free
2014-06-16 11:46:20 +08:00
cbb33583b3
arm64: use SStream_concat0() instead of SStream_concat() for simple string processing whenever possible
2014-06-16 11:16:30 +08:00
9678705d57
arm: convert MCOperand_CreateReg() to MCOperand_CreateReg0() to avoid malloc/free
2014-06-10 13:59:55 +07:00
748687df46
arm: convert the left-over MCOperand_CreateImm to MCOperand_CreateImm0
2014-06-10 09:18:39 +07:00
0f648ea3e8
arm: use CreateImm0() & CreateReg0() to create MCOperand* to avoid using malloc/free to improve performance
2014-06-10 01:01:23 +07:00
8c1104b567
arm: do not use markup
2014-06-10 00:39:06 +07:00
dd9225b930
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 00:37:53 +07:00
b95647d2c1
systemz & xcore: create details only when detail mode is ON. this fixes some crashes in tests/test
2014-06-09 18:49:37 +07:00
69582d71ae
initialize cs_insn.detail by properly zero-out right members for each arch
2014-06-09 17:50:01 +07:00
29fd0f6405
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd4
2014-06-09 08:00:18 +07:00
5329a6ffd4
directly update cs_insn from MCInst interface to avoid multiple memcpy()
2014-06-08 23:35:52 +07:00
8cae86ccfa
x86: copy prefix back after updating it in X86_lockrep()
2014-06-07 23:47:35 +08:00
22a5a761d8
x86: simplify byteReader_t
2014-06-07 23:41:20 +08:00
30c065998b
optimize memset() of MCInst_Init()
2014-06-07 13:30:59 +08:00
5474d877b0
x86: optimize struct InternalInstruction for memset(). this improve performance by around 4%
2014-06-07 12:56:44 +08:00
0ad226e332
x86: fix a conflict when merging -next to -optimize branch
2014-06-06 00:59:15 +08:00
cf0813809a
x86: more simplification on managing MCOperand. this also fixes a bug in handling memory reference instructions
2014-06-06 00:56:46 +08:00
0e534bf0ff
x86: correct the related comment of the last commit
2014-06-05 17:05:16 +07:00
9417ad6cd5
x86: printDstIdx() should only print segment in non-64bit mode. bug reported by Filipe Cabecinhas (@filcab)
2014-06-05 17:03:52 +07:00
e70a043a04
x86: more simplification for better performance
2014-06-05 10:52:43 +08:00
937e48314c
x86: avoid malloc/free MCOperand with new API of MCInst: MCInst_addOperand0, MCInst_CreateReg0, MCInst_CreateImm0
2014-06-04 22:51:51 +07:00
a62b9a07e4
x86: use SStream_concat0() where possible to improve performance - for AT&T and X86_REDUCE
2014-06-04 22:25:48 +07:00
46b6693d36
x86: save prefixes to avoid expensive copying loop. based on idea of Dang Hoang Vu
2014-06-04 19:04:46 +08:00
b76233c648
avoid using vsnprintf when possible for SStream_concat() to improve performance. based on the idea of Dang Hoang Vu.
2014-06-04 18:31:02 +08:00
368c45b4c6
x86 instruction groups: Add SYSEXIT and SYSRET to the X86_GRP_IRET group
2014-06-04 00:08:46 -07:00
a19d3f0b60
Merge branch 'feature/x86-groups' of https://github.com/parasyte/capstone into test
2014-06-04 13:35:12 +07:00
6b00344f23
x86 instruction groups: Fix RET/IRET mapping.
2014-06-03 23:31:58 -07:00
0577bb728c
x86: ATT syntax does not print word size pointer like Intel syntax
2014-06-03 13:50:35 +07:00
6f74ccc97a
Add new x86 instruction groups
...
- VM: Virtual Machine
- INT: Interrupts
- IRET: Interupt returns
- CALL: Subroutine call
- RET: Subroutine return
Includes a special case for writes to port 0xb2, which triggers an SMI
2014-06-02 22:21:41 -07:00
c70442edc6
arm: shift info associates with the right op in LDR instruction. bug reported by Daniel Colascione
2014-06-01 11:35:34 +07:00
a04ee4feb8
arm: add missing the check for detail mode in the last commit
2014-06-01 10:52:01 +07:00
b79d915a38
arm: add missing operand info for Thumb instruction vldr. bug reported by Daniel Colascione
2014-06-01 10:48:55 +07:00
bb71c13098
arm: add missing operand info for Thumb instruction LDR involving label. bug reported by Daniel Colascione
2014-06-01 10:14:31 +07:00
6eb55cf52e
arm: add operand details for 'mov pc, lr'. bug reported by Daniel Colascione
2014-06-01 10:03:14 +07:00
48b6cb4ce5
arm: CC_AL is the default code condition for instructions without CC. bug reported by Daniel Colascione
2014-06-01 09:45:19 +07:00
5e2e660be7
fix some warnings reported by Coverity
2014-05-30 17:43:36 +08:00
2c20a1b5a3
ppc: wrong comparison in printOperand(). bug found by Coverity
2014-05-30 17:00:20 +08:00
b70e121ce3
x86: FP instructions are only available when X86_REDUCE mode is off
2014-05-28 15:57:51 +08:00
d0023197eb
cmake: support Sparc, SystemZ & XCore
2014-05-28 15:15:00 +08:00
3a5965eb05
xcore: fix some warnings with Diet mode
2014-05-28 15:14:28 +08:00
0150f06553
x86: fix a warning on Diet mode
2014-05-28 15:04:15 +08:00
9148420b0d
replace strcasecmp() with strcmp()
2014-05-28 12:57:46 +08:00
d69f9ded5b
x86: delete dead code
2014-05-28 12:39:11 +08:00
b2e566ac88
xcore: use strcpy() rather than strncpy()
2014-05-28 11:35:19 +08:00
2a33afe6e8
msvc: make MSVC shutup on strncpy()
2014-05-28 00:24:33 +08:00
dc1af545c0
msvc: fix warnings
2014-05-28 00:14:22 +08:00
be2b788dc1
xcore: handle details for some special tricky instructions
2014-05-27 23:34:03 +08:00
f721e3124d
Disassembler -> Disassembly
2014-05-27 10:45:58 +08:00
8f50ba894c
Merge branch 'next' into xcore
2014-05-27 10:39:11 +08:00
04f2ec6d0f
cleanup redundant headers included
2014-05-27 10:39:04 +08:00
2cf9c524da
x86: MOV64rr belongs to GRP_MODE64 group. bug reported by Jason Oster
2014-05-27 07:23:53 +08:00
553bb488d7
python: support XCore
2014-05-26 23:47:45 +08:00
c80d840ffc
add XCore architecture
2014-05-26 23:02:48 +08:00
3dc080c2b6
systemz: cleanup SystemZGenDisassemblerTables.inc
2014-05-26 15:54:16 +08:00
5d6383e335
sparc: SPARC_CC_ICC_N should not have the same value as SPARC_CC_INVALID. bug reported by Jason Oster
2014-05-25 13:48:06 +08:00
6380446222
Add `r0l` register to SystemZMapping.c
2014-05-24 21:26:12 -07:00
4ebd062ee3
x86: cleanup unused code
2014-05-22 12:11:35 +08:00
fed098f9a7
x86: eliminate irrelevant prefixes in x86.prefix[] - such as f2/f3 prefixed irrelevant instructions
2014-05-22 12:10:21 +08:00
1e93adf5c3
x86: add CL operand into details for 'SHL *, CL' instruction
2014-05-21 17:10:10 +08:00
7a65ad7e4b
x86: detail operands for 'fstpnce st(0), st(0)' & 'fstpst(7), st(0)'
2014-05-21 16:18:56 +08:00
b6e3f01bb8
x86: handle REP MOVSD/CMPSD/SCASD/LODSD/STOSD properly (due to confused 128bit media instructions having the same mnemonics)
2014-05-21 15:11:58 +08:00
3a86d92e7c
x86: correct instructions related to REP prefix
2014-05-21 14:12:24 +08:00
1d6f7ee50e
x86: prefix REP/REPNE are only relevant for MOVS/CMPS/SCAS/LDOS/STOS/INS/OUTS instructions
2014-05-21 12:38:10 +08:00
984ed7e9e8
MIPS: Add HI, LO, and PC registers to MipsMapping.c
...
- Using MIPS_REG_HI, MIPS_REG_LO, and MIPS_REG_PC with cs_reg_name() caused out-of-bounds reads
2014-05-19 22:56:19 -07:00
6456481508
x86: add immediate operand (1) for SHL/SHR/ROR/ROL/SAR/SAL in detail mode & Intel syntax
2014-05-19 16:46:31 +08:00
f338657f17
x86: set syntax variable when changing syntax with cs_option()
2014-05-19 16:34:54 +08:00
1922b2f74b
arm64: clean reg_name_maps[]
2014-05-18 10:30:09 +08:00
c5cad6cab3
avoid using stdbool.h to support compilers without C99 support
2014-05-15 21:40:24 +08:00
1d2e69b869
msvc: remove headers/ directory & replace it with include/platform.h
2014-05-15 13:56:54 +08:00
7bab8dc12e
x86: AT&T syntax is irrelevant in Diet mode, so setting this syntax should return CS_ERR_DIET error
2014-05-14 23:48:17 +08:00
f7850266d5
x86: enable AT&T code only when DIET mode is off
2014-05-14 22:03:06 +08:00
0ffd811d67
merge next branch
2014-05-14 14:33:03 +08:00
b2a88df20f
MSVC added some code picked up by MingW, so cross-win32/74 compile is broken. this fixes the issue
2014-05-14 14:28:40 +08:00
506890863c
x86: assembly syntax is irrelevant in Diet mode. this optimization reduces library size to only 180KB on OSX
2014-05-14 12:26:53 +08:00
8598a219f3
enable arch code from source with CAPSTONE_HAS_* for MSVC to pick up
2014-05-14 11:26:41 +08:00
eb2e840887
x86: fix C89 issues for X86GenAsmWriter1_reduce.inc & X86GenAsmWriter_reduce.inc
2014-05-12 21:53:53 +08:00
cfcace3f43
arm: make checkDecoderPredicate() handle boolean casting for MSVC (redone in more systematic way for autogen code)
2014-05-12 21:38:05 +08:00
805fed5162
make checkDecoderPredicate() handle boolean casting for MSVC
2014-05-12 21:29:04 +08:00
ef3e450f1a
arm: checkDecoderPredicate() needs to handle Bool data type in the way that MSVC can understand
2014-05-12 18:15:18 +08:00
043702e9ef
more fixes for warnings reported by MSVC
2014-05-12 16:17:00 +08:00
6893ec535e
more warnings fixed reported by MSVC
2014-05-12 15:36:38 +08:00
638835a1d5
fix some warnings reported by MSVC
2014-05-12 15:15:32 +08:00
abffe02a46
sparc: recover autogen code in arch/Sparc/SparcGenDisassemblerTables.inc
2014-05-12 13:48:22 +08:00
bb0744df5d
do not initialize some local vars unnecessarily. this problem was introduced when we fixed C89 issues for MSVC
2014-05-12 13:41:49 +08:00
2d34251889
x86: handle 16bit segment bound for JMP. bug reported by Pancake & Anton Kochkov
2014-05-11 15:33:11 +08:00
0596e11bd5
arm64: fix a wrong int type of a local var in printLabelOperand. this bug was introduced when we fixed C89 issue for MSVC
2014-05-10 09:17:48 +08:00
35c8467275
still want that to compile on other systems
2014-05-09 20:51:02 +01:00
605faf1db9
moved the hardcoded macros in the vcproj & just disable the warning for the crt
2014-05-09 20:40:00 +01:00
b5e7db57ee
Merge branch 'next' into msvc2
2014-05-09 17:38:31 +08:00
d27b0155ef
arm: add BLX_pred into the list of relative branch instructions
2014-05-09 17:34:54 +08:00
bc80b3dc24
arm: fix some more Thumb relative branch instructions. bug reported by Giovanni Nanomad Condello
2014-05-09 17:31:41 +08:00
42706a39e2
indentation with tab
2014-05-09 07:33:35 +08:00
336bf29230
Merge branch 'next' of https://github.com/0vercl0k/capstone into msvc2
2014-05-09 07:10:47 +08:00
d43187d4f9
arm: BLXi is another relative branch instruction to be fixed. bug reported by Giovanni Nanomad Condello
2014-05-09 07:02:51 +08:00
Nguyen Anh Quynh