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1727 Commits

Author SHA1 Message Date
billow 3bc09883bd fix `CADD` `CSUB` 2023-04-14 00:35:54 +08:00
billow f3f62b05dc add tc110 tests and fix tricore decode 2023-04-14 00:35:54 +08:00
billow 125d8bc115 feat: Update Tricore assembly code and disassembler logic. 
- Add new Tricore test `tc110.s.cs`
 2023-04-14 00:35:53 +08:00
billow d1404e8e79 fix tricore tests 2023-04-14 00:35:52 +08:00
billow d31b9cf0b9 fix TriCoreDisassembler.c from tests 2023-04-14 00:35:51 +08:00
billow 8e19b13abd fix 2023-04-14 00:35:49 +08:00
billow 6d26813d56 feat: Add support for TriCore feature bits and new architectures 
- Add support for new Tricore architectures
- Clean up redundant instructions definitions
- Modify architecture options for the TRICORE mode
- Update disallowed modes for Tricore architecture
 2023-04-14 00:35:47 +08:00
billow 5ebe09366b fix 2023-04-14 00:35:46 +08:00
billow adebfda12c refactor: Optimize TriCore instructions in arch/TriCore/TriCoreInstrInfo.td 
- Add missing instructions and update existing ones
 2023-04-14 00:35:45 +08:00
billow 15a49dee30 refactor: Improve TriCore floating-point operations in instruction set 2023-04-14 00:35:44 +08:00
billow 8603d7ccb4 Refactor: Optimize TriCore instruction information. 
- Refactor TriCore instruction info
- Improve code organization
- Optimize instruction handling
- Eliminate unnecessary code duplication
 2023-04-14 00:35:43 +08:00
billow 07d3238d9f Add support for TriCore V162 and new instructions/operands. 
- Add new instruction `MOVZ_A`, remove instruction `NOT`, and add several new multiply and multiply-subtract instructions
- Move `multiclass mISR_1` and `multiclass mISYS_0` to separate file and fix typo in `rfe` instruction in `mISYS_0`
- Add support for new CPU feature `TriCore_FEATURE_HasV162` and update relevant inc files.
 2023-04-14 00:35:42 +08:00
billow d75ff4d9ed refactor: Improve instruction handling for TriCore architecture 2023-04-14 00:35:41 +08:00
billow 0b4546820e refactor: Improve TriCore instruction definitions in architecture file 
- Refactor architecture specific code for TriCore
- Update TriCore instruction information in [arch/TriCore/TriCoreInstrInfo.td]
- Improve performance and readability of relevant functions
 2023-04-14 00:35:40 +08:00
billow 07065c525b Optimize TriCore instruction information. 
- Refactor and optimize instruction encoding for TriCore architecture
- Improve performance and reduce code size by simplifying opcodes and encoding logic
- Update instruction definitions in TriCoreInstrInfo.td file
- Omit some large but non-essential changes in diff summary for readability
 2023-04-14 00:35:39 +08:00
billow 676477d465 Optimize TriCore instruction information. 
- Refactor TriCore instructions
- Simplify operand encoding for better readability
 2023-04-14 00:35:39 +08:00
billow 8853900171 refactor: Refactor TriCore instruction classes and operands 2023-04-14 00:35:38 +08:00
billow c5239815a5 refactor: Improve Architecture Instruction Information. 
- Refactor TriCore instruction information file
- Simplify and optimize certain instructions
 2023-04-14 00:35:37 +08:00
billow 6fe3766434 refactor: Refactor TriCore instruction definitions and mappings 
- Add new `multiclass mI_MADDRsh_` to handle `MADDR_H` and `MADDRS_H` in `arch/TriCore/TriCoreInstrInfo.td`
 2023-04-14 00:35:36 +08:00
billow 8b56ae652b refactor: Add new TriCore instructions and remove deprecated ones. 
- Remove deprecated instructions
- Update comments and formatting
 2023-04-14 00:35:35 +08:00
billow d41decd0f0 feat: Add and remove TriCore instructions. 
- Add 3 new TriCore instructions
- Remove TriCore instruction "TriCore_INS_INIT"
- Alphabetized and rearranged various TriCore instructions
- Commented out code remains in the diff but is not part of the program.
 2023-04-14 00:35:34 +08:00
billow d631ecc723 add `tricore_feature` support 2023-04-14 00:35:33 +08:00
billow a076fdeb0a refactor: Refactor TriCore instruction decoding and register definition. 
- Update TriCore processor register definitions with auto-generated file `TriCoreGenCSRegEnum.inc`
- Add several new TriCore processor instructions with auto-generated file `TriCoreGenCSInsnEnum.inc`
- Update TriCore_OP_GROUP enumeration with auto-generated file `TriCoreGenCSOpGroup.inc`
- Rename and restructure TriCore processor register classes
- Remove unused register class definitions and related code
 2023-04-14 00:35:32 +08:00
billow d58a83c7f1 refactor: Update TriCore instruction requirements 
- Update `Requires` directives for several instructions to reflect changes in hardware versions
 2023-04-14 00:35:32 +08:00
billow 7dbeb5c58f refactor: Add support for new TriCore instructions and constraints. 
- Add support for V110 and V120 in various LD instructions
- Define new multiclass for code reuse
- Restructure LD_A_v120 in favor of LD_A with Requires constraint
- Add new defs for LT_U with suffixes for V110 support
 2023-04-14 00:35:31 +08:00
billow 2fa188ec5a refactor: Improve TriCore instruction handling. 
- Add new instructions for TriCore architecture
- Implement changes to TriCoreInstrInfo.td
 2023-04-14 00:35:30 +08:00
billow d515e62ddc refactor: Refactor TriCore register names. 
- Rename TriCore register names for better readability
- Update TriCore instruction information
 2023-04-14 00:35:29 +08:00
billow ad0e18fece fix `cachea` 2023-04-14 00:35:28 +08:00
billow 4567335c20 add some tricore v1.1 inst 2023-04-14 00:35:27 +08:00
billow 753b6a4ce0 cleanup 2023-04-14 00:35:26 +08:00
billow b9eba6f1fd add tricore Predicates 2023-04-14 00:35:25 +08:00
billow c862106861 just add TriCoreISA enum 2023-04-14 00:35:25 +08:00
billow d759996f15 fix: `disp` print and fill 2023-04-14 00:35:24 +08:00
billow 878e09db04 fix: decode `j` `call` `loop` 2023-04-14 00:35:22 +08:00
billow d9e715bc17 feat: Fix bugs and update instructions for TriCore architecture. 
- Fix bug in `printDisp8Imm` function in `TriCoreInstPrinter.c`
- Add new `CALL_sb` instruction to `TriCoreInstrInfo.td`
- Reorder instruction definitions and operands in `TriCoreInstrInfo.td`
 2023-04-14 00:35:21 +08:00
billow fae62b74bf refactor: Refactor TriCore instructions and operands 
- Add new immediate operands and refactor code for better readability in TriCoreInstrInfo
- Update InstPrinter functions to handle new immediate operands and remove unused function
 2023-04-14 00:35:20 +08:00
billow 5b7e20ad55 fix: TriCore Instruction Formats and Printing 
- Add new operand type `off18imm`
- Add `printOff18Imm` function for printing specific immediate value
 2023-04-14 00:35:19 +08:00
billow 7e937d10ad Fix: TriCore instruction operations and decoding. 2023-04-14 00:35:18 +08:00
billow 6bd7b4b894 fix: decode error 2023-04-14 00:35:17 +08:00
billow 9bdd734d0e fix: TriCore instruction decoding and printing. 
- Modify TriCore instructions to use bracket syntax and offsets for better clarity
- Add off4_fixup and printSExtImm_n
 2023-04-14 00:35:17 +08:00
billow a78a46a397 fix: TriCore architecture disassembly codes 
- Rename `ISLR_post_increment` to `ISLR_pos` for clarity
- Fix register decoding for TriCore architecture in `TriCoreDisassembler.c`
- Add new file `LoadStore.s.cs` to `suite/MC/TriCore`
 2023-04-14 00:35:16 +08:00
billow f19a93ad43 add `BO` 2023-04-14 00:35:14 +08:00
billow 6381b0750e add `MTCR` 2023-04-14 00:35:13 +08:00
billow 1c190c49cc Whether to call `a10` a `sp` 2023-04-14 00:35:12 +08:00
billow fc3cf3aa80 fix `imask` 2023-04-14 00:35:11 +08:00
billow 63db2dc804 fix `mov.a` `mov.d` 2023-04-14 00:35:10 +08:00
billow 927e075500 fix 2023-04-14 00:35:09 +08:00
billow fec75ae36a fix `RR` 2023-04-14 00:35:09 +08:00
billow 85d2936f87 fix `INSERT_rrpw` 2023-04-14 00:35:08 +08:00
billow 3a6076a6d4 fix `RRPW` 2023-04-14 00:35:07 +08:00
billow 9567b8915d fix 2023-04-14 00:35:06 +08:00
billow 70058f9104 fix `SRRS` 2023-04-14 00:35:05 +08:00
billow fd8a2b8dc9 fix `BO` `BOL` 2023-04-14 00:35:04 +08:00
billow 001f3487b1 fix `DecodeRegisterClass` 2023-04-14 00:35:03 +08:00
billow 8fa4d4cb99 fix `DecodeRegisterClass` 
- `DecodeABSInstruction`
- `DecodeRLCInstruction`
- `DecodeSSRInstruction`
- `DecodeSRCInstruction`
 2023-04-14 00:35:02 +08:00
billow 98f0eb61a8 fix 2023-04-14 00:35:01 +08:00
billow e5b44ff47c add `sign_ext` `zero_ext` 2023-04-14 00:35:01 +08:00
billow cffcfdbb4c fix 2023-04-14 00:34:58 +08:00
billow 564f962146 fix 2023-04-14 00:34:57 +08:00
billow 75c5e26358 fix `DecodeInstruction` 2023-04-14 00:34:54 +08:00
billow bb16f2d785 `Decode*Instruction` 2023-04-14 00:34:53 +08:00
billow b1f7cfeb84 fix build 2023-04-14 00:34:52 +08:00
billow 30432c862d add FPU Instructions 2023-04-14 00:34:52 +08:00
billow 33080bb326 update `TriCore*.inc` 2023-04-14 00:34:51 +08:00
billow 1a148e2b65 ST SUB SYSCALL XOR XNOR 2023-04-14 00:34:50 +08:00
billow 1e44b5346d SHA* ST* 2023-04-14 00:34:49 +08:00
billow 27e5ef647a RSUB* SAT* SEL* SH* 2023-04-14 00:34:48 +08:00
billow 093829be2b modified: arch/TriCore/TriCoreInstrInfo.td 2023-04-14 00:34:47 +08:00
billow f7aa5d17ff `MUL*` `NAND*` `NE*` `NOP` `NOR` `OR` 2023-04-14 00:34:46 +08:00
billow 26454fd243 `MSUB*` 2023-04-14 00:34:45 +08:00
billow 248f7c6f14 `MOV*` 2023-04-14 00:34:45 +08:00
billow 86f6a60818 `MAX*` `MFCR` `MIN*` 2023-04-14 00:34:44 +08:00
billow dae993af5d fix `MADD*` 2023-04-14 00:34:43 +08:00
billow 7f32015cfb `MADD*` 2023-04-14 00:34:42 +08:00
billow 3bbb2d5b76 - `LD*` 
- `LEA*`
- `LHA*`
- `LOOP*`
- `LT*`
 2023-04-14 00:34:41 +08:00
billow 16befd3724 `ld*` 2023-04-14 00:34:40 +08:00
billow 30cf8288e8 modified: arch/TriCore/TriCoreInstrInfo.td 2023-04-14 00:34:39 +08:00
billow 59da967a01 Changes to be committed: 
modified:   arch/TriCore/TriCoreInstrFormats.td
	modified:   arch/TriCore/TriCoreInstrInfo.td
 2023-04-14 00:34:38 +08:00
billow 1968699d4d add: 
- `DEXTR*`
- `DISABLE*`
- `DSYNC*`
- `DVADJ*`
- `DIV*`
- `DVINIT*`
- `DVSTEP*`
- `ENABLE*`
- `EQ*`
 2023-04-14 00:34:38 +08:00
billow f8c7dc474f add: 
- `CALL*`
- `CL*`
- `CMOV*`
- `CMPSWAP_W`
- `CRC*`
- `CSUB*`
- `DEBUG*`
 2023-04-14 00:34:37 +08:00
billow f7175332ba add `cadd` 2023-04-14 00:34:36 +08:00
billow 688ee6a07c add `cache` inst 2023-04-14 00:34:35 +08:00
billow 69e051687a add `AND` 2023-04-14 00:34:34 +08:00
billow b5b456b4f4 add more `ADD` 2023-04-14 00:34:33 +08:00
billow 96aec6be49 Add more multiclass 2023-04-14 00:34:32 +08:00
billow ed94f7fcfc add more `ADD` 2023-04-14 00:34:31 +08:00
billow 175691f2cf add `ABS` 2023-04-14 00:34:30 +08:00
billow e6513b26ad add TriCore tablegen files 2023-04-14 00:34:30 +08:00
billow d1021f4a6b Fix build and test 2023-04-14 00:34:28 +08:00
Sidney Pontes Filho 81b1df7f91 Transfer modifications of TriDis/llvm-tricore on Feb, 04 2017 2023-04-14 00:34:25 +08:00
Sidney Pontes Filho 707c57b921 Fix TriCore register mapping 2023-04-14 00:34:23 +08:00
Sidney Pontes Filho 8ea8d69cc5 Fix TriCore Mapping 2023-04-14 00:34:23 +08:00
Sidney Pontes Filho 72cdfdab80 Adjustments in TriCore and add more instructions into tests/test_tricore.c 2023-04-14 00:34:22 +08:00
Sidney Pontes Filho 651aa5a1f1 Fix memory access printing and clean unused functions 2023-04-14 00:34:21 +08:00
Sidney Pontes Filho 4aace70036 Transfer modifications of TriDis/llvm-tricore on Oct 05, 2016 2023-04-14 00:34:20 +08:00
Sidney Pontes Filho 4bc36ec68b Transfer modifications of TriDis/llvm-tricore on Sep 20, 2016 2023-04-14 00:34:19 +08:00
Sidney Pontes Filho f855c92b46 Adjust printing of Registers and upgrade TriCore test 2023-04-14 00:34:18 +08:00
Sidney Pontes Filho 3c63df7f45 Fix printing MemSrc 2023-04-14 00:34:17 +08:00
Sidney Pontes Filho edbd73409c Remove all compiler warnings 2023-04-14 00:34:17 +08:00
Sidney Pontes Filho dd4011297b Fix all compiler errors 2023-04-14 00:34:16 +08:00