378 Commits
v0.5 ... v1.0

Author SHA1 Message Date
Mario Bălănică
253adece42 Update README.md
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-03-18 11:30:58 +02:00
Mario Bălănică
0c89a9ed32 DwcEqosSnpDxe: Return proper status when link is down
Return EFI_NO_MEDIA instead of EFI_NOT_READY to avoid the long delays at
boot.

From DxeNetLib:
> If Aip protocol is supported by low layer drivers, three kinds of
> media states can be detected: EFI_SUCCESS, EFI_NOT_READY and
> EFI_NO_MEDIA, represents connected state, connecting state and no
> media state respectively. When function detects the current state is
> EFI_NOT_READY, it will loop to wait for next time's check until state
> turns to be EFI_SUCCESS or EFI_NO_MEDIA.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-03-18 03:53:09 +02:00
Mario Bălănică
118c9c3765 Khadas/Edge2: Enable VCC_5V0_PWREN_H early
Required for HDMI DDC.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-03-17 05:20:40 +02:00
Mario Bălănică
1a8b095368 PlatformBootManagerLib: Remove stale FvFile(s) before registering boot keys
Firmware updates can invalidate existing FvFile entries. Attempting to
clean them up after registering the boot keys (e.g. ESC) often leads to
the keys not working until after a reboot - perhaps because the options
they reference no longer match?

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-03-17 03:53:32 +02:00
Mario Bălănică
519a6f744e Add network stack configuration options
This allows enabling/disabling various parts of the UEFI network stack:
- Entire stack
- IPv4 stack
- IPv6 stack
- PXE boot
- HTTP boot

All options are enabled by default.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-03-17 01:55:17 +02:00
Mario Bălănică
b959fe9020 Add Boot Discovery Policy driver
This allows controlling the boot discovery policy (Minimal, Connect
Network, Connect All).

We now default to "Connect All" because it appears that BDS does not
properly connect all child handles on some controllers, resulting in
missing partitions and ultimately the boot option being skipped. This
seems to affect SATA and NVME at least, however USB is fine.

Fixes #101

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-03-16 06:00:52 +02:00
Mario Bălănică
0cd0068fd1 Pcf8563RealTimeClockLib: Kick off time from build epoch
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-03-15 19:05:52 +02:00
Mario Bălănică
f94ee94486 Drop edk2-platforms submodule
edk2-platforms has removed pretty much all the dependencies we had on
it: Pcf8563RealTimeClockLib and the Hisilicon package. Also drop the
Ax88772c driver as it's not needed.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-03-15 17:32:39 +02:00
Mario Bălănică
69271dcf48 Update to latest EDK2
edk2-stable202502

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-03-15 17:15:32 +02:00
Mario Bălănică
f8af61cbe1 Decrease auto boot timeout to 5 seconds
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-03-15 02:17:00 +02:00
Mario Bălănică
54764b28ef Rk3588PciHostBridgeLib: Decrease link up timeout to 1 second
2 seconds seem rather excessive. Linux also waits 1 second.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-03-15 02:12:41 +02:00
Mario Bălănică
021a476686 Remove I2cDemoTest from shell
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-03-15 02:01:57 +02:00
Mario Bălănică
0e585c8a6e GOP: Add option for 90-degree rotation
Swap the reported horizontal and vertical resolutions and rotate block
transfer operations. Also set PixelFormat to PixelBltOnly as we
shouldn't claim to support a framebuffer given the fake resolution.

This approach is flawed in multiple ways: slow perf, no framebuffer in
OS (or garbled up). But it is way more convenient on the Fydetab - and
realistically it's going to be fine for Linux boot as it has a native
display driver.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-03-15 01:53:06 +02:00
Mario Bălănică
e9209cbaa6 GOP: Optimize block transfer operations
- no need for cache maintenance as the framebuffer is already non-cached
- remove handling for different bits per pixel - we only support 32 bpp
- simplify EfiBltVideoToVideo overlap case handling

The console no longer lags at high resolutions.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-03-14 19:23:56 +02:00
Mario Bălănică
bc21dd8f26 Vop2Dxe: Fix up horizontal resolution alignment
RK3588 requires HActive to be 4-pixel aligned.

This fixes modes such as 1366x768 (rounded up to 1368), which would
otherwise appear fuzzy.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-03-14 17:52:25 +02:00
Mario Bălănică
46669d1439 GOP: Add EDID support
The preferred display mode is now automatically detected by parsing the
EDID in this order:
- detailed timings from base block and CEA-861 & VTB-EXT extensions
- SVDs / HDMI VICs from CEA-861 extensions
- standard timings from base block
- established timings from base block

Only supported on HDMI for now.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-03-14 17:52:24 +02:00
Mario Bălănică
440e45ad39 GOP: Support connector detection
Display connectors are now probed in a configurable priority order, with
the first found display set as the primary output. All other connectors
remain disabled, though it's still possible to enable duplication in the
settings (all displays will be considered identical to the primary one).

If no display is found, by default, output will be forced with the
configured mode (Native - fallback to 640x480 / custom / predefined) on
all connectors. This is mainly done to allow using connectors that don't
have detection implemented yet (DP/eDP). It might also be useful to
recover from potential issues with EDID in the future - one can plug in
the display after boot and *hopefully* have it work at the fallback
resolution.
This option can also be disabled in the settings, which is recommended
when using the serial port, as some OSes don't redirect the text output
there if a GOP instance is always present.

For now, detection is supported only on HDMI and DSI (which is assumed
to be permanently connected).

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-03-14 17:52:23 +02:00
Mario Bălănică
ea8fa5b2cc DwHdmiQp: Support more display modes
DwHdmiQp:
- Follow BSP code and add retries to the I2C read/write ops, because I
have seen timeouts with one TV sink while writing SCDC registers.
- Set DVI mode correctly based on sink info (needs EDID).
- Add a configuration option to force DVI mode -- this can be useful to
trick some TVs into using PC mode: no overscan, full range RGB. We don't
currently support limited range for CEA modes, which leads to slightly
crushed black levels.
- Setup AVI & HDMI vendor infoframes.
- Set scrambling for HDMI 2.0 modes (up to 4K 60 Hz).

HdptxHdmiPhy:
- Use actual bitrate rather than a hardcoded value for 1080p60.
- Calculate PLL config to support arbitrary rates.
- Add more precise predefined PLL configs for some modes.

Vop2:
- Switch DCLK to the HDMI PHY PLL as it provides better accuracy and
enables more modes.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-03-14 17:52:23 +02:00
Mario Bălănică
60b5a4c252 GOP: Support multiple display modes
Add a configuration menu which allows changing the preferred display
mode:
- Native: uses predefined timings from panel (for DSI) or EDID (to-do)
- Custom: user can enter arbitrary timings (pixel clock, front porch,
sync width, back porch, sync polarity)
- Common predefined modes from 640x480p60 to 4096x2160p60

In case the custom display settings are invalid/unsupported, pressing
LCtrl+LShift+F6 at any time will cause a reboot with default settings.

The HDMI output will currently not work because it's still hardcoded to
1080p60 and we're now falling back to a safe 480p due to lack of EDID.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-03-14 17:52:22 +02:00
Mario Bălănică
5697f4400a Allow platforms to specify all supported display connectors
Particularly for HDMI and eDP as the other drivers could already bind to
multiple outputs.

The eDP driver is still disabled by default because it requires
EdpEnableBacklight() to be implemented in RockchipPlatformLib, but it
does appear to load fine and has been tested to work some time ago.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-03-14 17:52:21 +02:00
amazingfate
48d52ef954 Revert "OrangePi5Plus: DTS: Enable front USB-A 3.0 and USB-C ports"
This reverts commit c52b05713a.
2025-03-01 00:52:19 +02:00
amazingfate
5eb1d5b68a update mainline devicetree to tag v6.14-rc4-dts 2025-03-01 00:52:19 +02:00
Mario Bălănică
3564ae3fe5 Revert "ROCK5ITX: DTS: Enable HDMI0 output"
This reverts commit 06408b6bf6.

Turns out that HDMI0 is routed to the EDP connector and a DP->HDMI
converter is used instead for the 2nd 4K port.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-01-29 20:29:32 +02:00
Mario Bălănică
e14cb556d7 README: Document sf shell command to update SPI NOR flash
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-01-23 02:41:41 +02:00
Mario Bălănică
bdb19474c7 Set CPU clock to max on all platforms
Mainly because I've seen way too many people wondering why the cores run
at 800 MHz and being unaware of the setup option to change that. There's
throttling in place anyway, so overheating without cooling isn't that
big of a concern.

This also improves boot performance in UEFI, given that we're running on
a single A55.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-01-22 19:53:32 +02:00
Mario Bălănică
db841513a0 Add support for integrated GMAC Ethernet (EQoS)
Also fix the byte-swapped MAC addresses.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-01-22 16:57:39 +02:00
Mario Bălănică
9eb0078799 Enable iSCSI, TFTP command and unsecure HTTP boot
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-01-22 16:50:35 +02:00
Mario Bălănică
1031e5c615 Clean up global BuildOptions
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-01-20 15:51:41 +02:00
Mario Bălănică
306ff58049 Don't disable ComponentName(2) protocols
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-01-20 14:47:43 +02:00
Mario Bălănică
9bd368a3d9 Limit supported languages to en-US
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-01-20 14:43:08 +02:00
Mario Bălănică
7dedbf7d4b Uncrustify codebase
Except for U-Boot ported code which should retain its formatting.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-01-20 14:32:51 +02:00
Integral
9db65a1d02 README: Add Fedora Workstation Rawhide to tested mainline linux images (#179) 2025-01-05 17:48:18 +02:00
Mario Bălănică
dbf783223f Update README.md
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-01-05 06:01:53 +02:00
Mario Bălănică
eff37d1c6a Disable runtime EFI RTC on Linux FDT boot
Linux registers both rtc-efi and rtc-hym8563, which is obviously wrong
since they share the same hardware.

Running `timedatectl` in this case results in spurious interrupts caught
by the I2C driver, RTC time appearing to be stuck, or:
`Failed to query server: Failed to read RTC: Input/output error`

If I2C devices on a bus shared with RTC are ever exposed in ACPI, the
same approach should probably be taken. That is, disable EFI RTC and
provide a TAD device going through an I2cSerialBus connection instead.
At least on Windows, EFI RTC appears to be accessed only at boot time,
so it may not necessarily be an issue there.

Fixes #70

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-01-05 06:01:43 +02:00
Mario Bălănică
3e4234ac61 Move ACPI OS identification to its own driver
To support multiple handlers.

Also add Linux kernel image detection while I'm at it.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-01-04 14:57:03 +02:00
Mario Bălănică
8d3257255d Khadas/Edge2: DTS: Enable HDMI, USB-C, Bluetooth and analog audio
Note: Wi-Fi and Bluetooth require firmware blobs not yet upstreamed.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-01-04 01:33:36 +02:00
Mario Bălănică
06408b6bf6 ROCK5ITX: DTS: Enable HDMI0 output
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-01-01 22:55:46 +02:00
Mario Bălănică
c52b05713a OrangePi5Plus: DTS: Enable front USB-A 3.0 and USB-C ports
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2025-01-01 22:53:43 +02:00
Mario Bălănică
b7898949e7 ROCK5ITX: DTS: Remove "pcie30_refclk" gated-fixed-clock
This is to maintain compatibility with kernels older than v6.13-rc1. The
clock is backed by a GPIO regulator anyway, so simply referencing it in
vpcie3v3-supply also addresses the potential issue where pcie3x2 might
probe earlier than pcie3x4 and hang on DBI access because the clock
didn't have a chance to be enabled.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-12-30 14:13:22 +02:00
Mario Bălănică
76d4032bb0 ROCK5ITX: Add PCIE30X2 perst
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-12-29 01:39:44 +02:00
Mario Bălănică
a80e23a23e NanoPC-CM3588-NAS: Enable PCIe bifurcation and route Combo PHY 2 to USB3
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-12-28 16:31:45 +02:00
Mario Bălănică
c9563d7748 ROCK5ITX: Enable PCIe bifurcation
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-12-28 16:10:08 +02:00
Mario Bălănică
f13ca9067e Update README.md 2024-12-24 19:34:07 +02:00
Mario Bălănică
40406ca9c2 Add BuzzTV PowerStation 6 platform
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-12-24 11:12:33 +02:00
Mario Bălănică
4d6a42479a Switch console output to 100x31
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-12-23 18:41:11 +02:00
Mario Bălănică
f94929cb5f Hook recovery key to MaskROM reset
If the recovery key is held right after power on, UEFI will reset to
MaskROM.

Some platforms don't have an easily accessible MaskROM button, but they
do have a recovery key (volume up on Fydetab) that can be used for this
purpose. U-Boot proper maps it to rockusb loader mode instead, however
we don't support this protocol.

This is done early in the SEC phase to reduce the chances of something
going horribly wrong (e.g. in DXE) and preventing recovery.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-12-23 17:30:35 +02:00
Mario Bălănică
ad4ec8ea93 Decouple Rk3588CruLib from RockchipPlatformLib
I've finally been bitten by this...

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-12-23 15:33:54 +02:00
Mario Bălănică
2181afea21 Allow out-of-tree mainline DTS
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-12-22 19:01:21 +02:00
Mario Bălănică
95404828df PCIe PHY bifurcation fixes
In preparation for a platform which must be limited to x2x2 mode while
also having the dedicated 3x2 controller disabled.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-12-20 23:50:56 +02:00
Mario Bălănică
e7a6b9983d GpioLib: Fix pull down/up definitions
Bit [1]:
0b0: Pull Down
0b1: Pull Up

Bit [0]:
0b0: Pull Disable
0b1: Pull Enable

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-12-20 21:47:24 +02:00
Mario Bălănică
f92dbbec48 FdtPlatformDxe: Fix typo
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-12-19 16:19:14 +02:00
Mario Bălănică
437888c733 Improve SD/eMMC var store detection robustness
The hardware boot order on all platforms is: FSPI->EMMC->SD->USB.

U-Boot SPL (our chainloader), however, is told by its DTB to boot in
this order: SD->EMMC->FSPI. It then populates `RkAtagTypeBootDev` with
the device it decided to boot from. We use this information to determine
the drive we belong to, in order to write the variable store there.

While this behavior is useful for testing, it should generally be
avoided because it bypasses the SPL version we intended to ship with
UEFI, which could lead to all sorts of issues.

One such issue is that some SPL builds (namely Orange Pi's) flashed to
SPI will happily boot from SD card while setting the ATAG to EMMC
instead. Obviously, this leads UEFI to use the wrong device (or none at
all if EMMC is missing) for writing variables. Since SPL only reads the
variable store into memory from the actual boot device (SD card),
settings will not persist.

To address this, we'll no longer rely on that ATAG unless it indicates
FSPI boot, in which case it would most likely be correct due to FSPI
having priority in hardware - well, assuming there no further broken
SPLs in the wild that might set it to FSPI while booting from SD :P.

Instead, we'll look through the SD->EMMC devices (same order as SPL) to
find a FIT image matching our own, indicating that's likely the boot
device.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-12-19 16:16:23 +02:00
Mario Bălănică
e954d0b831 workflows/build: Sort platforms and add rock-5bplus
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-12-18 13:19:57 +02:00
Mario Bălănică
543e4d03ab workflows/build: Install uuid-dev
ubuntu-latest runner was updated to 24.04.1, which is missing this dependency.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-12-18 11:38:25 +02:00
Mario Bălănică
793457a28e Add SARADC reading library
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-12-18 11:26:10 +02:00
Mario Bălănică
3bb6db9273 Add support for mainline Linux boot with FDT
Two compatibility modes are now available in the setup menu:
- Vendor: for Rockchip SDK Linux 6.1 kernels only.
- Mainline: for upstream Linux 6.10 and newer.

Mainline is the default choice on platforms that have support for it.

Moreover, both ACPI and FDT are now exposed by default, leaving the
choice up to the OS: Linux prefers FDT, while Windows is only concerned
with ACPI. BSDs might also prefer FDT, in which case it may be necessary
to switch back to ACPI.
The reason for this change is that ACPI provides a suboptimal Linux
experience and has reached a dead end (it cannot be improved without
serious OS changes).

The only major drawback is lack of any HDMI output on kernels older than
6.13. To workaround this limitation, an option to force use of the UEFI
GOP display has been added, which is disabled by default. This option
hides all VOP-related device nodes, in order to prevent any kernel
drivers from resetting the previous hardware configuration done by UEFI.
Note that GPU acceleration, mode setting, etc. will not work in this
mode.

Platforms with mainline support:
- Ameridroid Indiedroid Nova
- FriendlyElec NanoPC-CM3588-NAS
- FriendlyElec NanoPC-T6
- FriendlyElec NanoPi-R6C
- FriendlyElec NanoPi-R6S
- Khadas Edge2
- Orange Pi 5
- Orange Pi 5 Plus
- Radxa ROCK 5A
- Radxa ROCK 5B
- Radxa ROCK 5 ITX

Tested distros:
- Ubuntu 24.10 (kernel 6.11)
- Fedora Workstation 41 (kernels 6.11 and 6.13-rc2)

Tested platforms:
- ROCK 5B
- Orange Pi 5 Plus

Kernel support status:
https://gitlab.collabora.com/hardware-enablement/rockchip-3588/notes-for-rockchip-3588/-/blob/main/mainline-status.md

Imported submodule devicetree-rebasing from tag v6.13-rc3-dts.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-12-17 20:09:51 +02:00
Mario Bălănică
61fdb612d6 Add reset to MaskROM boot option
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-12-07 21:33:29 +02:00
Mario Bălănică
d6e003b778 Switch to upstream ResetSystemLib
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-12-07 20:21:06 +02:00
Mario Bălănică
7ddd7d7c0c Remove ArmPlatformLib MPCore boilerplate
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-12-05 15:40:53 +02:00
Mario Bălănică
685d444657 Update to latest rkbin
* ATF (BL31) from v1.45 to v1.47
* OP-TEE (BL32) from v1.15 to v1.17
* ddrbin from v1.16 to v1.18

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-12-05 14:52:19 +02:00
Mario Bălănică
ec03363023 Update to latest arm-trusted-firmware
Rebased onto v2.12.0. No functional changes.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-12-05 14:31:44 +02:00
Mario Bălănică
ada8ce2cb1 Add upstream EFI Memory Attribute Protocol state manager
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-12-05 13:30:33 +02:00
LokiSharp
41af90239e Add NanoPi M6 (#164) 2024-12-05 11:13:43 +02:00
jneem
53236151ca CM3588-nas support (#163)
Co-authored-by: Joshua Navarro <navarro967@gmail.com>
2024-12-05 11:07:29 +02:00
Marcin Juszkiewicz
c2d3801cfa FriendlyELEC/NanoPC-T6: enable USB 2.0 on LTS board (#156)
NanoPC-T6 LTS has different USB configuration. There is no minipcie
slot, two usb 2.0 ports are accessible from outside and another two on
internal header.

To have it working we need to enable USB20_HOST_PWREN line.

Closes: #153

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
2024-12-05 11:02:11 +02:00
Mario Bălănică
78226d8bae Update to latest EDK2
edk2-stable202411

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-12-05 10:56:43 +02:00
Sophon
d6682281e0 Merge pull request #161 from sanderhollaar/doc/update-debian-install-packages 2024-10-05 22:39:42 +08:00
sander
8dde0b1501 fix: Note, selecting 'acpica-tools' instead of 'iasl' 2024-09-25 12:56:45 +02:00
Sander Hollaar
c650ed694f doc: update Install required packages for Debian
In Debian Trixie this fixes: `/bin/sh: 1: python: not found` and `sh: 1: dtc: not found`
2024-09-24 20:00:53 +02:00
Matthias Schreiner
e7c4ff5b6a Revert "Fydetab Duo: fixes for SDcard"
With current change, SD card no longer appears in UEFI Boot Manager. Looking at commit history, the problem is already described and workaround:
c02b333c22 (same as current change: bad)
416b2fa11b (actual solution)

The Fydetab Duo motherboard has SDMMC_DET inverted, which is against Rockchip design. This is a hardware mistake that prevents the RK3588 MaskROM to boot from SD card when tray is fully closed. No software fix is possible because MaskROM is read-only. Therefore, in order to boot UEFI firmware and OS from SD card, the tray has to be left ajar and UEFI firmware must not invert the state once again.

This allows UEFI firmware to detect the SD card no matter if tray is fully in or partially.
2024-09-09 22:46:25 +08:00
Panda 潘达
e98af137c4 feat: 6.1 DTB + fixes for SDcard on the Fydetab Duo
Co-authored-by: Yang Tsao <yang@fydeos.io>
2024-09-09 15:49:28 +08:00
dixyes
47b54dd645 Add rock-5bplus support 2024-08-19 17:08:44 +08:00
dixyes
1782be77b3 Add rock-5b-plus dtb 2024-08-19 17:08:44 +08:00
Yun Dou
6f478fc994 Format edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/PciExpress30.c
Co-authored-by: Molly Sophia <mollysophia379@gmail.com>
2024-08-19 17:08:20 +08:00
dixyes
706a9da509 Support bifurcation in ACPI and FDT
Signed-off-by: dixyes <dixyes@gmail.com>
2024-08-19 17:08:20 +08:00
dixyes
5095fb4658 Add pcie bufurcation options in dxe
Signed-off-by: dixyes <dixyes@gmail.com>
2024-08-19 17:08:20 +08:00
dixyes
c7d90e42d7 Remove tabs in file
Signed-off-by: dixyes <dixyes@gmail.com>
2024-08-19 17:08:20 +08:00
Mario Bălănică
0d37e7250e ACPI: Add broken-cd property for SDMMC
Missed this change. The Windows driver needs to be made aware that the
internal card detect register cannot be trusted. But card detection
still works there, because sdport keeps track of the state based on the
GPIO interrupt.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-07-11 04:03:19 +03:00
Mario Bălănică
416b2fa11b FydetabDuo: Disable SD card detection
There's a trick to boot from SD on this tablet: the card tray has to be
opened slightly, just enough so that the card detect pin is released
while the card itself still makes contact with the data pins.

Given that both states can mean "connected", UEFI should no longer
rely on this signal to detect card presence.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-07-10 20:18:00 +03:00
Mario Bălănică
915093ff4b FydetabDuo: Disable UHS-I speed modes for SDMMC in ACPI
Windows may fail to load with UNMOUNTABLE_BOOT_DEVICE otherwise. I was
able to boot *mostly* fine until today, but now it crashes constantly.

It appears there are some signal integrity issues at SDR50/104, no
matter the clock rate (tried lowering it to 150, 100 and 50 MHz).
Tuning seems to complete okay, but after a CMD18 it starts going haywire
with Data/Command CRC errors and can't recover.

Tested again on an Indiedroid Nova and the issue does not reproduce.

So unfortunately we have to limit the speed here to HS 25 MB/s.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-07-10 19:41:15 +03:00
Mario Bălănică
19360cf5b2 Update README.md
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-07-09 05:50:16 +03:00
Mario Bălănică
066de1179b FydetabDuo: Add display support
The panel is a 1600x2560 CSOT PNC357DB1-4.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-07-09 05:22:31 +03:00
Mario Bălănică
9797896a6d Add MIPI DSI support
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-07-09 05:22:30 +03:00
Mario Bălănică
f8768a8a02 Add initial support for Fydetab Duo
The DSI panel is not yet working.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-07-09 05:22:29 +03:00
Mario Bălănică
c02b333c22 RkSdmmcDxe: Add option for inverted card detect signal
It's worth noting that when the detection logic is inverted,
the boot ROM assumes the SD card is disconnected and skips
booting from it altogether.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-07-09 05:22:29 +03:00
Mario Bălănică
1b6ef19bf3 RkSdmmcPlatformLib: Ensure JTAG is disabled
If the card is not connected at boot, force_jtag in
SYS_GRF_SOC_CON6 may remain set. This muxes DAT2/DAT3 over
to JTAG instead of SDMMC, preventing SD card operation in
4-bit mode.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-07-09 05:22:24 +03:00
Mario Bălănică
0bfa31ff0e Update README.md
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-06-24 03:32:36 +03:00
Mario Bălănică
83e1b9bbea rkbin: Downgrade SPL back to v1.12
SD card driver in v1.13 throws errors and won't boot anymore.
Tested on Indiedroid Nova.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-06-24 00:16:36 +03:00
Mario Bălănică
9678f643ec Update to latest rkbin
* ATF (BL31) from v1.40 to v1.45
* OP-TEE (BL32) from v1.13 to v1.15
* ddrbin from v1.12 to v1.16
* U-Boot SPL from v1.12 to v1.13

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-06-24 00:02:48 +03:00
Mario Bălănică
359354e0bb Enable Arm TRNG service
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-06-23 22:49:05 +03:00
Mario Bălănică
8e7e736365 Update TF-A submodule
Adds support for TRNG SMC service.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-06-23 22:46:44 +03:00
Mario Bălănică
1bb15338fc Fix networking after EDK2 update
Latest EDK2 requires a proper RNG driver in order to use network boot
(CVE-2023-45237).

We ought to implement one, but for now bypass this check.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-06-23 04:01:20 +03:00
Mario Bălănică
f0727b8e35 Update to latest EDK2
edk2-stable202405

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-06-23 01:33:00 +03:00
Mario Bălănică
02d150251c DwcSdhciDxe: Disable ADMA2 to avoid data corruption
This controller has the limitation that a single ADMA2 descriptor cannot
cross 128 MB boundaries and must be split.
This would require a patch in SdMmcPciHcDxe, but SDMA works fine for the
time being.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-06-22 20:10:08 +03:00
Mario Bălănică
053cf714a7 ACPI: Prepare SD controller support for Windows
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-06-18 21:17:17 +03:00
Mario Bălănică
dd0b22f5fd ACPI: Add SCMI clock and voltage domain methods
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-06-18 20:59:23 +03:00
Mario Bălănică
bffaee6af4 Update TF-A submodule
This enables the upcoming SCMI support in ACPI and SD/MMC clock &
voltage control for Windows.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-06-18 19:49:41 +03:00
Mario Bălănică
de6b6f843e Switch to open-source TF-A
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-06-18 19:34:52 +03:00
Mario Bălănică
ee52a5a8ce PlatformLib: Fix overlapping memory map regions
Regions should be clearly delimited so attributes don't mix up.

Also ensure that the TF-A region containing SCMI shared memory is not
added to the UEFI map. This addresses an issue where attributes seem to
change at runtime and the mismatch leads to a loss of cache coherency
between EL3 and lower level accesses.

TF-A maps the shared memory as Device memory, so it needs to remain at
least non-cacheable here too (Device is not exactly possible due to
unaligned accesses from ArmScmiDxe). This could actually just be normal
write-back memory, since it's not shared with any external clients, but
whatever.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-06-18 19:34:51 +03:00
Mario Bălănică
1b9a49f624 RK3588Dxe: Enable M.2 slot power in SATA mode
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-06-18 19:29:56 +03:00
Mario Bălănică
b1c1c2cd13 SdramLib: Fix detection for LPDDR4X and LPDDR5
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-06-18 19:29:48 +03:00
Jianfeng Liu
1fa01b9ea1 Add support for rock-5-itx (#138) 2024-04-25 21:15:54 +03:00
silime
a39e76ff86 Platform/ROCK5B: Enable WIFI Bluetooth regulator (#134) 2024-04-05 17:38:12 +03:00
Ricardo Pardini
956bbdc73b update DTBs from Armbian rk-6.1-rkr1 (#133)
Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
2024-04-01 17:29:13 +03:00
Doug Cook
94a242cf05 New platform: AIO-3588q (#130) 2024-03-26 23:50:10 +02:00
Mario Bălănică
779b6dc5bc workflows: Update actions 2024-03-16 22:42:39 +02:00
Mario Bălănică
06a6d8843f Clean-up build.sh
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-03-16 22:42:25 +02:00
Mario Bălănică
3e5a3c8c06 ACPI: Unconditionally mask off PCIe native hot plug control
We don't actually support hot plug and this causes lockups in Windows.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-03-02 00:01:00 +02:00
Mario Bălănică
ba8fbeea98 Rk3588PciHostBridgeLib: Try to avoid a potential bus hang up
Some devices that appear to have working CFG0 filtering (my VIA VL805)
do not actually like config cycles at B/D/F 01:01.0 and may screw up
further accesses (e.g. read 0xFFFFFFFF at valid locations) + eventually
hang up the bus after a few more attempts.

Checking for mirroring in this case is asking for trouble, but it seems
that trying 01:01.0 first and then 01:00.0 avoids the problem in UEFI.

OSes that rely on single device ECAM mode in ACPI are still going to
hang up the system, since they scan the entire affected bus.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-02-13 01:53:04 +02:00
Mario Bălănică
4b915e69f5 ACPI: Support PCIe root port and switches in Windows and Linux
To deal with the broken ECAM on this platform, reuse some existing OS
workarounds:
- for Windows: "NXPMX6" OEM ID in FADT and split MCFG entries for root
port and main config space.

- for Linux: "AMAZON" OEM ID + "GRAVITON" OEM Table ID in MCFG. An
"AMZN0001" device with _UID matching the RC segment number returns the
root port's DBI address in _CRS.

Both workarounds filter device > 0 on primary and secondary buses of RP
to hide ghost and duplicate devices.

The compatibility mode used can be configured in the setup menu.
Default is "Auto (NXPMX6 + Single Device)", which selects the NXPMX6
mode when Windows is booted and the classic single device/bus mode for
other OSes, since it's the most compatible one.

Also move the PCIe and SATA SSDT definitions in DSDT and patch _STA
instead to disable the unnecessary controllers.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-02-11 21:48:46 +02:00
Mario Bălănică
ccf967ed7a ACPI: Expose EHCI unconditionally
But detect the OS booted and hide the PNP0D20 ID for Windows, so we
don't end up binding to the inbox driver package and crashing.

The fixed driver package[^1] will bind to the custom RKCP0D20 _HID
instead.

[^1]: https://github.com/worproject/Rockchip-Windows-Drivers/tree/master/drivers/usb/usbehci_noncoherent

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-02-11 21:48:44 +02:00
Mario Bălănică
4684b3ad73 ACPI: Set MSI not supported flag in FADT
This stops Linux from attempting to enable MSI and ultimately failing.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-02-11 21:48:42 +02:00
Mario Bălănică
0b69d04421 ACPI: Remove "rockchip,rk3399-i2c" compatible
Linux does not like the DT properties and kernel panics.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-02-11 21:48:36 +02:00
Mario Bălănică
4af3a03c11 Drop dependency on string.h
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-01-19 20:39:23 +02:00
Mario Bălănică
21c4983009 ACPI: Support I2S master clock adjustment via _DSM
Mux the TX clock source accordingly and initialize MCLK at 256 * 48000Hz
to fix playback speed in Windows.

RX is not configured yet.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-01-19 04:19:17 +02:00
Mario Bălănică
2124a8c3de CruLib: Assorted improvements
Lay groundwork to support:
- clocks from other CRU instances (e.g. PMU1CRU).
- gating and reset. Resets are separate due to them controlling not only
clocks but also peripheral blocks.

Also:
- validate input parameters
- fix PMU1CRU definitions

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-01-19 04:19:16 +02:00
Mario Bălănică
4209774c09 RK3588Dxe: Clean up unused code
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-01-19 04:19:16 +02:00
Mario Bălănică
1598d883be Platform/OPi5: Fix i2c0m2
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-01-19 04:19:15 +02:00
Mario Bălănică
cc77cee865 Platform/Mekotronics: Fix i2c0_sda_m2
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-01-13 05:56:50 +02:00
CoolStar
e452f9d179 Platform/RK3588: Enable I2S and codec depending on board (#114) 2024-01-12 03:22:26 +02:00
Mario Bălănică
72385b183a PlatformBootManagerLib: Add USB keyboard path to ConIn earlier
When a keyboard gets installed after connecting the USB controller
handles, ConPlatformDxe will check that its short-form device path
exists in the ConIn variable before enabling input from it.

This variable is missing at first boot, so adding the path after the
keyboard was already ignored means it won't be usable during BDS
countdown.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-01-11 06:01:33 +02:00
Mario Bălănică
bc0a1bc833 Silicon/RK3588: Add option to change serial baud rate within UEFI
Firstly, split up the Dw8250 serial lib into "full" and "debug"
versions. The full version is only used at SEC phase (PrePi) for setting
the specified baud rate, while the debug one is used everywhere else and
cannot reinitialize the UART.

To read the baud rate NV variable in SEC, introduce BaseVariableLib,
which is just a slightly modified FaultTolerantWritePei + VariablePei to
not use HOBs and PPIs, since they're not available this early.

Previous boot stages (DDR, TF-A, U-Boot SPL) are still hardcoded to
output at 1.5 Mbaud.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-01-10 03:00:05 +02:00
Mario Bălănică
a7806a34ac Silicon/Rockchip: Fork Dw8250SerialPortLib
Before I do anything to it..

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-01-10 03:00:05 +02:00
Mario Bălănică
601a81a813 Silicon/RK3588: Remove own NvStorage PCDs
Use gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorage* everywhere for
consistency.

This also fixes FTW, since its PCDs were previously set to wrong
addresses in the DSC.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-01-10 02:59:59 +02:00
Molly Sophia
526d9e9a7b GpioLib: Fix dead loops
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2024-01-08 04:50:46 +00:00
CoolStar
0da51416c7 Platform/RK3588: Refactor I2cIoMux to use GpioPinSetFunction and add missing controllers (#113) 2024-01-06 01:35:05 +02:00
root
5974d88a1e Platform/OPi5Plus: Enable Wi-Fi regulator 2024-01-04 19:56:24 +02:00
SleepWalker
cf562625e5 Platform/NanoPC-T6: Power on 4G/LTE module and fix logo (#111) 2024-01-04 19:12:34 +02:00
Mario Bălănică
22d22a4338 Silicon/RK3588: Add _DSM for setting GMAC RGMII speed
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
2024-01-03 23:02:30 +02:00
Doug Cook
dc1d255855 GMAC - add hardware IDs for use by Windows
Set GMAC HID to RKCP6543 (arbitrarily-chosen, open to alternatives).

Move the PRP0001 id to `_CID`.
2023-12-22 09:11:49 +08:00
shimmyshai00
a6c7ca1fef Platform/RK3588: Add Firefly ITX-3588J board support (#109) 2023-12-17 12:01:16 +02:00
CoolStar
05bc33baee Silicon/RK3588: Adjust I2C for Windows driver, add DMA, and enable in boards 2023-12-08 20:42:18 +08:00
CoolStar
83fe40896f Silicon/RK3588: Adjust GPIO for Windows driver and enable in boards (#106) 2023-12-02 17:49:46 +02:00
Doug Cook
9529bc4902 Silicon/RK3588: Fix inconsistent Base System RAM length (#104)
The Base System RAM  section nominally starts at `mSystemMemoryBase` but
computes its length as if it starts at `0`. This happens to be fine
since `mSystemMemoryBase` actually is `0`, so this doesn't cause any
real problems, but it seems inconsistent to use a symbol in one place
and an implicitly-hard-coded `0` elsewhere.

Fix is to use subtract the value of `mSystemMemoryBase` from the length.
Since `mSystemMemoryBase` is `0`, this is a no-op, but it makes the
table use consistent logic, and might avoid a future issue if this code
is ever copy-pasted somewhere that base is not 0.
2023-11-24 01:02:51 +02:00
Doug Cook
66d22455ef Silicon/RK3588: Fix COMBO_PHY_MODE_SATA typo (#103)
Not sure that it matters, but there is an apparent typo in the value
given to PIPE_PHY_GRF_PIPE_CON3 for COMBO_PHY_MODE_SATA. The '4' is
probably off by one digit.

Reset value is 0x0002.

Existing SATA-mode value is 0x0407 (pipe_sel=PCIe):

- `0` = qsgm=0, pipe_sel=**00 (PCIe)**, reserved=0.
- `4` = clkreq=0, rxelecidle=**1**, clk_ref_src=00.
- `0` = reserved=0000.
- `7` = txpattern_sata=0, txmargin=1, txdeemph=1, txswing=1.

Likely intended value is 0x4007 (pipe_sel=SATA):

- `4` = qsgm=0, pipe_sel=**10 (SATA)**, reserved=0.
- `0` = clkreq=0, rxelecidle=**0**, clk_ref_src=00.
- `0` = reserved=0000.
- `7` = txpattern_sata=0, txmargin=1, txdeemph=1, txswing=1.
2023-11-24 00:54:32 +02:00
Molly Sophia
e3a793c89b DwHdmiQp: Add initial support for DwHdmi I2CM
...and dump the EDID

Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-11-21 11:08:51 +00:00
Molly Sophia
e9f0d3363e build.sh: Do not use cross_compile on aarch64 system
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-11-07 01:52:58 +00:00
Mario Bălănică
98e1008599 Silicon/RK3588: Fix MCFG when CFG0 TLPs are being correctly filtered
Some devices (either single or multi-function) manage to appear only once, so we
must expose the original ECAM base in this case, starting from dev 0.
2023-10-12 02:57:41 +03:00
Mario Bălănică
105f7b9fc9 Silicon/Rockchip: PWMLib: Insert delay after locking previous period & duty
Otherwise the new values would sometimes be ignored.
2023-10-07 23:04:01 +03:00
Mario Bălănică
8b6b3a6242 Add basic Secure Boot support 2023-10-06 22:30:49 +03:00
Mario Bălănică
f1ca49412c Use latest GCC instead of GCC5
"build: : warning: Toolchain GCC5 is deprecated and will be removed before the
edk2-stable202402 release. You should use 'GCCNOLTO' instead of 'GCC49', and
'GCC' instead of 'GCC5'"
2023-10-06 17:30:14 +03:00
Mario Bălănică
8921a37b17 Update to latest rkbin
* ATF (BL31) to v1.40
  * ddrbin to v1.12
2023-10-06 16:54:37 +03:00
Mario Bălănică
c2bb0235c5 Silicon/RK3588: Move ACPI code to its own platform driver 2023-10-06 15:15:48 +03:00
Mario Bălănică
9b56a310f1 Add Device Tree support
The included DTBs correspond to:
  * <a8384552a2/arch/arm64/boot/dts/rockchip>
  * roc-rk3588s-pc: <b8646da212/arch/arm64/boot/dts/rockchip>

See README for more details.
2023-10-06 14:18:04 +03:00
Mario Bălănică
6175a503df Update README.md 2023-09-19 04:37:43 +03:00
Mario Bălănică
f6b305c705 Add RTL MAC address programming guide to README
Thanks to @strygin
2023-09-19 04:01:52 +03:00
Mario Bălănică
06dcc238c6 Remove references to RPi and Arm Juno 2023-09-18 05:02:02 +03:00
Mario Bălănică
842db13abd Silicon/RK3588: Uninstall EFI_MEMORY_ATTRIBUTE_PROTOCOL
Older versions of rhboot's shim use this protocol incorrectly and lead to a
Synchronous Exception.

Many distros haven't updated yet, so uninstall the protocol as a workaround for
the time being.

See:
  - https://github.com/microsoft/mu_silicon_arm_tiano/issues/124
  - https://edk2.groups.io/g/devel/topic/99631663
2023-09-18 04:14:27 +03:00
Mario Bălănică
031633ddfc Update README.md 2023-09-16 22:25:35 +03:00
Mario Bălănică
1ae9c5f1c5 Update to latest EDK2
edk2-stable202308
2023-09-15 01:57:16 +03:00
Mario Bălănică
7a0363351f Silicon/Rockchip: I2cDxe: Connect all controller handles at end of Dxe
Only the first handle was connected.
2023-09-15 01:06:44 +03:00
Mario Bălănică
8b616fe787 Silicon/RK3588: Set default fan speed to 50% 2023-09-14 04:50:29 +03:00
Mario Bălănică
3154f1454a Add fan control for more platforms
- Indiedroid Nova (GPIO4_B4)
- ROC-RK3588S-PC / Station M3 (fan header)
- Blade 3 (fan header)
- Orange Pi 5 (GPIO4_B2)
- Orange Pi 5 Plus (fan header)
- ROCK 5B (fan header)
2023-09-14 04:42:46 +03:00
Mario Bălănică
1a9dc8252d Platform/Khadas: Add MCU driver for fan control 2023-09-13 04:38:10 +03:00
Mario Bălănică
e50878b95a Silicon/Rockchip: Add RAM disk support 2023-09-12 04:15:58 +03:00
Mario Bălănică
34f9e1860f Silicon/Rockchip: StatusLedDxe: Fix BlinkLedSync() 2023-09-12 03:42:45 +03:00
Mario Bălănică
e1fc17f6f1 Add basic status LED support
During DXE phase, the LED will pulse repeatedly. If this keeps going on forever
or the LED freezes, something went terribly wrong.

After the console is ready, at BDS phase, the LED will switch to a calm short
pulsing every two seconds or so. This indicates the firmware is alive and
waiting for user input or the countdown to boot automatically. If the blinking
stops, it can either mean that the firmware has exited the boot services and
handed off control to the OS (most likely), or that it's not responding. Brief
freezes are expected with some peripherals due to how device drivers use the
timer.

I had initially planned on blinking the LED at ExitBootServices() too, but the
delay added to the boot process doesn't seem justified.

Long pulses >= 2 are reserved for future error code reporting.

Enabled on all platforms that have a controllable LED.
2023-09-12 03:37:15 +03:00
Mario Bălănică
55f9943b00 Silicon/RK3588: GpioLib: Log direction and value set, adjust verbosity 2023-09-10 22:28:08 +03:00
Mario Bălănică
5833bde557 Silicon/Rockchip: Vop2Dxe: Fix info debug message level 2023-09-06 02:44:11 +03:00
Mario Bălănică
7505423178 Silicon/RK3588: Set VP2 pixel clock using CruLib
Custom video modes are now working on DisplayPort, but not on HDMI yet as the
driver uses hardcoded timings for 1080p 60Hz.

Once that's fixed, we can look into adding a setup option for the display mode
and even handle EDID.
2023-09-06 02:37:21 +03:00
Mario Bălănică
a36bf868d1 Silicon/RK3588: CruLib: Support (almost) arbitrary PLL rates 2023-09-06 01:17:06 +03:00
Mario Bălănică
cdf1a5ed02 Silicon/Rockchip: Add initial DisplayPort support
DwDpLib was ported from U-Boot downstream commit
549d42b6f4d1b261c433c0942868fd6e1b38aaaf.

It has been globally enabled on all RK3588 platforms where DP lanes are exposed.

Output mode is fixed by GOP at 1080p 60Hz - no EDID and HPD implemented yet.

Only works in one orientation of the Type-C connector.

Tested on:
  - R58-Mini (USB-C)
  - Indiedroid Nova (USB-C)
  - ROCK 5A (onboard HDMI -> DP converter)
2023-09-03 07:05:38 +03:00
Mario Bălănică
73bdaca713 Silicon/Rockchip: GOP: Support multiple mode setting
More changes are required in Vop2Dxe and DwHdmiQpLib.
2023-09-03 04:34:35 +03:00
Mario Bălănică
4415c8ae93 Silicon/Rockchip: GOP: Support multiple connectors
...on a single CRTC / framebuffer.
2023-09-03 04:22:15 +03:00
Mario Bălănică
8df3fc2c3f Silicon/RK3588: UsbDpPhyDxe: Add DisplayPort configuration support 2023-09-03 03:54:50 +03:00
Mario Bălănică
d56ea77d77 Silicon/RK3588: UsbDpPhyDxe: Set lane flip state when both USB and DP are exposed 2023-08-30 20:13:48 +03:00
Mario Bălănică
5bc1517de4 Silicon/RK3588: Fix GMAC ACPI _UID conflict
Make Windows happy again.
2023-08-30 03:45:55 +03:00
Mario Bălănică
f187fa7237 Silicon/Rockchip: DWC3: Disable SS instances in park mode
No, I did not notice any issues, but Rockchip have enabled this quirk in their
kernel, so let's do the same.

Apparently, on some implementations of DWC3 the controller would halt under high
load and never come back online.
2023-08-30 03:23:44 +03:00
Mario Bălănică
dbaeeacd38 Remove simple-init dependency
It was disabled by default and can't really be used due to a Synchronous Exception.
2023-08-27 22:11:54 +03:00
Mario Bălănică
e8a04487d3 Silicon/RK3588: Fix uninitialized handle in RK3588Dxe
This would point to invalid memory when the AcpiUsb2State setting was enabled,
preventing gRockchipPlatformConfigAppliedProtocolGuid from getting installed.
2023-08-26 01:25:46 +03:00
jfliu
e94e810c9d add devicetree name of board in smbios OEM Strings 2023-08-25 18:30:58 +03:00
jfliu
d4c97c6eb6 remove unused second IDBlock in flash 2023-08-25 17:02:07 +03:00
Mario Bălănică
4dbfc37a6b Platform/OrangePi5: Revert USB-C VBUS disable
Pushed accidentally.
2023-08-23 00:02:21 +03:00
Mario Bălănică
53b8299232 Silicon/RK3588: GmacPlatformDxe: Add missing break in switch statement 2023-08-22 23:58:20 +03:00
Mario Bălănică
ed76800bdf Initialize GMAC and expose in ACPI
Enabled on all platforms that use it.

Tested to be working with NetBSD on:
- R58X & R58-Mini
- Orange Pi 5
- ROCK 5A
- ROC-RK3588S-PC / Station M3

VMware ESXi also detects the NICs and link status, however it's not able to get
an IP address.

The original GMAC0 definition by Rockchip was more thorough, but I have no idea
if all the methods have been tested and with what kernel, so for now we'll keep
it minimal like on Quartz64.

This will only work when connected to a Gigabit capable port, lower speed modes
are not supported due to lack of clock management in the OS.
2023-08-22 23:52:52 +03:00
Mario Bălănică
d2ed387cc5 Silicon/RK3588: Fix PPTT A76 L2 cache reference 2023-08-20 14:32:56 +03:00
Mario Bălănică
d8039ee7fb Silicon/Rockchip: RkSdmmcDxe: Set base clock rate
If a card was plugged in after boot, it wouldn't respond.
Turns out we need to increase the base clock from the default 400 KHz. Set it to
52 MHz like the earlier stages do when a card is present at boot.

Weirdly enough this arised only after I globally enabled the DEBUG_INFO logging
level.
2023-08-20 03:30:17 +03:00
Mario Bălănică
05daac0d50 Silicon/Rockchip Fix flag clearing in DEBUG_PRINT_ERROR_LEVEL_NO_INFO 2023-08-20 02:38:05 +03:00
Mario Bălănică
4e02eb69e5 Silicon/Rockchip: Adjust logging verbosity
- Release builds are now free of any logging, to keep the serial console clean
and avoid bottlenecking the boot process.

- Debug builds are a bit more verbose.
2023-08-20 01:07:07 +03:00
Mario Bălănică
d6d9df82fb Logging fixes
- Replace EFI_D_* with DEBUG_*
- Fix informational messages that were logged as errors or warnings.
2023-08-20 00:32:07 +03:00
Mario Bălănică
e540f36293 Configure SDMMC I/O muxes 2023-08-19 19:39:08 +03:00
Mario Bălănică
5a6bb8a0e5 Silicon/Synopsys: DwMmcHcDxe: Initialize the slot even if no card is present at driver binding start
Otherwise we can't plug in an SD card after boot.
2023-08-19 19:20:12 +03:00
Mario Bălănică
937e90447b RockchipPlatformLib: Rename DwEmmcDxeIoMux & SdhciEmmcIoMux 2023-08-19 17:50:31 +03:00
Mario Bălănică
ce653aeaca Platform/OrangePi5: Do not override eMMC and FSPI pin muxing
This way we can also support the 5B wihich has an eMMC instead of SPI NOR.
2023-08-19 17:30:51 +03:00
Mario Bălănică
bf0ba70cb5 Silicon/RK3588: PPTT package has a valid AcpiProcessorId 2023-08-19 17:12:29 +03:00
Mario Bălănică
0be33750a4 Describe CPU topology in ACPI 2023-08-19 16:29:49 +03:00
Mario Bălănică
e3b055025d Silicon/RK3588: Fix HII form ID conflict 2023-08-19 03:53:34 +03:00
Mario Bălănică
0b23d9913b Platform/OrangePi5Plus: Expose the correct XHCI controller in ACPI 2023-08-19 03:44:56 +03:00
Mario Bălănică
2ffd0b3e59 Configure USB/DP PHY for all platforms
Only tested on:
 - ROCK 5B
 - Orange Pi 5 Plus
 - Indiedroid Nova
 - Edge2
 - R58X
2023-08-19 03:32:10 +03:00
Mario Bălănică
da6271594a Silicon/RK3588: Add early USB/DP PHY support
UsbDpPhyDxe was ported from U-Boot upstream commit
7b57ca18f8a3a88216b69cd295e1eed2b0c6c1be.

It currently lacks:
- proper DisplayPort PHY bring-up
- lane orientation flip binding, exposed via a protocol to the TCPM driver

USB 3 works mostly okay, but it's not as reliable as through the USB/SATA/PCIe
Combo PHY. My RTL8156B NIC for instance fails with tons of transaction errors
from the XHCI driver. This does not occur when the device is plugged into a hub.
The same behavior can be observed with Rockchip's legacy kernel booted via
U-Boot, so at least the issue is not limited to UEFI.

Thus, we introduce some config options to allow disabling SuperSpeed.

Oh, XhciDxe also doesn't cope too well with flaky USB-C connectors, it may hang
for a good while (sometimes indefinitely) retrying transfers when there isn't a
good connection.
2023-08-19 03:32:05 +03:00
Molly Sophia
5bfd4808de Platform/ROCK-5B: Enable fan control
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-08-13 23:02:52 +08:00
Molly Sophia
9ec8f97ebd Add support for fan controlling in settings
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-08-13 22:53:38 +08:00
Skr-niao
a46a675cb9 Platform/ROCK-5B: Enable fan pwm at 40kHz, 60% duty 2023-08-13 15:56:17 +08:00
Molly Sophia
e8632850d3 Platform/ROCK-5A: Enable fan pwm at 1kHz, 50% duty
Hardcoded for now

Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-08-12 12:17:53 +08:00
Molly Sophia
343be283d4 README.md: Update support status
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-08-12 12:12:35 +08:00
Molly Sophia
08407f5703 RK3588/PWMLib: Fix Duty/Period cycle setting
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-08-12 12:06:35 +08:00
Molly Sophia
ae3932ee0b RK3588/GpioLib: Fix an mistake in IOMUX addr calculation
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-08-12 10:56:16 +08:00
Molly Sophia
444ac8109b misc/rk3588_spi_nor_gpt: Fix GPT table
Make the last_lba value in GPT header smaller at 16M, so that after
flashing into mmc/sd devices, fdisk doesn't get confused.

Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-08-11 13:09:59 +08:00
Mario Bălănică
d999a44a38 Expose USB EHCI + OHCI controllers in ACPI
- EHCI is exposed conditionally (via a user setting) and disabled by default due to Windows compatibility issues.
- OHCI is exposed at all times. Windows on Arm does not have a driver for it.
2023-08-05 23:37:47 +03:00
Mario Bălănică
e76211191e Fix platform DSC macros used in byte array PCDs
Forgot to enclose them in $( ).

Also, decimal values used to work fine until I switched to macros, then they suddenly started to read back as zero.
2023-08-05 06:06:38 +03:00
Mario Bălănică
7d3a9ec3b5 Platforms: Configure runtime support for I2C buses 2023-08-05 04:32:24 +03:00
Mario Bălănică
9ec1e446c5 Silicon/Rockchip: I2cDxe: Add runtime support 2023-08-05 04:24:50 +03:00
Mario Bălănică
4b862edfc2 Platform/R58X: Disable HS400 for eMMC
Work around issue #54
2023-08-03 21:49:49 +03:00
Mario Bălănică
6f41ec8eb7 Silicon/Rockchip: Add HS400 disable flag for SDHCI 2023-08-03 21:47:35 +03:00
Mario Bălănică
4584499270 Silicon/Rockchip: Add 0xd6 (Foresee) eMMC MID to boot description list 2023-08-03 05:39:51 +03:00
Mario Bălănică
4ac45a4a74 Silicon/Rockchip: Add 0x9B (YMTC) eMMC MID to boot description list 2023-08-03 05:27:45 +03:00
Mario Bălănică
51f33c10b7 Platforms: Enable HYM8563 RTC support
Enabled on all platforms, except for:
 - Radxa ROCK 5A: I2C location unknown yet
 - Mixtile Blade 3: no RTC present

Not tested on Hinlink and FriendlyElec devices.
2023-08-03 03:04:49 +03:00
Mario Bălănică
9ec4c35553 Move some I2C PCD definitions to platform DSC and delete unused ones
Even though regulator setup is the same on all platforms, other I2C devices are placed on different busses.
2023-08-03 02:33:53 +03:00
Mario Bălănică
1ca239fba8 Silicon/Rockchip: Add 8563-based RTC support
Uses Pcf8563RealTimeClockLib, which is compatible with the HYM8563 chip used on many Rockchip platforms.
2023-08-02 05:11:27 +03:00
Mario Bălănică
a5fdc7c793 Silicon/Rockchip: I2cDxe: Implement SetBusFrequency stub 2023-08-02 05:11:27 +03:00
Mario Bălănică
4b015d357b Silicon/Rockchip: I2cDxe: Don't initialize a bus more than once 2023-08-02 05:11:26 +03:00
Mario Bălănică
c0bd3af135 Silicon/Rockchip: Introduce RockchipI2cMasterProtocol
We need a way to get the platform I2C bus number associated with the master protocol, so drivers that consume it directly (like RTC) can be provided with the appropriate controller handle.

RTC drivers don't follow the higher-level I2C I/O model as it doesn't support runtime use.
2023-08-02 05:11:26 +03:00
Mario Bălănică
30423e8d6f Silicon/RK3588: Fix I2C_BASE macro 2023-08-02 05:11:26 +03:00
Molly Sophia
9439ee8f03 Platform/NanoPi-R6C: Fix compilation
Gmac.asl doesn't build, so comment it out for now

Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-08-02 10:09:10 +08:00
root
f9c0f21beb Add FriendlyElec NanoPi-R6C platform 2023-08-02 09:46:36 +08:00
Mario Bălănică
e34219f362 Platform/R58-Mini: Enable PCIe for WLAN
Recent changes have fixed PCIe on all Mekotronics boards.
2023-07-28 04:36:30 +03:00
amazingfate
52315a7bf5 add usb hub reset gpio for h88k 2023-07-26 18:58:05 +03:00
Mario Bălănică
98aec4c33c Clean-up some of the unused code
Rockchip EVB platforms and RK356x silicon bits have also been deleted.

1) EVB platform was outdated, unbuildable and I don't have the hardware to test. Feel free to add it back if you do :-)

2) RK356x support was almost non-existent outside of some basic HAL SDK ported code.
There's no interest to support it in this repo either - unless, of course, it's done properly with code reusability in mind (but then might as well aim for upstream).
2023-07-26 02:49:26 +03:00
amazingfate
8358d31f3a fix shell syntax 2023-07-25 20:27:27 +03:00
amazingfate
4ea9e4041d Add Hinlink H88K platform 2023-07-25 20:27:05 +03:00
Mario Bălănică
6eeff5000d Platform/ROCK5A: Enable vcc_5v0
USB 2.0 ports were not working.

Fixes #35
2023-07-24 18:28:54 +03:00
Mario Bălănică
784d85ffd5 Silicon/RK3588: Support PCIe switches in UEFI 2023-07-23 23:36:30 +03:00
Mario Bălănică
c812b12708 Add Mixtile Blade 3 platform
- The two RTL8125s don't work as they're behind a PCIe switch, we don't support this yet.

 - With a 5V supply the board is not able to properly feed the 5V and 3.3V lines, resulting in USB devices not working at all and NVME crashing under load.

Since we currently lack PD negotiation, higher fixed voltage must be supplied to either the USB-C PD port or U.2 slot.

It is also possible to load vendor U-Boot, let it do the negotiation then reboot into UEFI from another media. Voltage will persist across reboots and even power cycles as long as the supply is not disconnected.
2023-07-16 04:44:17 +03:00
Mario Bălănică
c206fdfe0e Silicon/RK3588: Route PCIe 2 l0 & l1 to the correct Combo PHYs 2023-07-16 04:09:53 +03:00
Mario Bălănică
f85454f8b7 Mark mkimages as executable 2023-07-15 18:55:29 +03:00
Mario Bălănică
c2652a54bf Add arm64 mkimage
Built from cc781e0266

Fixes issue #34
2023-07-15 18:38:05 +03:00
Mario Bălănică
30fcba8889 Silicon/Rockchip: Add 0x45 (SanDisk) eMMC MID to boot description list 2023-07-13 02:44:55 +03:00
Mario Bălănică
6853c6ceaa Silicon/Rockchip: Add proper boot descriptions for SD/eMMC 2023-07-09 16:12:18 +03:00
Mario Bălănică
68841b48bf Silicon/Synopsys: DwMmcHcDxe: Discard CRC field for CID too 2023-07-09 03:38:57 +03:00
Mario Bălănică
175d90f9d4 Silicon/Rockchip: Rename gOhciDeviceProtocol to gOhciDeviceProtocolGuid 2023-07-07 22:00:07 +03:00
Mario Bălănică
37d0c718ff Silicon/Rockchip: Connect OHCI and SD/eMMC boot device before console
This fixes:
 - USB 1.1 devices (keyboard) not working until the BDS timeout
 - NVRAM vars on SD/eMMC not being dumped in time when the boot process isn't interrupted
2023-07-07 21:52:54 +03:00
Mario Bălănică
01d7159814 Silicon/Rockchip: DwcSdhciDxe: Fix PHY DLL configuration
HS400 appears to work reliably now.
2023-07-07 05:01:55 +03:00
Mario Bălănică
825f4f68f0 Silicon/Rockchip: RkFvbDxe: Fix boot disk detection
Broken by recent SD/eMMC changes.
2023-07-07 00:25:26 +03:00
Mario Bălănică
dd7867fd10 Silicon/Rockchip: RkSdmmcDxe: Allow software card detection 2023-07-06 18:48:24 +03:00
Mario Bălănică
f7f26addb4 Rename SD platform libs and PCDs 2023-07-06 18:33:33 +03:00
Mario Bălănică
e895cbbb33 Silicon/Rockchip: Delete DwEmmcDxe
We've switched to DwMmcHcDxe which provides better PIO performance, with the potential for DMA and higher speed modes in the future.

WinPE can also be loaded from SD card now.
2023-07-06 18:08:09 +03:00
Mario Bălănică
077100b9e0 Silicon/Synopsys: DwMmcHcDxe: Support SD version 1 cards
Tested with a 256 MB Nokia card.
2023-07-06 17:50:50 +03:00
Mario Bălănică
2773d70772 Silicon/Synopsys: DwMmcHcDxe: Wait for auto CMD12 and data transfer over
The driver is now able to properly identify cards and write data to them.
Tested with ADATA 8 GB Class 4 and SanDisk Extreme 32 GB.

Performance is quite a bit better compared to DwEmmcDxe, at the same bus speed.
2023-07-06 17:50:50 +03:00
Mario Bălănică
6f0aad4630 Silicon/Synopsys: DwMmcHcDxe: Add error & timeout handling to TransferFifo()
The driver would hang in an infinite loop trying to transfer data when it was no longer possible.
For instance, quickly plugging and unplugging a card could easily trigger this.
2023-07-06 17:50:49 +03:00
Mario Bălănică
287f386df5 Silicon/Synopsys: DwMmcHcDxe: Reset FIFO before doing block transfers 2023-07-06 17:50:49 +03:00
Mario Bălănică
abf1dc7dce Silicon/Synopsys: DwMmcHcDxe: Handle command errors 2023-07-06 17:50:49 +03:00
Mario Bălănică
dc1d8ba8de Silicon/Synopsys: DwMmcHcDxe: Fix card detection 2023-07-06 17:50:48 +03:00
Mario Bălănică
2fb26b6ccf Silicon/Rockchip: Add DwMmcHcDxe-based SD driver
Only tested with a Class 4 card in HS mode (for now).

Missing clock rate and phase configuration.
2023-07-06 17:50:48 +03:00
Mario Bălănică
f567489c71 Silicon/Synopsys: Add gDwMmcHcNonDiscoverableDeviceGuid 2023-07-06 17:50:48 +03:00
Mario Bălănică
1ae483c7b3 Silicon/Synopsys: Move DwMmcHcDxe.dec to root of DesignWare 2023-07-06 17:50:47 +03:00
Mario Bălănică
26c3c2124e Silicon/Synopsys: Import DwMmcHcDxe
7919500800

This is an alternative to DwEmmcDxe for the custom MSHC controller. It follows the new driver model and appears to support SDR104.

I found it randomly in the edk2 devel mailing list, submitted to EmbeddedPkg. It didn't get merged due to some minor cosmetic issues.
2023-07-06 17:50:47 +03:00
initdc
4815cc03c0 Add NanoPi R6S platform 2023-06-30 22:21:41 +03:00
Molly Sophia
331fbdd582 build.sh: Don't build SimpleInit when not enabled[skip ci]
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-06-27 12:50:06 +08:00
Molly Sophia
f32687b128 build.sh: Fix build when SimpleInit disabled while present[skip ci]
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-06-27 12:41:13 +08:00
Mario Bălănică
c6ab6ecf00 Silicon/Rockchip: Switch to upstream MmcDxe
The downstream version was only needed by SdhciHostDxe to set HS400ES.
2023-06-27 04:31:51 +03:00
Mario Bălănică
3d3f905b74 Delete old SdhciHostDxe code 2023-06-27 04:09:48 +03:00
Mario Bălănică
0d5f7fe014 Silicon/Rockchip: Add SdMmcPciHcDxe-based eMMC driver
This replaces the old SdhciHostDxe driver which is quite limited and has some issues around the DMA code.

It supports all speed modes with the exception of HS400ES (requires a few changes in SdMmcPciHcDxe).

Derived from Quartz64-UEFI's EmmcDxe.
2023-06-27 03:58:52 +03:00
Mario Bălănică
a4b551c603 workflows: Add nightly builds
CI build time has doubled due to GitHub Actions being limited to 20 parallel workflow runs, so only build the firmware for Release on a "nightly" schedule in order to halve the number of runs.

Also ignore markdown documentation changes and allow manual dispatch.
2023-06-25 01:15:06 +03:00
Mario Bălănică
7083c37b9c Add own mkimage back
Would be better to build it from source or even port to a Python script.
2023-06-24 01:52:43 +03:00
Mario Bălănică
85aee99911 Add rockchip-linux/rkbin submodule 2023-06-24 01:40:53 +03:00
Mario Bălănică
bc747e314f Delete rkbin blobs from repo 2023-06-24 01:32:26 +03:00
Mario Bălănică
1ea0d782a5 Platforms: Include PCIe & SATA SSDTs, disable IORT 2023-06-24 01:12:52 +03:00
Mario Bălănică
9c10dafb37 Silicon/RK3588: Expose PCIe & SATA in ACPI depending on configuration
This implementation based on RPi's ConfigDxe is good enough for now.
Might come back to it later and rework using dynamic tables with generators, so that PCIe resources, MCFG, MADT and IORT can be entirely populated by code.
2023-06-24 01:12:51 +03:00
Danct12
d3debe48a0 rkbin: Upgrade blobs
- Upgrade BL31 to v1.38
- Upgrade BL32 to v1.13
- Upgrade DDR blob to v1.11
- Upgrade SPL to v1.12

Changelog for these blobs can be found here:
https://gitlab.com/rk3588_linux/rk/rkbin/-/blob/78cbbc/doc/release/RK3588_EN.md
2023-06-23 18:25:47 +03:00
Mario Bălănică
1a1923e338 Silicon/RK3588: Fix PCIe addresses & add initial ACPI support
The configuration is almost identical to that of Quartz64-UEFI.
We hide the root port and expose only bus 1 to the OS due to non-compliant ECAM (therefore switches won't work).

ACPI support has been validated in Ubuntu Server 22.04.2 with NVME boot on PCIe 3x4 and onboard RTL8125B NIC on PCIe 2x1.

Windows is able to enumerate devices and even initialize the NVME drive, but unfortunately it keeps timing out.

Not yet enabled in platforms because we must expose only the controllers that are enabled/initialized.
2023-06-22 23:27:15 +03:00
Mario Bălănică
68f803dcfd Platforms: Configure and enable PCIe support
It's been tested to work on all platforms, with the exception of Mekotronics boards:
PCIE20L0 on R58-Mini hangs at "PCIe: Enabling DBI access" and on R58X it doesn't detect the Wi-Fi chip.

This is likely happening due to incorrect pin muxing, since GMAC routing was causing similar issues on other boards.
Will be addressed in a future patch.
2023-06-16 05:06:10 +03:00
Mario Bălănică
748e19d6de Silicon/RK3588: Update HII Combo PHY help descriptions
PHYs wired to permanent devices are not selectable, so the user won't see the description anyway.
2023-06-15 04:06:36 +03:00
Mario Bălănică
9f8e241524 Silicon/Rockchip: Enable networking and add Realtek UNDI drivers
Tested to work fine with the onboard RTL8125B PCIe NIC on ROCK 5B.
2023-06-15 03:39:55 +03:00
Mario Bălănică
5a9bb82754 Silicon/RK3588: Move PciHostBridgeInit Combo PHY config to RK3588Dxe 2023-06-15 03:03:23 +03:00
Mario Bălănică
91682461df Silicon/RK3588: Make PCIe 3.0 user-configurable 2023-06-15 01:53:03 +03:00
Mario Bălănică
0a8451ee09 Silicon/Rockchip: Delete old PCIe code and clean up dsc/fdf
The new implementation is currently RK3588-specific, so move its component descriptions to the according dsc/fdf.
2023-06-15 00:13:12 +03:00
Molly Sophia
74e0eb9e5e Silicon/RK3588: Add multiple PCIe2 support
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-06-14 23:12:27 +03:00
Mario Bălănică
9480cf365b Add OPi 5 Plus to README.md 2023-06-14 01:49:21 +03:00
Mario Bălănică
f32e9633fa Add Orange Pi 5 Plus platform
Variable changes on SPI NOR don't persist yet for some reason.
2023-06-14 01:36:55 +03:00
Mario Bălănică
40db0be757 Silicon/Rockchip: Add PlatformBootDescriptionLib
This filters the boot descriptions in UefiBootManagerLib and returns proper ones for the SD & eMMC Block I/O devices.

Additionally, it appends "(Not Connected)" to devices without a media present and "[Firmware]" to the boot device that holds the UEFI image.
2023-06-13 05:03:30 +03:00
Mario Bălănică
69054eaa09 Silicon/Rockchip: Implement proper card detection for DwEmmcDxe
Make use of the SDMMC_DET pin if available, otherwise fall back to RPi-style software detection.

This allows MmcDxe to handle hot-plugging and fixes timeouts without a card present.
2023-06-13 04:41:40 +03:00
Mario Bălănică
0b70ec8d83 Silicon/RK3588: Add GpioPinReadActual function to GpioLib
This reads the actual state of the pin, while GpioPinRead returns the target value.
2023-06-13 04:25:13 +03:00
Mario Bălănică
4cc20e30a1 Silicon/Rockchip: Move DwEmmcDxe platform-specific code into a lib 2023-06-13 04:19:43 +03:00
Mario Bălănică
8971c2feb4 workflows/build: Shallow submodule checkout
This shaves over 1 minute on average off the checkout step.
2023-06-11 16:38:42 +03:00
Molly Sophia
e0f6bc60df GpioLib: Implement pinconf functions
Bugs may exist

Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-06-11 13:09:33 +08:00
Molly Sophia
5aed3e41b7 edk2-platforms: Add as a submodule
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-06-11 12:38:03 +08:00
Molly Sophia
b917dcce9b Remove old edk2-platforms folder
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-06-11 12:33:52 +08:00
Molly Sophia
85a4f36ba4 edk2-rockchip: Split out from edk2-platforms
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-06-11 12:33:22 +08:00
Molly Sophia
7e438114d3 edk2-non-osi: Add as a submodule
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-06-11 12:13:33 +08:00
Molly Sophia
197333ea2b Remove old edk2-non-osi folder
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-06-11 12:09:44 +08:00
Molly Sophia
1e334b95fe Silicon/Rockchip: Fix compilation after edk2 rebase
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-06-11 11:44:02 +08:00
Molly Sophia
c4e15c7a34 edk2: Rebase to edk2-stable202302
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-06-11 11:44:02 +08:00
Molly Sophia
506658f6a7 Remove old edk2 folder.
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-06-11 11:44:02 +08:00
Mario Bălănică
a2be49950b Silicon/Rockchip: Add processor name PCD
Some (early?) RK3588S silicon does not have the CPU version set in OTP, meaning that it will identify as a full RK3588.
2023-06-11 05:17:06 +03:00
Mario Bălănică
8068666b43 Silicon/Rockchip: More dsc/fdf/dec cleanup
Remove more leftovers from HiSilicon and DwEmmcDxe package.
2023-06-11 04:49:15 +03:00
Mario Bălănică
cc60274c17 Silicon/Rockchip: Disable reset to maskrom app
It does not work and I'm not sure it can be reliably made to.
2023-06-11 03:38:09 +03:00
Mario Bălănică
d1f0312307 Silicon/Rockchip: RK3588Dxe: Remove unused variables 2023-06-10 19:45:20 +03:00
Mario Bălănică
97078c4496 Silicon/Rockchip: RK3588Dxe: Clean up
Remove hardcoded boot options, unused headers and libraries leftover from HiKeyDxe.
2023-06-10 19:37:19 +03:00
Mario Bălănică
d7c18353f1 Silicon/Rockchip: Place variable arch drivers after RkFvbDxe
RkFvbDxe must load before VariableRuntimeDxe so it can take care of a potentially corrupted / missing FV header.

DSC change is purely cosmetic.
2023-06-10 17:59:33 +03:00
Mario Bălănică
610b43eb07 Silicon/Rockchip/RK3588: Re-enable RK860X regulator support 2023-06-10 15:57:37 +03:00
Mario Bălănică
2c58062352 Refactor platform and flash descriptions 2023-06-10 15:37:23 +03:00
Molly Sophia
3d435e40de ROCK-5A: Dsdt: Expose sata0
It was done earlier in fc5ee180d8, which was accidentally reverted in my commits

Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-06-01 17:05:22 +08:00
Molly Sophia
6e6e0d137d NanoPC-T6: Configure ComboPhys correctly
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-06-01 16:49:03 +08:00
Molly Sophia
ec44410a65 ROCK-5A: Dsdt: Enable eMMC
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-06-01 11:49:01 +08:00
Molly Sophia
b9775add6b RkFvbDxe: Fix Fvb erase when Fvb Header is invalid
After writing UEFI image into eMMC for the first time, the FvbHeader is
invalid and the WRITE_STATUS attribute is unset, which prevents the Fvb
from being erased thus causing Exception.

Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-06-01 11:00:43 +08:00
Mario Bălănică
8d3b89755d Update README.md 2023-06-01 03:52:28 +03:00
Mario Bălănică
b9e6b9baec Platforms: Make UEFI FV size consistent
Increase size to 0x00500000 for remaining platforms.
2023-06-01 03:40:02 +03:00
Mario Bălănică
1bb2861929 Do not append NV var store to the final flash image
This allows the variables to persist across firmware updates.

If the store is corrupted or missing (which was also the case with NV_DATA.img being actually empty), the FVB driver should rewrite a clean FV header.
2023-06-01 03:36:20 +03:00
Mario Bălănică
017844d902 Platform/ROCK5A: Rename "ROCK 5A" to "ROCK 5 Model A"
To be consistent with Model B and naming on the website.
2023-06-01 02:54:54 +03:00
Mario Bălănică
5fc7f34ea5 Platform/ROCK5B: Don't allow switching Combo PHY #0
It is hardwired to the onboard Realtek PCIe NIC.
2023-06-01 02:43:40 +03:00
Mario Bălănică
f6c1346772 Silicon/Rockchip: Disable SATA staggered spin-up
With it enabled, NetBSD doesn't pick up any drive (be it HDD or SSD) most of the time (is this a driver or controller bug?).
2023-06-01 02:42:05 +03:00
Mario Bălănică
fc5ee180d8 Platforms: Expose SATA devices in ACPI
Enable only controllers that have the PHY routable to some kind of connector on the platform.

It would be better to have them into their own SSDT that gets installed at runtime depending on the Combo PHY configuration.
2023-06-01 02:39:39 +03:00
Mario Bălănică
57a86578c2 Platforms: Set default CPU clock presets
The SoC heats up quite a lot with CPU clocks and voltages always set to max.
Therefore, leave clocks at their boot default value on platforms without active cooling that's turned on by default.
The presets can be overridden by the user in the Configuration menu, assuming proper cooling is installed.
2023-06-01 01:06:48 +03:00
Mario Bălănică
39118afb47 Silicon/Rockchip: Add default cluster clock preset PCDs 2023-06-01 00:46:43 +03:00
Mario Bălănică
40be23e7d5 Platforms: Configure default Combo PHY modes
- Combo PHY #1 is not exposed on RK3588S.

- For platforms that have an USB 3 port directly wired to the PHY (that is, no hub in between), allow switching modes as it's fairly possible to hack together an USB 3 to PCIe or SATA cable.
2023-06-01 00:00:03 +03:00
Mario Bălănică
7595444430 Silicon/Rockchip: Make the Naneng Combo PHY user-configurable 2023-05-31 23:23:37 +03:00
Mario Bălănică
16d3555631 Silicon/Rockchip: Fix SATA support
The upstream driver works fine if we correct the HBA capabilities.

Also fix and split the ACPI devices into their own file, since RK3588S lacks SATA #1.
2023-05-30 18:57:35 +03:00
Mario Bălănică
dbde496288 Platforms: Switch to AHCI drivers from MdeModulePkg 2023-05-30 18:38:36 +03:00
Mario Bălănică
4f261d1115 Platform/ROCK5A: Enable eMMC and update pin muxing comments
Same as the previous change for Indiedroid Nova.
2023-05-30 04:15:21 +03:00
Mario Bălănică
e1f1f50ef5 Platform/IndiedroidNova: Do not override eMMC and FSPI pin muxing
The eMMC slot is shared with FSPI, making it possible to connect either an eMMC or SPI NOR module.
Pin muxing is already configured by earlier boot stages depending on what's detected in the slot, thus no need to perform the detection ourselves.
2023-05-30 04:13:27 +03:00
Mario Bălănică
df1f46add9 Platforms: Enable RkFvbDxe 2023-05-30 03:24:44 +03:00
Mario Bălănică
c1de6b10ff Silicon/Rockchip: Support persistent variable store on SD/eMMC
On SD/eMMC this feature is more limited, since these devices are meant to be used by the OS and we can't take ownership of them.
As such, changes to the var store will only be saved at boot time when certain events happen (platform reset, ready to boot, image load).

Full runtime support is available when booted from SPI NOR flash.

Also introduce the gRockchipTokenSpaceGuid.PcdNvStoragePreferSpiFlash flag which forces the var store to be on SPI flash, if available, no matter the boot device.
This can be useful during development as NOR flash is quite slow to write compared to SD.
2023-05-30 03:08:04 +03:00
Mario Bălănică
4db804855f Silicon/Rockchip: Make SD controllers identifiable by base address 2023-05-30 02:06:12 +03:00
Mario Bălănică
1184da0f5d Silicon/Rockchip: Signal an event on system reset 2023-05-30 02:00:33 +03:00
Mario Bălănică
d496851043 U-Boot FIT: Map UEFI NV region into memory
Load it at the same address as seen in flash so we don't have to deal with reading it from the boot device in UEFI anymore.
2023-05-30 01:54:27 +03:00
Mario Bălănică
1d435eeafb Silicon/Rockchip: Add ATAGS reading library 2023-05-26 17:48:50 +03:00
Molly Sophia
0c765f022b Workflow: Fix CI
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-05-21 16:11:43 +08:00
Molly Sophia
3461e121e6 Rockchip: Reduce code duplication in DwEmmcDxe
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-05-21 16:08:16 +08:00
Molly Sophia
8eb1541a00 RK3588: Remove duplicated (and unused) RK3588Dxe
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-05-21 16:05:27 +08:00
Molly Sophia
3dd1abd91d Update build.sh
This includes several tiny fixes:
- Fixed `build.sh --clean` command
- Partially fixed `build.sh -d all` command
- Don't check for SimpleInit folder when BUILD_GUI is false
- Added a define CONFIG_SOC for reducing code duplication

Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-05-21 15:54:03 +08:00
Molly Sophia
cfdb896be5 Platforms: Add initial support for Radxa rock-5a
What's working:
- USB3 Ports
- HDMI0 Output

Note: On rock-5a the FSPI for SPI NOR is multiplexed with the eMMC
module, so both are not configured yet. May try to add some
autodetecting code later.

Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-05-20 11:59:54 +08:00
Molly Sophia
694dfc8b25 Workflow: Add NanoPC T6
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-05-14 14:18:23 +08:00
Sophon
f5e87e2230 Merge pull request #22 from MollySophia/molly/nanopc-t6
Platforms: Add initial support for NanoPC T6
2023-05-14 14:13:59 +08:00
Molly Sophia
b3abf83da7 Platforms: Add initial support for NanoPC T6
What's working:
- Type-C and USB
- HDMI0 Output
- eMMC and SDHCI

What's broken or untested:
- Everything else

Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
2023-05-14 14:06:27 +08:00
Mario Bălănică
3676af4b37 Add Khadas Edge2 platform 2023-05-11 19:07:20 +03:00
Mario Bălănică
5570bf1348 Silicon/Rockchip: Delete Usb2PhySuspend() in RockchipPlatformLib
Unused and actually enables the PHYs.
2023-05-02 04:07:38 +03:00
Mario Bălănică
4999bfad7d Add Mekotronics R58 Mini platform
The device is a trimmed down R58X.
No PCIe / M.2 slots and SD expansion is completely missing.
2023-05-02 03:32:00 +03:00
Mario Bălănică
05f8cc20fc Add Mekotronics R58X platform
Everything currently supported works except for the micro SD card slot - no idea what it's connected to,
no signs of life on either MSHC controller even in Maskrom mode.
2023-05-02 02:54:32 +03:00
Mario Bălănică
b88a32dd93 Fix and expose eMMC device in ACPI
In preparation for Windows support.
2023-04-28 18:54:25 +03:00
Mario Bălănică
08c90b9eb2 Silicon/Rockchip: Improve eMMC detection 2023-04-28 18:49:29 +03:00
Mario Bălănică
6e88083971 Enable EMMC boot for platforms that support it 2023-04-21 22:17:17 +03:00
Mario Bălănică
f5895f0295 Silicon/Rockchip: Add card detection in SdhciHostDxe
Adapted from ArasanMmcHostDxe.
Fixes #17
2023-04-21 22:16:08 +03:00
Mario Bălănică
e62c694e7b Add config options for CPU clock rates and voltages
By default, clock rates are set to maximum and voltages are set depending on the clock.
This behavior can be changed in the CPU Performance form (for platforms that have persistent NV support as of now).

Clocks are set as soon as we get write access to the var store, however voltages will be set later on first notification of the ReadyToBoot event.
This allows the user to dial settings back in case the values are too high and the system hangs or boot loops when loading the OS.
2023-04-20 12:14:15 +03:00
Mario Bălănică
fc1afc0b1e Add identification tags to RK860X regulators 2023-04-20 09:55:08 +03:00
Mario Bălănică
b9857a812a Minor refactoring for RockchipPlatformLib and I2cDxe 2023-04-17 05:16:35 +03:00
Mario Bălănică
bf4468e1b6 Add Firefly ROC-RK3588S-PC and Station M3 platforms
Station M3 is basically a complete package (case, cooling, accessories) built around the ROC-RK3588S-PC board.
We have a separate platform for it as it's sold under a different brand with its own logo and product name.
2023-04-17 03:15:55 +03:00
Mario Bălănică
c2b5ffd259 Silicon/Rockchip: Add SMBIOS PCDs for motherboard vendor and name 2023-04-17 03:15:54 +03:00
Mario Bălănică
1dd3e75ad5 Add miscellaneous init function for platforms 2023-04-17 03:15:33 +03:00
Mario Bălănică
a4bf6ae99f Platform/IndiedroidNova: Enable & configure voltage regulators 2023-04-15 02:10:18 +03:00
Mario Bălănică
bf712b17d5 Silicon/Rockchip: More fixes for the regulator event handler 2023-04-14 23:13:57 +03:00
Mario Bălănică
15d6b7a31b Silicon/Rockchip: Remove dependency on gRk860xRegulatorProtocolGuid
In case some platforms don't have it configured yet.
2023-04-14 22:36:19 +03:00
Mario Bălănică
45c5c04c27 Platform/ROCK5B: Update RK806 voltages
Little CPU cluster is set to maximum voltage for roughly 1.8 GHz.
2023-04-13 05:06:29 +03:00
Mario Bălănică
e2696f8a03 Platform/ROCK5B: Enable RK860X regulators for the big cores 2023-04-13 04:41:30 +03:00
Mario Bălănică
c6e85e2b93 Platform/OrangePi5: Enable RK860X regulators for the big cores 2023-04-13 04:36:55 +03:00
Mario Bălănică
eda397ef22 Silicon/Rockchip: Configure RK860X in RK3588Dxe 2023-04-13 04:20:19 +03:00
Mario Bălănică
d922f80d9a Silicon/Rockchip: Add RK860X voltage regulator driver 2023-04-13 04:06:30 +03:00
Mario Bălănică
aa2637795f Silicon/Rockchip: Move USB PHY setup back to UsbHcdInitDxe 2023-04-13 02:37:22 +03:00
Mario Bălănică
920a324046 Fix USB controller sizes and delete unused PCDs 2023-04-13 02:33:16 +03:00
Mario Bălănică
aaa4412ed6 Silicon/Rockchip: Create a protocol for OhciDxe
We can initialize these controllers only *after* USB PHY setup, which happens in a driver that may load later.

This also fixes the boot delay caused by storage devices being initially enumerated on OHCI (due to it loading earlier) and a second time on EHCI or XHCI.
2023-04-13 02:25:10 +03:00
WillzenZou
b808ae5d79 Platform/OrangePi5: Adjust the voltage to allow the CPU frequency to be normal and remove the PCIe3 initialisation until PCIe2 is supported.
Note: Voltage reference from Orange Pi5's Linux device tree and schematic
2023-04-09 03:34:37 +03:00
Mario Bălănică
5468c3911b workflows/build: Add indiedroid-nova 2023-04-08 16:22:34 +03:00
Mario Bălănică
d3fd20e064 Platform/IndiedroidNova: Add initial support
Almost everything currently supported works, with the exception of SDMMC and possibly other things that require GPIO mux.
We have no schematics for this board yet.

Also known as 9Tripod Pico Pi V2.0.
2023-04-08 16:19:47 +03:00
Mario Bălănică
f3a02af3d3 Platform/ROCK5B: Remove vendor from platform name
Fix "Radxa Radxa"
2023-04-06 21:54:03 +03:00
Mario Bălănică
b2a49eb86c Silicon/Rockchip: Set ARM clocks to maximum 2023-04-06 21:22:21 +03:00
Mario Bălănică
1571a69925 Move RK806 init to RockchipPlatformLib 2023-04-06 20:27:35 +03:00
Mario Bălănică
519474e4ec Move RK3588Dxe to Silicon/Rockchip/RK3588
All board-specific code should be moved to RockchipPlatformLib instead.
2023-04-06 20:23:25 +03:00
Mario Bălănică
f688ecb5c1 Move common ACPI tables to Silicon/Rockchip/RK3588 2023-04-05 20:34:26 +03:00
Mario Bălănică
d8fb4f170b Update SMBIOS and share it between boards
The serial number and SoC model are now read from OTP memory.

CPU clock is read from SCMI but it may need some tweaking.
2023-04-05 02:19:47 +03:00
Mario Bălănică
9172e8a588 Silicon/Rockchip: Add RK3588 OTP library 2023-04-05 01:35:10 +03:00
Mario Bălănică
47ff4eb0fe Platform/ROCK5B: Don't include SimpleInit.inc if it's disabled 2023-04-02 20:41:49 +03:00
Mario Bălănică
c56ba68db8 Delete ROCK5B and OrangePi5 package declarations
We don't need them anymore.
2023-04-02 20:12:43 +03:00
Mario Bălănică
3a940530c8 Delete our Dw8250SerialPortLib fork and use Hisilicon's instead 2023-04-02 20:10:15 +03:00
Mario Bălănică
ca9f78d422 Move ROCK5B's GpioLib to Silicon/Rockchip/RK3588 2023-04-02 19:51:38 +03:00
Mario Bălănică
42fd558d61 Move ROCK5B's RkMtlLib to Silicon/Rockchip 2023-04-02 19:29:07 +03:00
Mario Bălănică
4fdc21d1f5 Move ROCK5B's maskrom app to Silicon/Rockchip 2023-04-02 19:21:05 +03:00
Mario Bălănică
ec0751ff07 Move ROCK5B's MemoryInitPeiLib to Silicon/Rockchip/RK3588 2023-04-02 19:09:04 +03:00
Mario Bălănică
9b28318d67 Move ROCK5B's ResetSystemLib to Silicon/Rockchip 2023-04-02 18:32:35 +03:00
Mario Bălănică
b6b21196b1 Move ROCK5B's DwEmmcDxe to Silicon/Rockchip/RK3588 2023-04-02 18:23:25 +03:00
Mario Bălănică
8b86613593 Move plat CruLib and Sdhci helper to Silicon/Rockchip/RK3588 2023-04-02 17:56:52 +03:00
Mario Bălănică
70067ff9ba Silicon/Rockchip: Remove stale boot options in PlatformBootManagerLib
Fixes #16
2023-04-02 01:02:22 +03:00
Mario Bălănică
14296a2d03 Silicon/Rockchip: Delete unused BmcConfigBootLib 2023-04-02 00:32:38 +03:00
Mario Bălănică
760f28cf7c Move ROCK5B's PlatformBootManagerLib to Silicon/Rockchip 2023-04-02 00:24:57 +03:00
Xilin Wu
a92e99261c Make simple-init optional 2023-03-28 09:44:38 +08:00
Xilin Wu
91fcaad18f rock-5b: Enable FvSimpleFileSystemDxe 2023-03-28 09:23:36 +08:00
WillzenZou
f0bf08d7a2 Platform/OrangePi5: Support SD card boot and expose microSD socket via ACPI.
From the efforts of @Googulator.
2023-03-27 23:05:49 +03:00
WillzenZou
6d0fe9b99d Replace mkimage binary form rockchip's uboot sources to fix "libc.so.6: version `GLIBC_2.34' not found" when build in ubuntu 20.04.
It might be better to integrate the source code of mkimage in rockchip's uboot.
2023-03-27 23:05:49 +03:00
WillzenZou
1832e267aa Platform/OrangePi5: Add OrangePi Logo. 2023-03-27 23:05:49 +03:00
Mario Bălănică
a7c9207fc3 workflows/build: Switch to actions/checkout@v3
Silence warnings.
2023-03-26 04:31:28 +03:00
36755 changed files with 116299 additions and 5571982 deletions

View File

@@ -1,30 +1,62 @@
name: Build
on:
push:
paths-ignore:
- '**.md'
branches:
- master
pull_request:
paths-ignore:
- '**.md'
branches:
- master
workflow_call:
inputs:
build-configs:
type: string
required: true
workflow_dispatch:
jobs:
build:
runs-on: ubuntu-latest
strategy:
matrix:
PLATFORM: [rock-5b, orangepi-5] # rk3588-evb is currently failing
CONFIGURATION: [Debug, Release]
PLATFORM:
- aio-3588q
- blade3
- edge2
- fydetab-duo
- h88k
- indiedroid-nova
- itx-3588j
- nanopc-cm3588-nas
- nanopc-t6
- nanopi-m6
- nanopi-r6c
- nanopi-r6s
- orangepi-5
- orangepi-5plus
- powerstation-6
- r58-mini
- r58x
- roc-rk3588s-pc
- rock-5-itx
- rock-5a
- rock-5b
- rock-5bplus
- station-m3
CONFIGURATION: ${{ fromJSON(format('[{0}]', inputs.build-configs || '"Debug"')) }}
steps:
- name: Checkout
uses: actions/checkout@v2
- name: Submodule init
shell: bash
run: git submodule update --init --recursive
uses: actions/checkout@v4
with:
submodules: recursive
- name: Install dependencies
shell: bash
run: |
sudo apt-get update && \
sudo apt-get install -y \
acpica-tools \
binutils-aarch64-linux-gnu \
@@ -35,21 +67,44 @@ jobs:
gcc-aarch64-linux-gnu \
libc6-dev-arm64-cross \
python3 \
python3-pyelftools
python3-pyelftools \
uuid-dev
- name: Get version tag
id: get_version_tag
shell: bash
run: echo "version=$(git describe --tags --always)" >> $GITHUB_OUTPUT
- name: Set up Secure Boot default keys
run: |
mkdir keys
# We don't really need a usable PK, so just generate a public key for it and discard the private key
openssl req -new -x509 -newkey rsa:2048 -subj "/CN=Rockchip Platform Key/" -keyout /dev/null -outform DER -out keys/pk.cer -days 7300 -nodes -sha256
curl -L https://go.microsoft.com/fwlink/?LinkId=321185 -o keys/ms_kek.cer
curl -L https://go.microsoft.com/fwlink/?linkid=321192 -o keys/ms_db1.cer
curl -L https://go.microsoft.com/fwlink/?linkid=321194 -o keys/ms_db2.cer
curl -L https://uefi.org/sites/default/files/resources/dbxupdate_arm64.bin -o keys/arm64_dbx.bin
- name: Build platform
shell: bash
run: |
./build.sh --device ${{matrix.PLATFORM}} --release ${{matrix.CONFIGURATION}}
run: |
export EDK2_SECUREBOOT_FLAGS=" \
-D DEFAULT_KEYS=TRUE \
-D PK_DEFAULT_FILE=keys/pk.cer \
-D KEK_DEFAULT_FILE1=keys/ms_kek.cer \
-D DB_DEFAULT_FILE1=keys/ms_db1.cer \
-D DB_DEFAULT_FILE2=keys/ms_db2.cer \
-D DBX_DEFAULT_FILE1=keys/arm64_dbx.bin \
-D SECURE_BOOT_ENABLE=TRUE"
export EDK2_BUILD_FLAGS=" \
${EDK2_SECUREBOOT_FLAGS}"
./build.sh --device ${{matrix.PLATFORM}} --release ${{matrix.CONFIGURATION}} --edk2-flags "${EDK2_BUILD_FLAGS}"
mv RK3588_NOR_FLASH.img ${{matrix.PLATFORM}}_UEFI_${{matrix.CONFIGURATION}}_${{steps.get_version_tag.outputs.version}}.img
- name: Upload artifact
uses: actions/upload-artifact@v3
uses: actions/upload-artifact@v4
with:
name: ${{matrix.PLATFORM}} UEFI ${{matrix.CONFIGURATION}} image
path: ./*.img

41
.github/workflows/nightly.yml vendored Normal file
View File

@@ -0,0 +1,41 @@
name: Nightly
run-name: Nightly build
on:
schedule:
- cron: "0 0 * * *"
jobs:
prepare:
runs-on: ubuntu-latest
permissions:
actions: write
steps:
- name: Delete previous cancelled runs
uses: Mattraks/delete-workflow-runs@v2
with:
retain_days: 0
keep_minimum_runs: 0
delete_workflow_pattern: ${{ github.workflow }}
delete_run_by_conclusion_pattern: cancelled
- name: Check for new commits
id: check-new-commits
uses: adriangl/check-new-commits-action@v1
with:
seconds: 86400 # One day in seconds
branch: 'master'
- name: Cancel action if no new commits
if: ${{ steps.check-new-commits.outputs.has-new-commits != 'true' }}
uses: andymckay/cancel-action@0.3
- name: Wait for cancellation
if: ${{ steps.check-new-commits.outputs.has-new-commits != 'true' }}
shell: bash
run: while true; do echo "Waiting for job to be cancelled"; sleep 5; done
build_for_nightly:
needs: prepare
uses: ./.github/workflows/build.yml
with:
build-configs: '"Debug", "Release"'

View File

@@ -1,13 +1,15 @@
name: Release
on:
on:
push:
tags:
- '*'
jobs:
build_for_release:
uses: ./.github/workflows/build.yml
with:
build-configs: '"Debug", "Release"'
release:
runs-on: ubuntu-latest
needs: build_for_release
@@ -15,20 +17,12 @@ jobs:
contents: write
steps:
- name: Download all workflow run artifacts
uses: actions/download-artifact@v3
uses: actions/download-artifact@v4
- name: Create release
uses: softprops/action-gh-release@v1
uses: softprops/action-gh-release@v2
with:
draft: true
prerelease: false
files: "*/*Release*.img"
fail_on_unmatched_files: true
generate_release_notes: true
append_body: true
body: |
## Usage
Flash the board-specific image to SPINOR with rkdevtool / rkdeveloptool or to an EMMC / SD card.
If your board is not yet supported, using a similar image may work but beware of potential issues.
Debug builds can be found in the artifacts of the workflow run for this release.

1
.gitignore vendored
View File

@@ -6,7 +6,6 @@ workspace
ramdisk
.cache
.vscode
*.dts
*.swp
*.rej
*.orig

20
.gitmodules vendored
View File

@@ -1,4 +1,16 @@
[submodule "simple-init"]
path = simple-init
url = https://github.com/BigfootACA/simple-init.git
branch = master
[submodule "edk2"]
path = edk2
url = https://github.com/tianocore/edk2.git
[submodule "edk2-non-osi"]
path = edk2-non-osi
url = https://github.com/tianocore/edk2-non-osi.git
[submodule "misc/rkbin"]
path = misc/rkbin
url = https://github.com/rockchip-linux/rkbin.git
[submodule "arm-trusted-firmware"]
path = arm-trusted-firmware
url = https://github.com/worproject/arm-trusted-firmware
branch = rk3588
[submodule "devicetree/mainline/upstream"]
path = devicetree/mainline/upstream
url = https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git

467
README.md
View File

@@ -1,65 +1,454 @@
# EDK2 UEFI firmware for Rockchip RK35xx platforms
# EDK2 UEFI firmware for Rockchip RK3588 platforms
This repository contains an UEFI firmware implementation based on EDK2 for various RK3588 boards.
**WARNING: This repo is highly experimental**
It delivers a PC-like standardized boot experience, supporting multiple operating systems, such as Windows, Linux, BSD and VMware ESXi.
## Description
![EDK2 Front Page](images/edk2-frontpage.png)
This repository is based on the official open-source UEFI implementation from Rockchip, which is under active development.
# Supported platforms
Support levels are categorized into two tiers: Platinum and Bronze.
Therefore, to keep up with the work from Rockchip, we should avoid modifying code from Rockchip in most cases.
Platinum devices are considered to have the best overall support, based on factors such as:
- Device Tree and peripherals compatible with mainline Linux. [**Required**]
- Active interest from the vendor in supporting their hardware.
- Hardware design choices:
- If an Ethernet port is present, Realtek PCIe NIC or integrated GMAC. [**Required**]
- SPI NOR flash for dedicated firmware storage. [Preferred]
Discussion thread: [Windows / UEFI on Rock 5 (Mega thread)](https://forum.radxa.com/t/windows-uefi-on-rock-5-mega-thread/12924)
Bronze devices may have limitations such as:
- Missing one or more required features listed above.
- Low interest from vendors and/or the community.
- Lack of proper validation, potentially affecting functionality.
## Building
Note that this list is subject to change at any time as devices gain better support or fall behind.
Using Arch Linux as example
## Platinum
- [Radxa ROCK 5B](https://radxa.com/products/rock5/5b/)
- [Radxa ROCK 5A](https://radxa.com/products/rock5/5a/)
- [Radxa ROCK 5 ITX](https://radxa.com/products/rock5/5itx/)
- [Orange Pi 5](http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-5.html)
- [Orange Pi 5 Plus](http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-5-plus.html)
- [Khadas Edge2](https://www.khadas.com/edge2)
- [BuzzTV P6](https://buzztvglobal.com/products/powerstation-6)
- [FriendlyELEC NanoPC T6](https://wiki.friendlyelec.com/wiki/index.php/NanoPC-T6)
- [FriendlyELEC NanoPi R6C](https://wiki.friendlyelec.com/wiki/index.php/NanoPi_R6C)
- [FriendlyELEC NanoPi R6S](https://wiki.friendlyelec.com/wiki/index.php/NanoPi_R6S)
- [FriendlyELEC NanoPC CM3588-NAS](https://wiki.friendlyelec.com/wiki/index.php/CM3588_NAS_Kit)
- [ameriDroid Indiedroid Nova](https://indiedroid.us)
Install required packages:
## Bronze
- [Radxa ROCK 5B+](https://radxa.com/products/rock5/5bp)
- [Fydetab Duo](https://fydetabduo.com/)
- [Firefly AIO-3588Q](https://en.t-firefly.com/product/industry/aio3588q)
- [Firefly ITX-3588J](https://en.t-firefly.com/product/industry/itx3588j)
- [Firefly ROC-RK3588S-PC](https://en.t-firefly.com/product/industry/rocrk3588spc) / [StationPC Station M3](https://www.stationpc.com/product/stationm3)
- [Mekotronics R58X](https://www.mekotronics.com/h-pd-75.html)
- [Mekotronics R58 Mini](https://www.mekotronics.com/h-pd-76.html)
- [Mixtile Blade 3](https://www.mixtile.com/blade-3)
- [FriendlyELEC NanoPi M6](https://wiki.friendlyelec.com/wiki/index.php/NanoPi_M6)
- [Hinlink H88K](http://www.hinlink.com)
# Supported OSes
## In ACPI mode
| OS | Version | Tested/supported hardware | Notes |
| --- | --- | --- | --- |
| Windows | 11 | [Status](https://github.com/worproject/Rockchip-Windows-Drivers#hardware-support-status) ||
| NetBSD | 10 | Display, UART, USB, PCIe (incl. NVME), SATA, eMMC, GMAC Ethernet ||
| VMware ESXi Arm Fling | >= 1.12 | Display, USB | * PCIe devices will hang at boot, need to disable in settings or leave the ports empty.<br>* GMAC Ethernet gets detected but does not work. |
| Linux | tested Ubuntu 22.04, kernel 5.15.0-75-generic | Display, UART, USB, PCIe (incl. NVME & Ethernet), SATA | For full hardware functionality, use a kernel with RK3588 support and switch to Device Tree mode. |
> [!NOTE]
> ACPI support is only being developed and tested against Windows. There are no plans to further improve functionality for other OSes. Consider using Device Tree instead (where applicable, for instance Linux).
## In Device Tree mode
### Vendor compatibility mode
| OS | Version | Tested/supported hardware | Notes |
| --- | --- | --- | --- |
| Rockchip SDK Linux | Kernel 5.10/6.1<br> Tested with:<br> - [Armbian rk3588-live-iso](https://github.com/amazingfate/rk3588-live-iso) | Platform-dependent, most peripherals work. | If using a different kernel, see [Device Tree configuration](#device-tree-configuration). |
### Mainline compatibility mode
| OS | Version | Tested/supported hardware | Notes |
| --- | --- | --- | --- |
| Generic upstream Linux | Kernel 6.10 or newer.<br> Tested with:<br> - Ubuntu 24.10<br> - Fedora Workstation 41<br> - Fedora Workstation Rawhide | Platform and kernel version dependent, see [Collabora's RK3588 upstream status](https://gitlab.collabora.com/hardware-enablement/rockchip-3588/notes-for-rockchip-3588/-/blob/main/mainline-status.md). | * Kernels older than 6.13 lack HDMI output. To work around this, see: [Device Tree configuration](#device-tree-configuration). |
> [!NOTE]
> Mainline support is only available on [Platinum](#platinum) platforms.
# Supported peripherals in UEFI
> [!NOTE]
> Applicable to all platforms unless otherwise noted.
>
> Only devices relevant to the firmware itself (not OS) are listed below.
| Device | Status | Notes |
| --- | --- | --- |
| USB 3 / 2.0 / 1.1 | 🟢 Working | Host-mode only, USB 3 devices connected to a Type-C port only work in one orientation. |
| PCIe 3.0 / 2.1 | 🟢 Working | |
| SATA | 🟢 Working | |
| SD/eMMC | 🟢 Working | |
| HDMI output | 🟢 Working | |
| DisplayPort output (USB-C) | 🟡 Partial | No hot-plug detect & EDID. Only works in one orientation of the Type-C port. Some displays may not work regardless. |
| eDP output | 🟡 Partial | Disabled, requires manual configuration depending on the platform and panel. |
| DSI output | 🟢 Working | Only enabled on Fydetab Duo. Requires manual configuration depending on the platform and panel. |
| GMAC Ethernet | 🟢 Working | |
| Realtek PCIe Ethernet | 🟢 Working | Some platforms don't have MAC addresses set, networking may not work in that case. |
| Low-speed (GPIO/UART/I2C/SPI/PWM) | 🟢 Working | UART2 console available at 1500000 baud rate |
| SPI NOR Flash | 🟢 Working | |
| HYM8563 real-time clock | 🟢 Working | |
| RNG | 🟢 Working | |
| Cooling fan | 🟢 Working | Supported on most platforms. Fan connector where present, otherwise available at the GPIO header for 3-pin PWM fans (do *not* connect 2-pin fans there!):<br>* Orange Pi 5: `GPIO4_B2`<br>* Indiedroid Nova: `GPIO4_B4` |
| Status LED | 🟢 Working | |
| Voltage regulators (RK806/RK860) | 🟢 Working | |
| FUSB302 USB Type-C Controller | 🔴 Not working | Required for PD negotiation and connector orientation switching |
# Getting started
## 1. Requirements
* One of the [supported devices](#supported-platforms).
* Storage for the firmware: SPI NOR flash (included with some devices), SD card or eMMC.
* Quality power supply that can provide at least 15 W. Depending on the peripherals you use, more may be needed.
Note: on Mixtile Blade 3, a fixed voltage *higher than* 5V must be supplied. The board cannot power any external peripherals if the input voltage is just 5V. USB-PD negotiation is not supported by firmware.
* HDMI (preferred) or DisplayPort (USB-C) screen.
* Optionally, if display is not available or for debugging purposes, an UART adapter capable of 1500000 baud rate (e.g. USB CH340, CP2104).
## 2. Download the firmware image
The latest version can be obtained from <https://github.com/edk2-porting/edk2-rk3588/releases>.
If your platform is not yet supported, using an image meant for another device is **NOT** recommended. Although they are generally similar, voltage setup can happen to be different and you may risk damaging the board. External peripherals are unlikely to work either.
## 3. Flash the firmware
UEFI can be flashed to either an SPI NOR flash, SD card or eMMC module:
* For removable SD or eMMC (easiest), you can simply use balenaEtcher, RPi Imager or dd.
* For SPI NOR or soldered eMMC, instructions can be found at: <https://wiki.radxa.com/Rock5/install/spi>.
In short, you can flash the image from Linux booted on the device or by using RKDevTool on another computer. The latter requires entering Maskrom mode on the device. The way to do this slightly varies across platforms, refer to your vendor documentation.
**Warning:** these operations will erase data on the storage device. Make a backup first!
If you wish to have both UEFI and an OS on the same SD or eMMC device: flash UEFI first, then create any additional partitions without touching the first, reserved one. Steps for updating the firmware in this case can be found [here](#updating-the-firmware).
Note: Using SPI NOR (if present) is recommeded, as it leaves the other storage options free for other purposes. Additionally, SD/eMMC will limit the firmware's ability to access its own storage (variable store) when an OS is running. This feature is mostly used by OS installers to create the boot menu options, it is not mandatory.
## 4. Connect peripherals and power on the device
If the flashing process has been done correctly, you should see the status LED blinking (if present), and shortly after, the platform's boot logo with a progress bar at the bottom on the connected display.
At this stage, you can press <kbd>Esc</kbd> to enter the firmware setup, <kbd>F1</kbd> to launch the UEFI Shell, or, provided you also have an UEFI bootloader/app on a storage device, you can let the system automatically run that, which is the default behavior if no action is taken.
Check the [Supported OSes](#supported-oses) and [Supported peripherals in UEFI](#supported-peripherals-in-uefi) sections to see what's currently possible with this firmware.
Also check the configuration options described below, some of which may need to be changed depending on the OS used.
If you experience any issues, please see the [Troubleshooting](#troubleshooting) section.
# Configuration settings
The UEFI provides a few configuration options, like CPU frequency, PCIe/SATA selection for an M.2 port, fan control, etc. These can be viewed and changed using the UI configuration menu (under `Device Manager`->`Rockchip Platform Configuration`).
Configuration through the user interface is fairly straightforward and help/navigation information is provided around the menus.
## Tips
### Boot time optimization
* If there are unused M.2/PCIe slots, you can disable them to skip initialization: `Device Manager`->`Rockchip Platform Configuration`->`PCIe/SATA/USB Combo PIPE PHY` and set the relevant PHYs to `Unconnected`. Do the same for `PCI Express 3.0` by setting `Support State` to `Disabled`.
* Auto boot time-out can be decreased from `Boot Maintenance Manager`.
* If network boot is not used, it can be disabled: `Device Manager`->`Network Stack Configuration` then uncheck `Network Stack`.
* If you do not need the ability to hot-plug displays or use DisplayPort while in the firmware: `Device Manager`->`Rockchip Platform Configuration`->`Display` and set `Force Output` to `Disabled`. This will skip display initialization when none is connected.
* By default, the firmware connects all boot devices regardless of whether they are needed for the current boot. This is done to address potential compatibility issues and generally takes a negligible amount of time, thus it is recommended to not change it. However, it is still possible to do so: `Boot Maintenance Manager`->`Boot Discovery Policy`.
### Linux boot
* If you're getting a Synchronous Exception when booting certain distros, go to `Device Manager`->`EFI Memory Attribute Protocol` and uncheck `Enable Protocol`.
## Device Tree configuration
For rich Linux support, it is recommended to enable Device Tree mode. You can do so by going to `Device Manager`->`Rockchip Platform Configuration`->`ACPI / Device Tree` and setting `Config Table Mode` to `Device Tree`.
The firmware provides two compatibility modes:
* `Vendor` - compatible with Rockchip SDK Linux 5.10/6.1 kernel only.
* `Mainline` - compatible with generic upstream Linux 6.10 or newer kernel. This option is under active development and may lack certain features. Therefore, it is always recommended to use the latest kernel and firmware available in order to benefit from better device support.
[Platinum](#platinum) platforms will have the `Mainline` option enabled by default, while [Bronze](#bronze) ones will fall back to `Vendor`.
> [!TIP]
> In `Mainline` mode with generic Linux kernels older than 6.13, the HDMI output will not be usable. To use the UEFI-initialized display instead, go to `Device Manager`->`Rockchip Platform Configuration`->`ACPI / Device Tree` and enable `Force UEFI GOP Display`. Note that GPU acceleration cannot work in this mode.
### Custom Device Tree Blob (DTB) override and overlays
It is also possible to provide a custom DTB and overlays. To enable this, go to `Device Manager`->`Rockchip Platform Configuration`->`ACPI / Device Tree` and set `Support DTB override & overlays` to `Enabled`.
The firmware will now look for overrides in the partition of a selected boot option / OS loader. In most cases, this will be the first FAT32 EFI System Partition.
**Important:** The `dtb` directory must be placed at the root of the partition. It should not be inside any sub-directory.
* The base DTB must be located at `\dtb\base\<PLATFORM-DT-NAME>.dtb`.
* The overlays can be placed in:
* `\dtb\overlays` - will be applied first, regardless of the platform.
* `\dtb\overlays\<PLATFORM-DT-NAME>` - will be applied only to the specified platform.
and must have the `.dtbo` extension.
`<PLATFORM-DT-NAME>` can be:
| Name | Platform |
| --------------------------------------- | ----------------------------- |
| `rk3588-rock-5b` | ROCK 5B |
| `rk3588-rock-5bp` | ROCK 5B+ |
| `rk3588s-rock-5a` | ROCK 5A |
| `rk3588-rock-5-itx` | ROCK 5 ITX |
| `rk3588s-orangepi-5` | Orange Pi 5 |
| `rk3588-orangepi-5-plus` | Orange Pi 5 Plus |
| `rk3588s-9tripod-linux` | Indiedroid Nova |
| `rk3588s-fydetab-duo` | Fydetab Duo |
| `rk3588-buzztv-p6` | PowerStation 6 |
| `aio-3588q` | Firefly AIO-3588Q |
| `itx-3588j` | Firefly ITX-3588J |
| `roc-rk3588s-pc` | ROC-RK3588S-PC / Station M3 |
| `rk3588-blueberry-edge-v12-linux` | R58X (v1.2) |
| `rk3588-blueberry-minipc-linux` | R58 Mini |
| `rk3588s-khadas-edge2` | Edge2 |
| `rk3588-blade3-v101-linux` | Blade 3 |
| `rk3588-nanopc-t6` | NanoPC T6 |
| `rk3588-nanopc-cm3588-nas` | NanoPC CM3588-NAS |
| `rk3588s-nanopi-r6c` | NanoPi R6C |
| `rk3588s-nanopi-r6s` | NanoPi R6S |
| `rk3588s-nanopi-m6` | NanoPi M6 |
| `rk3588-hinlink-h88k` | H88K |
In the absence of a custom base DTB override, the overlays are applied on top of the firmware-provided DTB.
The firmware applies some fix-ups to its own DTB depending on the user settings (e.g. PCIe/SATA/USB selection, making SATA overlays redundant). These fix-ups are not applied to a custom base DTB - overlays must be used instead.
If the application of an overlay fails (e.g. due to it being invalid in regard to the base DTB), all overlays are discarded, including those that got applied up to that point.
If the custom base DTB is invalid, the firmware-provided one will be passed to the OS instead.
This entire process is logged to the [serial console](#advanced-troubleshooting). There's currently no other way to see potential errors.
# Updating the firmware
If the storage is only used for UEFI and nothing else, simply download the latest image and flash it as described in the [Getting started](#getting-started) section.
If it is also used by an OS and has additional partitions, only part of the image needs to be applied. This can be done with the `dd` tool:
```bash
sudo pacman -Syu
sudo pacman -S git base-devel gcc dtc aarch64-linux-gnu-binutils aarch64-linux-gnu-gcc aarch64-linux-gnu-glibc python python-pyelftools iasl --needed
dd if=FIRMWARE.img of=DESTINATION bs=512 skip=64 seek=64 conv=notrunc
```
Required packages for Ubuntu/Debian:
`FIRMWARE.img` is the firmware image for your platform. E.g. `edge2_UEFI_Release_v0.8.img`.
`DESTINATION` is the destination storage that you wish to update the firmware on. E.g. `/dev/sdb`.
Here we skip the GPT and copy the firmware starting at offset 0x8000 (`64` blocks * `512` bytes block size) until its end. See [Flash layout](#flash-layout) for more details.
## Flash SPI NOR from the UEFI Shell
1) Copy the firmware image to a FAT32 partition on a storage drive and connect it to the device.
2) Launch the UEFI Shell (press <kbd>F1</kbd> during boot or go to `Boot Manager`->`UEFI Shell`).
3) Navigate to the partition / file system containing the firmware image:
* Use the `map` command to list all mounted file systems, e.g. `fs0:`, `fs1:`, etc. Type the file system name and press <kbd>Enter</kbd> to change directory to it.
* If you're unsure which file system to use, run `ls fsX:` (replace `X` with the actual number) to list its contents.
4) Run `sf updatefile FIRMWARE.img 0x0` and wait for the update process to complete.
5) Reboot the device.
# Troubleshooting
> [!IMPORTANT]
> First of all, make sure your device can only possibly load the UEFI firmware and nothing else.
>
> **U-Boot must not be present on either SPI NOR, SD or eMMC, otherwise it could take precedence and cause issues.**
Below you can find some basic debugging information. If none of this helps, please see the [Advanced troubleshooting](#advanced-troubleshooting) section.
## Meaning of the Status LED
If your device has an activity LED, the firmware will blink it in different patterns to indicate the current system status.
1. Immediately after power on, the LED should start pulsing quickly. This indicates that the firmware is initializing.
2. After initialization (usually takes less than 5 seconds), the LED will switch to a short pulsing every 2 seconds or so. This indicates that the firmware is ready and waiting for user action or the countdown to boot automatically. The display output should also be enabled at this point.
3. When the firmware boots an OS and is about to exit, the LED will stop blinking.
If the LED:
* does not light up after power on, this means the firmware has not managed to load up at all.
* gets stuck in either on or off state after blinking a few times and never recovers, something went wrong and the firmware has crashed or frozen.
Note that it is only expected to stop as described at point 3) above.
## Recovery
In case you don't have easy access to the MaskROM button, UEFI provides a boot option for that purpose, accessible either via the Boot Manager or <kbd>F4</kbd> key during splash screen.
Additionally, holding the Recovery (or volume up) button while powering on the device will also enter MaskROM mode.
## Common issues
### Nothing shows up on the screen
Make sure you've flashed the firmware correctly and that it is the version designed for your device. In most cases this is the culprit.
Assuming the firmware loads fine:
* The display must support a resolution of at least 640 x 480 at 60 Hz.
* Try booting without any display connected, then plug it in after a couple of seconds (when the status LED pattern changes). This will force the firmware to output at the minimum supported resolution. You can then increase the resolution by going to `Device Manager`->`Rockchip Platform Configuration`->`Display`.
* If you're using USB-C to DisplayPort, only one orientation of the USB-C connector will work. Check both.
If you are still not able to get any display output, the only way to interact with UEFI is via the [serial console](#advanced-troubleshooting).
### Configuration settings do not get saved
This has been observed in cases where firmware was present on more than one device (SPI NOR, eMMC or SD). This is not a supported scenario, because UEFI will be unable to accurately determine the boot device it belongs to. The solution is to unplug or erase devices that may have other firmware on them.
### USB 3 devices do not work
* Try a different port.
* If you're using USB-C, 3.0 devices will only work in one orientation of the connector. Check both.
* Make sure the power supply and cable are good.
### Networking does not work
* Only integrated Gigabit Ethernet (GMAC), Realtek PCIe and USB controllers are supported.
* Some boards with Realtek NICs do not have a MAC address set at factory and will show-up as being all zeros in UEFI, possibly preventing the adapter from obtaining an IP address.
You can easily fix this by writing the MAC address manually:
1. Boot into Linux and open up a terminal. The commands below apply to Armbian with legacy kernel.
2. Install the headers for your kernel version:
```bash
sudo apt install -y linux-headers-legacy-rk35xx
```
3. Clone Realtek PGTool and build the driver:
```bash
git clone https://github.com/redchenjs/rtnicpg
cd rtnicpg
make
```
4. Unload all Realtek modules and load the driver built above:
```bash
sudo rmmod pgdrv
sudo ./pgload.sh
```
Note: make sure there aren't any remaining Realtek modules loaded after this, except for the new `pgdrv`.<br> If you have `r8125` built-in, you might have to reboot with `initcall_blacklist=rtl8125_init_module` as a kernel parameter (in Grub).
5. Burn a MAC address into the eFuses:
For only one NIC:
```bash
sudo ./rtnicpg-aarch64-linux-gnu /efuse /nodeid 00E04C001234
```
For two or more:
```bash
sudo ./rtnicpg-aarch64-linux-gnu /efuse /# 1 /nodeid 00E04C001234
sudo ./rtnicpg-aarch64-linux-gnu /efuse /# 2 /nodeid 00E04C001235
```
`00E04C001234` is an example address. You can generate random and unique ones using: <https://www.macvendorlookup.com/mac-address-generator>
**Note:** the number of eFuses is limited, thus MAC addresses can only be changed a few times.
### Wi-Fi / Bluetooth not working on mainline Linux
The most likely cause is missing upstream firmware support. Check `dmesg` for messages that indicate firmware load errors.
This can usually be fixed by manually copying the necessary blobs to `/usr/lib/firmware`.
For instance, on Khadas Edge2 with an onboard AP6275P module (BCM/SYN43752):
```bash
sudo apt install git gcc g++ build-essential gcc-aarch64-linux-gnu iasl python3-pyelftools
sudo wget https://github.com/armbian/firmware/raw/refs/heads/master/brcm/brcmfmac43752-pcie.bin -P /usr/lib/firmware/brcm/
sudo wget https://github.com/armbian/firmware/raw/refs/heads/master/brcm/brcmfmac43752-pcie.clm_blob -P /usr/lib/firmware/brcm/
sudo wget https://github.com/armbian/firmware/raw/refs/heads/master/brcm/brcmfmac43752-pcie.txt -P /usr/lib/firmware/brcm/
sudo wget https://github.com/armbian/firmware/raw/refs/heads/master/brcm/BCM4362A2.hcd -P /usr/lib/firmware/brcm/
```
then reboot.
Clone the repository:
```bash
git clone https://github.com/edk2-porting/edk2-rk35xx.git --recursive
cd edk2-rk35xx
```
## Advanced troubleshooting
The firmware will log detailed information to the serial console when using a debug version. See the [release notes](https://github.com/edk2-porting/edk2-rk3588/releases) for details on how to obtain this version.
Build UEFI (ROCK 5B for example):
```bash
./build.sh -d rock-5b
```
1. The debug image needs to be flashed in place of the existing one.
## TODO
- Create gpt image in build process instead of using the prebuilt one
- Fix resetting to maskrom
2. Connect the **UART2** RX, TX and GND pins on your device (check vendor documentation) to the UART adapter on your other computer.
## Notes
3. Open up a serial terminal (`PuTTY` on Windows, `stty` on Linux) set to 1500000 baud rate and 8n1 (default).
### Flash layout
4. Power on the device.
You should be able to see many debug messages being printed to the console. If that's not the case, double check the connections (swap RX/TX), make sure the adapter is functional and configured correctly.
The logs should give an insight of what's going on. If you need help analyzing them, feel free to open an issue ticket.
# Reporting issues
You can open issues related to UEFI at <https://github.com/edk2-porting/edk2-rk3588/issues>.
Please include as many details as possible: expected behavior, what actually happens, steps to reproduce, [serial logs](#advanced-troubleshooting), etc.
Also check the existing issues in case yours might be already reported.
# Building
The firmware can only be built on Linux currently. For Windows use WSL.
1. Install required packages:
For Ubuntu/Debian:
```bash
sudo apt install git gcc g++ build-essential gcc-aarch64-linux-gnu acpica-tools python3-pyelftools uuid-dev python-is-python3 device-tree-compiler
```
For Arch Linux:
```bash
sudo pacman -Syu
sudo pacman -S git base-devel gcc dtc aarch64-linux-gnu-binutils aarch64-linux-gnu-gcc aarch64-linux-gnu-glibc python python-pyelftools iasl --needed
```
2. Clone the repository:
```bash
git clone https://github.com/edk2-porting/edk2-rk3588.git --recursive
cd edk2-rk3588
```
3. Build UEFI (ROCK 5B for example, check [list of platform configs](https://github.com/edk2-porting/edk2-rk3588/tree/master/configs)):
```bash
./build.sh --device rock-5b --release Release # (or Debug)
```
If you get build errors, it is very likely that you're still missing some dependencies. The list of packages above is not complete and depending on the distro you may need to install additional ones. In most cases, looking up the error messages on the internet will point you at the right packages.
# Notes
## Flash layout
| Address | Size | Desc | File |
| ---------- | :--------- | --------------------- | ---------------------- |
| ---------- | ---------- | --------------------- | ---------------------- |
| 0x00000000 | 0x00004400 | GPT Table | rk3588_spi_nor_gpt.img |
| 0x00008000 | | IDBlock | idblock.bin |
| 0x00088000 | | IDBlock | idblock.bin |
| 0x00100000 | 0x00500000 | BL33_AP_UEFI FV | ${DEVICE}_EFI.itb |
| 0x007C0000 | 0x00010000 | NV_VARIABLE_STORE | |
| 0x007D0000 | 0x00010000 | NV_FTW_WORKING header | |
| 0x007E0000 | 0x00010000 | NV_FTW_WORKING data | NV_DATA.img |
| 0x007D0000 | 0x00010000 | NV_FTW_WORKING | |
| 0x007E0000 | 0x00010000 | NV_FTW_SPARE | |
### Memory Map
The variable store is not included in the flash image, in order to prevent overwriting it and to maintain the user settings across updates.
| Address | Size | Desc | File |
| ---------- | :--: | ------------- | ------------------- |
| 0x00040000 | | ATF | bl31_0x00040000.bin |
| 0x000f0000 | | ATF | bl31_0x000f0000.bin |
| 0x00200000 | | UEFI FV | BL33_AP_UEFI.Fv |
| 0x08400000 | | OP-TEE | bl32.bin |
| 0xff100000 | | ATF (PMU_MEM) | bl31_0xff100000.bin |
The firmware expects these exact offsets, do not change them.
## Memory Map
| Address | Size | Desc | File |
| ---------- | --------- | --------------------- | ------------------- |
| 0x00040000 | | ATF | bl31_0x00040000.bin |
| 0x000f0000 | | ATF | bl31_0x000f0000.bin |
| 0x00200000 | 0x00500000 | UEFI FV | BL33_AP_UEFI.Fv |
| 0x007C0000 | 0x00010000 | NV_VARIABLE_STORE | |
| 0x007D0000 | 0x00010000 | NV_FTW_WORKING | |
| 0x007E0000 | 0x00010000 | NV_FTW_SPARE | |
| 0x08400000 | | OP-TEE | bl32.bin |
| 0xff100000 | | ATF (PMU_MEM) | bl31_0xff100000.bin |
## Licenses
Most of the UEFI code is licensed under the default EDK2 license, which is [BSD-2-Clause-Patent](https://github.com/tianocore/edk2/blob/master/License.txt).
Some components ported from Linux and Rockchip's U-Boot fork are licensed as **GPL-2.0** (check `SPDX-License-Identifier`).
The license for some of the blobs in the `misc/rkbin/` directory can be found at: <https://github.com/rockchip-linux/rkbin/blob/master/LICENSE>. Note that it also contains binaries built from open-source projects such as U-Boot (SPL), Arm Trusted Firmware and OP-TEE, having a different license.
## Community
* Hack w/ Rockchip Telegram: <https://t.me/UEFIonRockchip>
* Windows on R Discord: <https://discord.gg/vjHwptUCa3>
## Credits & alternatives
This firmware is based on Rockchip's initial efforts at <https://gitlab.com/rk3588_linux/rk/uefi-monorepo>.
For RK356x, check out the Quartz64-UEFI project at https://github.com/jaredmcneill/quartz64_uefi, from which we also reused some code.

1
arm-trusted-firmware Submodule

Submodule arm-trusted-firmware added at d5c68fd928

381
build.sh
View File

@@ -1,215 +1,256 @@
#!/bin/bash
function _help(){
echo "Usage: build.sh --device DEV"
echo
echo "Build edk2 for Rockchip RK35xx platforms."
echo
echo "Options: "
echo " --device DEV, -d DEV: build for DEV."
echo " --all, -a: build all devices."
echo " --release MODE, -r MODE: Release mode for building, default is 'DEBUG', 'RELEASE' alternatively."
echo " --toolchain TOOLCHAIN: Set toolchain, default is 'GCC5'."
echo " --skip-rootfs-gen: skip generating SimpleInit rootfs to speed up building."
echo " --clean, -C: clean workspace and output."
echo " --distclean, -D: clean up all files that are not in repo."
echo " --outputdir, -O: output folder."
echo " --help, -h: show this help."
echo
exit "${1}"
echo
echo "Build EDK2 for Rockchip RK3588 platforms."
echo
echo "Usage: build.sh [options]"
echo
echo "Options:"
echo " -d, --device DEV Build for DEV, or 'all'."
echo " -r, --release MODE Release mode for building, default is 'DEBUG', 'RELEASE' alternatively."
echo " -t, --toolchain TOOLCHAIN Set toolchain, default is 'GCC'."
echo " --open-tfa ENABLE Use open-source TF-A submodule. Default: ${OPEN_TFA}"
echo " -C, --clean Clean workspace and output."
echo " -D, --distclean Clean up all files that are not in repo."
echo " --tfa-flags \"FLAGS\" Flags appended to open TF-A build process."
echo " --edk2-flags \"FLAGS\" Flags appended to the EDK2 build process."
echo " -h, --help Show this help."
echo
exit "${1}"
}
function _error(){ echo "${@}" >&2;exit 1; }
function _error() { echo "${@}" >&2; exit 1; }
function _build_idblock(){
echo " => Building idblock.bin"
pushd ${WORKSPACE}
FLASHFILES="FlashHead.bin FlashData.bin FlashBoot.bin"
rm -f rk35*_spl_loader_*.bin idblock.bin rk35*_ddr_*.bin rk35*_usbplug*.bin UsbHead.bin ${FLASHFILES}
function _build_idblock() {
echo " => Building idblock.bin"
pushd ${WORKSPACE}
# Create idblock.bin
${ROOTDIR}/misc/rkbin/tools/mkimage -n rk3588 -T rksd -d ${ROOTDIR}/misc/rkbin/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.09.bin:${ROOTDIR}/misc/rkbin/bin/rk35/rk3588_spl_v1.11.bin idblock.bin
popd
echo " => idblock.bin build done"
FLASHFILES="FlashHead.bin FlashData.bin FlashBoot.bin"
rm -f rk35*_spl_loader_*.bin idblock.bin rk35*_ddr_*.bin rk35*_usbplug*.bin UsbHead.bin ${FLASHFILES}
DDRBIN_RKBIN=$(grep '^FlashData' ${ROOTDIR}/misc/rkbin/RKBOOT/${MINIALL_INI} | cut -d = -f 2-)
SPL_RKBIN=$(grep '^FlashBoot' ${ROOTDIR}/misc/rkbin/RKBOOT/${MINIALL_INI} | cut -d = -f 2-)
DDRBIN="${ROOTDIR}/misc/rkbin/${DDRBIN_RKBIN}"
#
# SPL v1.13 has broken SD card support!
# Use v1.12 instead.
#
# SPL="${ROOTDIR}/misc/rkbin/${SPL_RKBIN}"
SPL="${ROOTDIR}/misc/rk3588_spl_v1.12.bin"
# Create idblock.bin
${ROOTDIR}/misc/tools/${MACHINE_TYPE}/mkimage -n rk3588 -T rksd -d ${DDRBIN}:${SPL} idblock.bin
popd
echo " => idblock.bin build done"
}
function _build_fit(){
echo " => Building FIT"
pushd ${WORKSPACE}
BL31=$(grep '^PATH=.*_bl31_' ${ROOTDIR}/misc/rkbin/RKTRUST/${TRUST_INI} | cut -d = -f 2-)
BL32=$(grep '^PATH=.*_bl32_' ${ROOTDIR}/misc/rkbin/RKTRUST/${TRUST_INI} | cut -d = -f 2-)
rm -f bl31_0x*.bin ${WORKSPACE}/BL33_AP_UEFI.Fv ${SOC_L}_${DEVICE}_EFI.its
function _build_fit() {
echo " => Building FIT"
pushd ${WORKSPACE}
${ROOTDIR}/misc/extractbl31.py ${ROOTDIR}/misc/rkbin/${BL31}
cp ${ROOTDIR}/misc/rkbin/${BL32} ${WORKSPACE}/bl32.bin
cp ${ROOTDIR}/misc/${SOC_L}_spl.dtb ${WORKSPACE}/${DEVICE}.dtb
cp ${WORKSPACE}/Build/${PLATFORM_NAME}/${_MODE}_${TOOLCHAIN}/FV/BL33_AP_UEFI.Fv ${WORKSPACE}/
cat ${ROOTDIR}/misc/uefi_${SOC_L}.its | sed "s,@DEVICE@,${DEVICE},g" > ${SOC_L}_${DEVICE}_EFI.its
${ROOTDIR}/misc/rkbin/tools/mkimage -f ${SOC_L}_${DEVICE}_EFI.its -E ${DEVICE}_EFI.itb
BL31_RKBIN=$(grep '^PATH=.*_bl31_' ${ROOTDIR}/misc/rkbin/RKTRUST/${TRUST_INI} | cut -d = -f 2-)
BL32_RKBIN=$(grep '^PATH=.*_bl32_' ${ROOTDIR}/misc/rkbin/RKTRUST/${TRUST_INI} | cut -d = -f 2-)
popd
echo " => FIT build done"
BL31="${ROOTDIR}/misc/rkbin/${BL31_RKBIN}"
BL32="${ROOTDIR}/misc/rkbin/${BL32_RKBIN}"
if [ ${OPEN_TFA} == 1 ]; then
BL31="${ROOTDIR}/arm-trusted-firmware/build/${TFA_PLAT}/${RELEASE_TYPE,,}/bl31/bl31.elf"
fi
rm -f bl31_0x*.bin ${WORKSPACE}/BL33_AP_UEFI.Fv ${SOC_L}_${DEVICE}_EFI.its
${ROOTDIR}/misc/extractbl31.py ${BL31}
if [ ! -f bl31_0x000f0000.bin ]; then
# Not used but FIT expects it.
touch bl31_0x000f0000.bin
fi
cp ${BL32} ${WORKSPACE}/bl32.bin
cp ${ROOTDIR}/misc/${SOC_L}_spl.dtb ${WORKSPACE}/${DEVICE}.dtb
cp ${WORKSPACE}/Build/${PLATFORM_NAME}/${RELEASE_TYPE}_${TOOLCHAIN}/FV/BL33_AP_UEFI.Fv ${WORKSPACE}/
cat ${ROOTDIR}/misc/uefi_${SOC_L}.its | sed "s,@DEVICE@,${DEVICE},g" > ${SOC_L}_${DEVICE}_EFI.its
${ROOTDIR}/misc/tools/${MACHINE_TYPE}/mkimage -f ${SOC_L}_${DEVICE}_EFI.its -E ${DEVICE}_EFI.itb
popd
echo " => FIT build done"
}
function _pack(){
_build_idblock
_build_fit
function _pack_image() {
_build_idblock
_build_fit
echo " => Building 8MB NOR FLASH IMAGE"
cp ${WORKSPACE}/Build/${PLATFORM_NAME}/${_MODE}_${TOOLCHAIN}/FV/NOR_FLASH_IMAGE.fd ${WORKSPACE}/RK3588_NOR_FLASH.img
echo " => Building 8MB NOR FLASH IMAGE"
cp ${WORKSPACE}/Build/${PLATFORM_NAME}/${RELEASE_TYPE}_${TOOLCHAIN}/FV/NOR_FLASH_IMAGE.fd ${WORKSPACE}/RK3588_NOR_FLASH.img
# backup NV_DATA at 0x007C0000
dd if=${WORKSPACE}/RK3588_NOR_FLASH.img of=${WORKSPACE}/NV_DATA.img bs=1K skip=7936
# might be GPT table? size:0x4400
dd if=${ROOTDIR}/misc/rk3588_spi_nor_gpt.img of=${WORKSPACE}/RK3588_NOR_FLASH.img
# idblock at 0x8000 and 0x88000
dd if=${WORKSPACE}/idblock.bin of=${WORKSPACE}/RK3588_NOR_FLASH.img bs=1K seek=32
dd if=${WORKSPACE}/idblock.bin of=${WORKSPACE}/RK3588_NOR_FLASH.img bs=1K seek=544
# FIT Image at 0x100000
dd if=${WORKSPACE}/${DEVICE}_EFI.itb of=${WORKSPACE}/RK3588_NOR_FLASH.img bs=1K seek=1024
# restore NV_DATA at 0x007C0000
dd if=${WORKSPACE}/NV_DATA.img of=${WORKSPACE}/RK3588_NOR_FLASH.img bs=1K seek=7936
cp ${WORKSPACE}/RK3588_NOR_FLASH.img ${ROOTDIR}/
# GPT at 0x0, size:0x4400
dd if=${ROOTDIR}/misc/rk3588_spi_nor_gpt.img of=${WORKSPACE}/RK3588_NOR_FLASH.img
# idblock at 0x8000
dd if=${WORKSPACE}/idblock.bin of=${WORKSPACE}/RK3588_NOR_FLASH.img bs=1K seek=32
# FIT Image at 0x100000
dd if=${WORKSPACE}/${DEVICE}_EFI.itb of=${WORKSPACE}/RK3588_NOR_FLASH.img bs=1K seek=1024
cp ${WORKSPACE}/RK3588_NOR_FLASH.img ${ROOTDIR}/
}
function _build(){
local DEVICE="${1}"
shift
[ -d "${WORKSPACE}/Conf" ]||mkdir -p "${WORKSPACE}/Conf"
source "${ROOTDIR}/edk2/edksetup.sh"
[ -d "${WORKSPACE}" ]||mkdir "${WORKSPACE}"
set -x
make -C "${ROOTDIR}/edk2/BaseTools"||exit "$?"
local DEVICE="${1}"; shift
EXT=""
#
# Grab platform parameters
#
if [ -f "configs/${DEVICE}.conf" ]
then source "configs/${DEVICE}.conf"
else _error "Device configuration not found"
fi
if [ -f "configs/${SOC}.conf" ]
then source "configs/${SOC}.conf"
else _error "SoC configuration not found"
fi
typeset -l SOC_L="$SOC"
if [ -f "configs/${DEVICE}.conf" ]
then source "configs/${DEVICE}.conf"
else _error "Device configuration not found"
fi
if [ -f "configs/${SOC}.conf" ]
then source "configs/${SOC}.conf"
else _error "SoC configuration not found"
fi
typeset -l SOC_L="$SOC"
rm -f "${OUTDIR}/RK35*_NOR_FLASH.img"
# based on the instructions from edk2-platform
rm -f "${OUTDIR}/RK35*_NOR_FLASH.img"
#
# Build TF-A
#
if [ ${OPEN_TFA} == 1 ]; then
pushd arm-trusted-firmware
case "${MODE}" in
RELEASE) _MODE=RELEASE;;
*) _MODE=DEBUG;;
esac
if [ ${RELEASE_TYPE} == "DEBUG" ]; then
DEBUG=1
else
DEBUG=0
fi
build \
-s \
-n 0 \
-a AARCH64 \
-t "${TOOLCHAIN}" \
-p "${ROOTDIR}/${DSC_FILE}" \
-b "${_MODE}" \
-D FIRMWARE_VER="${GITCOMMIT}" \
||return "$?"
make PLAT=${TFA_PLAT} DEBUG=${DEBUG} all ${TFA_FLAGS}
_pack
set +x
popd
fi
echo "Build done: RK3588_NOR_FLASH.img"
#
# Build EDK2
#
[ -d "${WORKSPACE}/Conf" ] || mkdir -p "${WORKSPACE}/Conf"
export GCC_AARCH64_PREFIX="${CROSS_COMPILE}"
export CLANG38_AARCH64_PREFIX="${CROSS_COMPILE}"
export PACKAGES_PATH="${ROOTDIR}/edk2:${ROOTDIR}/edk2-rockchip:${ROOTDIR}/devicetree:${ROOTDIR}/edk2-non-osi:${ROOTDIR}"
make -C "${ROOTDIR}/edk2/BaseTools"
source "${ROOTDIR}/edk2/edksetup.sh"
build \
-s \
-n 0 \
-a AARCH64 \
-t "${TOOLCHAIN}" \
-p "${ROOTDIR}/${DSC_FILE}" \
-b "${RELEASE_TYPE}" \
-D FIRMWARE_VER="${GIT_COMMIT}" \
-D NETWORK_ALLOW_HTTP_CONNECTIONS=TRUE \
-D NETWORK_ISCSI_ENABLE=TRUE \
-D INCLUDE_TFTP_COMMAND=TRUE \
--pcd gRockchipTokenSpaceGuid.PcdFitImageFlashAddress=0x100000 \
${EDK2_FLAGS}
#
# Compile final image
#
_pack_image
echo "Build done: RK3588_NOR_FLASH.img"
}
function _clean(){ rm --one-file-system --recursive --force "${WORKSPACE}" "${OUTDIR}"/boot-*.img "${OUTDIR}"/uefi-*.img*; }
function _clean() { rm --one-file-system --recursive --force "${OUTDIR}"/workspace "${OUTDIR}"/RK3588_*.img; }
function _distclean() { if [ -d .git ]; then git clean -xdf; else _clean; fi; }
function _distclean(){ if [ -d .git ];then git clean -xdf;else _clean;fi; }
OUTDIR="${PWD}"
ROOTDIR="$(realpath "$(dirname "$0")")"
cd "${ROOTDIR}"||exit 1
#
# Default variables
#
typeset -l DEVICE
typeset -u MODE
typeset -u RELEASE_TYPE
DEVICE=""
MODE=DEBUG
RELEASE_TYPE=DEBUG
TOOLCHAIN=GCC
OPEN_TFA=1
TFA_FLAGS=""
EDK2_FLAGS=""
CLEAN=false
DISTCLEAN=false
TOOLCHAIN=GCC5
export ROOTDIR OUTDIR
export GEN_ROOTFS=true
OPTS="$(getopt -o t:d:haCDO:r -l toolchain:,device:,help,all,skip-rootfs-gen,clean,distclean,outputdir:,release: -n 'build.sh' -- "$@")"||exit 1
OUTDIR="${PWD}"
#
# Get options
#
OPTS=$(getopt -o "d:r:t:CDh" -l "device:,release:,toolchain:,open-tfa:,tfa-flags:,edk2-flags:,clean,distclean,help" -n build.sh -- "${@}") || _help $?
eval set -- "${OPTS}"
while true
do case "${1}" in
-d|--device) DEVICE="${2}";shift 2;;
-a|--all) DEVICE=all;shift;;
-C|--clean) CLEAN=true;shift;;
-D|--distclean) DISTCLEAN=true;shift;;
-O|--outputdir) OUTDIR="${2}";shift 2;;
--skip-rootfs-gen) GEN_ROOTFS=false;shift;;
-r|--release) MODE="${2}";shift 2;;
-t|--toolchain) TOOLCHAIN="${2}";shift 2;;
-h|--help) _help 0;shift;;
--) shift;break;;
*) _help 1;;
esac
while true; do
case "${1}" in
-d|--device) DEVICE="${2}"; shift 2 ;;
-r|--release) RELEASE_TYPE="${2}"; shift 2 ;;
-t|--toolchain) TOOLCHAIN="${2}"; shift 2 ;;
--open-tfa) OPEN_TFA="${2}"; shift 2 ;;
--tfa-flags) TFA_FLAGS="${2}"; shift 2 ;;
--edk2-flags) EDK2_FLAGS="${2}"; shift 2 ;;
-C|--clean) CLEAN=true; shift ;;
-D|--distclean) DISTCLEAN=true; shift ;;
-h|--help) _help 0; shift ;;
--) shift; break ;;
*) break ;;
esac
done
if "${DISTCLEAN}";then _distclean;exit "$?";fi
if "${CLEAN}";then _clean;exit "$?";fi
[ -z "${DEVICE}" ]&&_help 1
if ! [ -f Common/edk2/edksetup.sh ] && ! [ -f ../edk2/edksetup.sh ]
then
set -e
echo "SKIP Updating submodules"
set +e
if [[ -n "${@}" ]]; then
echo "Invalid additional arguments '${@}'"
_help 1
fi
for i in "${SIMPLE_INIT}" ./simple-init ../simple-init
do
if [ -n "${i}" ]&&[ -f "${i}/SimpleInit.inc" ]
then
_SIMPLE_INIT="$(realpath "${i}")"
break
fi
done
if "${DISTCLEAN}"; then _distclean; exit "$?"; fi
if "${CLEAN}"; then _clean; exit "$?"; fi
[ -n "${_SIMPLE_INIT}" ]||_error "SimpleInit not found, please see README.md"
[ -f "configs/${DEVICE}.conf" ]||_error "Device configuration not found"
[ -z "${DEVICE}" ] && _help 1
[ -f "configs/${DEVICE}.conf" ] || [ "${DEVICE}" == "all" ] || _error "Device configuration not found"
#
# Get machine architecture
#
MACHINE_TYPE=$(uname -m)
# Fix-up possible differences in reported arch
if [ ${MACHINE_TYPE} == 'arm64' ]; then
MACHINE_TYPE='aarch64'
elif [ ${MACHINE_TYPE} == 'amd64' ]; then
MACHINE_TYPE='x86_64'
fi
if [ ${MACHINE_TYPE} != 'aarch64' ]; then
export CROSS_COMPILE="${CROSS_COMPILE:-aarch64-linux-gnu-}"
fi
GIT_COMMIT="$(git describe --tags --always)" || GIT_COMMIT="unknown"
export CROSS_COMPILE="${CROSS_COMPILE:-aarch64-linux-gnu-}"
export GCC5_AARCH64_PREFIX="${CROSS_COMPILE}"
export CLANG38_AARCH64_PREFIX="${CROSS_COMPILE}"
# export PACKAGES_PATH="$_EDK2:$_EDK2_PLATFORMS:$_SIMPLE_INIT:$PWD"
export PACKAGES_PATH="${ROOTDIR}/edk2:${ROOTDIR}/edk2-platforms:${ROOTDIR}/edk2-non-osi:${ROOTDIR}:${_SIMPLE_INIT}"
export WORKSPACE="${OUTDIR}/workspace"
GITCOMMIT="$(git describe --tags --always)"||GITCOMMIT="unknown"
export GITCOMMIT
[ -d "${WORKSPACE}" ] || mkdir "${WORKSPACE}"
ROOTDIR="$(realpath "$(dirname "$0")")"
cd "${ROOTDIR}" || exit 1
# Exit on first error
set -e
mkdir -p "${_SIMPLE_INIT}/build" "${_SIMPLE_INIT}/root/usr/share/locale"
for i in "${_SIMPLE_INIT}/po/"*.po
do
[ -f "${i}" ]||continue
_name="$(basename "$i" .po)"
_path="${_SIMPLE_INIT}/root/usr/share/locale/${_name}/LC_MESSAGES"
mkdir -p "${_path}"
msgfmt -o "${_path}/simple-init.mo" "${i}"
done
if "${GEN_ROOTFS}"
then
bash "${_SIMPLE_INIT}/scripts/gen-rootfs-source.sh" \
"${_SIMPLE_INIT}" \
"${_SIMPLE_INIT}/build"
fi
if [ "${DEVICE}" == "all" ]
then
E=0
for i in configs/*.conf
do
DEV="$(basename "$i" .conf)"
echo "Building ${DEV}"
_build "${DEV}"||E="$?"
done
exit "${E}"
for i in configs/*.conf; do
DEV="$(basename "$i" .conf)"
if [ "${DEV}" != "RK3588" ]
then
echo "Building ${DEV}"
_build "${DEV}"
fi
done
else
_build "${DEVICE}"
_build "${DEVICE}"
fi

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@@ -1,2 +1,3 @@
MINIALL_INI=RK3588MINIALL.ini
TRUST_INI=RK3588TRUST.ini
TFA_PLAT=rk3588_reference_pmic

3
configs/aio-3588q.conf Normal file
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@@ -0,0 +1,3 @@
DSC_FILE=edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc
PLATFORM_NAME=AIO-3588Q
SOC=RK3588

3
configs/blade3.conf Normal file
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DSC_FILE=edk2-rockchip/Platform/Mixtile/Blade3/Blade3.dsc
PLATFORM_NAME=Blade3
SOC=RK3588

3
configs/edge2.conf Normal file
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@@ -0,0 +1,3 @@
DSC_FILE=edk2-rockchip/Platform/Khadas/Edge2/Edge2.dsc
PLATFORM_NAME=Edge2
SOC=RK3588

3
configs/fydetab-duo.conf Normal file
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DSC_FILE=edk2-rockchip/Platform/FydeInnovations/FydetabDuo/FydetabDuo.dsc
PLATFORM_NAME=FydetabDuo
SOC=RK3588

3
configs/h88k.conf Normal file
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DSC_FILE=edk2-rockchip/Platform/Hinlink/H88K/H88K.dsc
PLATFORM_NAME=H88K
SOC=RK3588

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DSC_FILE=edk2-rockchip/Platform/Ameridroid/IndiedroidNova/IndiedroidNova.dsc
PLATFORM_NAME=IndiedroidNova
SOC=RK3588

3
configs/itx-3588j.conf Normal file
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DSC_FILE=edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.dsc
PLATFORM_NAME=ITX-3588J
SOC=RK3588

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DSC_FILE=edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/NanoPC-CM3588-NAS.dsc
PLATFORM_NAME=NanoPC-CM3588-NAS
SOC=RK3588

3
configs/nanopc-t6.conf Normal file
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DSC_FILE=edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/NanoPC-T6.dsc
PLATFORM_NAME=NanoPC-T6
SOC=RK3588

3
configs/nanopi-m6.conf Normal file
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DSC_FILE=edk2-rockchip/Platform/FriendlyElec/NanoPi-M6/NanoPi-M6.dsc
PLATFORM_NAME=NanoPi-M6
SOC=RK3588

3
configs/nanopi-r6c.conf Normal file
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DSC_FILE=edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/NanoPi-R6C.dsc
PLATFORM_NAME=NanoPi-R6C
SOC=RK3588

3
configs/nanopi-r6s.conf Normal file
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DSC_FILE=edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/NanoPi-R6S.dsc
PLATFORM_NAME=NanoPi-R6S
SOC=RK3588

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@@ -1,3 +1,3 @@
DSC_FILE=edk2-platforms/Platform/OrangePi/OrangePi5/OrangePi5.dsc
DSC_FILE=edk2-rockchip/Platform/OrangePi/OrangePi5/OrangePi5.dsc
PLATFORM_NAME=OrangePi5
SOC=RK3588

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DSC_FILE=edk2-rockchip/Platform/OrangePi/OrangePi5Plus/OrangePi5Plus.dsc
PLATFORM_NAME=OrangePi5Plus
SOC=RK3588

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DSC_FILE=edk2-rockchip/Platform/BuzzTV/PowerStation6/PowerStation6.dsc
PLATFORM_NAME=PowerStation6
SOC=RK3588

3
configs/r58-mini.conf Normal file
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DSC_FILE=edk2-rockchip/Platform/Mekotronics/R58-Mini/R58-Mini.dsc
PLATFORM_NAME=R58-Mini
SOC=RK3588

3
configs/r58x.conf Normal file
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DSC_FILE=edk2-rockchip/Platform/Mekotronics/R58X/R58X.dsc
PLATFORM_NAME=R58X
SOC=RK3588

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DSC_FILE=edk2-platforms/Platform/Rockchip/RK3588/RK3588.dsc
PLATFORM_NAME=RK3588
SOC=RK3588

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DSC_FILE=edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc
PLATFORM_NAME=ROC-RK3588S-PC
SOC=RK3588

3
configs/rock-5-itx.conf Normal file
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DSC_FILE=edk2-rockchip/Platform/Radxa/ROCK5ITX/ROCK5ITX.dsc
PLATFORM_NAME=ROCK5ITX
SOC=RK3588

3
configs/rock-5a.conf Normal file
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DSC_FILE=edk2-rockchip/Platform/Radxa/ROCK5A/ROCK5A.dsc
PLATFORM_NAME=ROCK5A
SOC=RK3588

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@@ -1,3 +1,3 @@
DSC_FILE=edk2-platforms/Platform/Radxa/ROCK5B/ROCK5B.dsc
DSC_FILE=edk2-rockchip/Platform/Radxa/ROCK5B/ROCK5B.dsc
PLATFORM_NAME=ROCK5B
SOC=RK3588

3
configs/rock-5bplus.conf Normal file
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DSC_FILE=edk2-rockchip/Platform/Radxa/ROCK5BPlus/ROCK5BPlus.dsc
PLATFORM_NAME=ROCK5BPlus
SOC=RK3588

3
configs/station-m3.conf Normal file
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DSC_FILE=edk2-rockchip/Platform/StationPC/StationM3/StationM3.dsc
PLATFORM_NAME=StationM3
SOC=RK3588

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# Rockchip Mainline Device Trees
New board files, small additions and fixes reusing existing bindings are accepted here, but only as a stopgap until they get merged upstream.

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2024, Mario Bălănică <mariobalanica02@gmail.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include <dt-bindings/usb/pd.h>
#include "rk3588.dtsi"
/ {
model = "BuzzTV P6";
compatible = "buzztv,p6", "rockchip,rk3588";
aliases {
ethernet0 = &gmac1;
mmc0 = &sdhci;
mmc1 = &sdmmc;
};
chosen {
stdout-path = "serial2:1500000n8";
};
hdmi0-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi0_con_in: endpoint {
remote-endpoint = <&hdmi0_out_con>;
};
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins>;
green_led: led-0 {
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_LOW>;
default-state = "on";
};
red_led: led-1 {
color = <LED_COLOR_ID_RED>;
gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
};
};
ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ir_receiver_pin>;
};
vcc12v_dcin: regulator-vcc12v-dcin {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc5v0_sys: regulator-vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_usb: regulator-vcc5v0-usb {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_host: regulator-vcc5v0-host {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
vin-supply = <&vcc5v0_usb>;
};
vbus5v0_typec: regulator-vbus5v0-typec {
compatible = "regulator-fixed";
regulator-name = "vbus5v0_typec";
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&typec5v_pwren>;
vin-supply = <&vcc5v0_usb>;
};
vcc3v3_pcie30: regulator-vcc3v3-pcie30 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie30";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie3_vcc3v3_en>;
startup-delay-us = <5000>;
vin-supply = <&vcc5v0_sys>;
};
vcc_3v3_sd_s0: regulator-vcc-3v3-sd-s0 {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_sd_s0";
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
enable-active-high;
gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&sd_s0_pwr>;
vin-supply = <&vcc_3v3_s3>;
};
vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v1_nldo_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
vin-supply = <&vcc5v0_sys>;
};
};
&combphy1_ps {
status = "okay";
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_big0_s0>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_big0_s0>;
};
&cpu_b2 {
cpu-supply = <&vdd_cpu_big1_s0>;
};
&cpu_b3 {
cpu-supply = <&vdd_cpu_big1_s0>;
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
&gpu {
mali-supply = <&vdd_gpu_s0>;
status = "okay";
};
&hdmi0 {
status = "okay";
};
&hdmi0_in {
hdmi0_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi0>;
};
};
&hdmi0_out {
hdmi0_out_con: endpoint {
remote-endpoint = <&hdmi0_con_in>;
};
};
&hdptxphy_hdmi0 {
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0m2_xfer>;
status = "okay";
vdd_cpu_big0_s0: regulator@42 {
compatible = "rockchip,rk8602";
reg = <0x42>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu_big0_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_big1_s0: regulator@43 {
compatible = "rockchip,rk8603", "rockchip,rk8602";
reg = <0x43>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu_big1_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1m2_xfer>;
status = "okay";
vdd_npu_s0: regulator@42 {
compatible = "rockchip,rk8602";
reg = <0x42>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_npu_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c6 {
status = "okay";
fusb302: typec-portc@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&usbc0_int>;
vbus-supply = <&vbus5v0_typec>;
usb_con: connector {
compatible = "usb-c-connector";
data-role = "dual";
label = "USB-C";
power-role = "source";
source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usbc0_orien_sw: endpoint {
remote-endpoint = <&usbdp_phy0_orientation_switch>;
};
};
port@1 {
reg = <1>;
usbc0_role_sw: endpoint {
remote-endpoint = <&dwc3_0_role_switch>;
};
};
port@2 {
reg = <2>;
dp_altmode_mux: endpoint {
remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
};
};
};
};
};
hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-output-names = "hym8563";
pinctrl-names = "default";
pinctrl-0 = <&hym8563_int>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
};
/* RTL8852BE */
&pcie2x1l0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie2_0_rst>;
reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&pcie30phy {
/*
* pcie3x4 is limited to 3x2 and requires x2 x2 PHY bifurcation to work.
* pcie3x2, however, is unused and needs to remain disabled.
*/
data-lanes = <1 1 2 2>;
status = "okay";
};
/* M.2 M key */
&pcie3x4 {
pinctrl-names = "default";
pinctrl-0 = <&pcie3_rst>;
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie30>;
status = "okay";
};
&gmac1 {
clock_in_out = "output";
phy-handle = <&rgmii_phy1>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&gmac1_miim
&gmac1_tx_bus2
&gmac1_rx_bus2
&gmac1_rgmii_clk
&gmac1_rgmii_bus>;
rx_delay = <0x00>;
tx_delay = <0x43>;
status = "okay";
};
&mdio1 {
/* RTL8211F */
rgmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id001c.c916";
reg = <0x1>;
pinctrl-names = "default";
pinctrl-0 = <&rtl8211f_rst>;
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
};
};
&pinctrl {
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
leds {
led_pins: led-pins {
rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>,
<3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
ir-receiver {
ir_receiver_pin: ir-receiver-pin {
rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie2 {
pcie2_0_rst: pcie2-0-rst {
rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie3 {
pcie3_rst: pcie3-rst {
rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
pcie3_vcc3v3_en: pcie3-vcc3v3-en {
rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
rtl8211f {
rtl8211f_rst: rtl8211f-rst {
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb-typec {
usbc0_int: usbc0-int {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
};
typec5v_pwren: typec5v-pwren {
rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdmmc {
sd_s0_pwr: sd-s0-pwr {
rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
bluetooth {
bt_reset: bt-reset {
rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_host_wake: bt-host-wake {
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_dev_wake: bt-dev-wake {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&saradc {
vref-supply = <&avcc_1v8_s0>;
status = "okay";
};
&sdhci {
bus-width = <8>;
no-sdio;
no-sd;
non-removable;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
status = "okay";
};
&sdmmc {
max-frequency = <200000000>;
no-sdio;
no-mmc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
disable-wp;
sd-uhs-sdr104;
vmmc-supply = <&vcc_3v3_sd_s0>;
vqmmc-supply = <&vccio_sd_s0>;
status = "okay";
};
&spi2 {
status = "okay";
assigned-clocks = <&cru CLK_SPI2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
num-cs = <1>;
pmic@0 {
compatible = "rockchip,rk806";
spi-max-frequency = <1000000>;
reg = <0x0>;
interrupt-parent = <&gpio0>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
system-power-controller;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc5-supply = <&vcc5v0_sys>;
vcc6-supply = <&vcc5v0_sys>;
vcc7-supply = <&vcc5v0_sys>;
vcc8-supply = <&vcc5v0_sys>;
vcc9-supply = <&vcc5v0_sys>;
vcc10-supply = <&vcc5v0_sys>;
vcc11-supply = <&vcc_2v0_pldo_s3>;
vcc12-supply = <&vcc5v0_sys>;
vcc13-supply = <&vcc_1v1_nldo_s3>;
vcc14-supply = <&vcc_1v1_nldo_s3>;
vcca-supply = <&vcc5v0_sys>;
gpio-controller;
#gpio-cells = <2>;
rk806_dvs1_null: dvs1-null-pins {
pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
rk806_dvs2_null: dvs2-null-pins {
pins = "gpio_pwrctrl2";
function = "pin_fun0";
};
rk806_dvs3_null: dvs3-null-pins {
pins = "gpio_pwrctrl3";
function = "pin_fun0";
};
regulators {
vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_gpu_s0";
regulator-enable-ramp-delay = <400>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_cpu_lit_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_log_s0: dcdc-reg3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <750000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_log_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <750000>;
};
};
vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_vdenc_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_ddr_s0: dcdc-reg5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <900000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_ddr_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <850000>;
};
};
vdd2_ddr_s3: dcdc-reg6 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vdd2_ddr_s3";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_2v0_pldo_s3: dcdc-reg7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2000000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_2v0_pldo_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <2000000>;
};
};
vcc_3v3_s3: dcdc-reg8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_3v3_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vddq_ddr_s0: dcdc-reg9 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vddq_ddr_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8_s3: dcdc-reg10 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
avcc_1v8_s0: pldo-reg1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "avcc_1v8_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8_s0: pldo-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
avdd_1v2_s0: pldo-reg3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "avdd_1v2_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v3_s0: pldo-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <12500>;
regulator-name = "vcc_3v3_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd_s0: pldo-reg5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <12500>;
regulator-name = "vccio_sd_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
pldo6_s3: pldo-reg6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "pldo6_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_0v75_s3: nldo-reg1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "vdd_0v75_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <750000>;
};
};
vdd_ddr_pll_s0: nldo-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-name = "vdd_ddr_pll_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <850000>;
};
};
avdd_0v75_s0: nldo-reg3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "avdd_0v75_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_0v85_s0: nldo-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-name = "vdd_0v85_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_0v75_s0: nldo-reg5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "vdd_0v75_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
};
&tsadc {
status = "okay";
};
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
&uart9 {
pinctrl-names = "default";
pinctrl-0 = <&uart9m0_xfer>, <&uart9m0_rtsn>, <&uart9m0_ctsn>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "realtek,rtl8852bs-bt", "realtek,rtl8822cs-bt";
enable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
host-wake-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
device-wake-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bt_reset>, <&bt_host_wake>, <&bt_dev_wake>;
};
};
&u2phy0 {
status = "okay";
};
&u2phy0_otg {
status = "okay";
};
&u2phy1 {
status = "okay";
};
&u2phy1_otg {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&u2phy2 {
status = "okay";
};
&u2phy2_host {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&usbdp_phy0 {
mode-switch;
orientation-switch;
sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
usbdp_phy0_orientation_switch: endpoint@0 {
reg = <0>;
remote-endpoint = <&usbc0_orien_sw>;
};
usbdp_phy0_dp_altmode_mux: endpoint@1 {
reg = <1>;
remote-endpoint = <&dp_altmode_mux>;
};
};
};
&usbdp_phy1 {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
/* Front USB Type-C port */
&usb_host0_xhci {
usb-role-switch;
status = "okay";
port {
dwc3_0_role_switch: endpoint {
remote-endpoint = <&usbc0_role_sw>;
};
};
};
/* Front USB 2.0 port */
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
/* Front USB 3.0 port */
&usb_host1_xhci {
dr_mode = "host";
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vop {
status = "okay";
};
&vp0 {
vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi0_in_vp0>;
};
};

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@@ -0,0 +1,33 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk3588-rock-5-itx.dts"
/ {
/delete-node/ pcie-oscillator;
};
/*
* Remove the "pcie30_refclk" gated-fixed-clock to maintain compatibility
* with kernels older than v6.13-rc1. It is backed by a GPIO regulator
* anyway, so simply referencing it in vpcie3v3-supply also addresses
* the potential issue where pcie3x2 might probe earlier than pcie3x4 and
* hang on DBI access because the clock didn't have a chance to be enabled.
*/
&pcie3x2 {
clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
<&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
<&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk",
"aux", "pipe";
vpcie3v3-supply = <&vcc3v3_pi6c_05>;
};
&pcie3x4 {
clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
<&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
<&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk",
"aux", "pipe";
};

View File

@@ -0,0 +1,271 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include <dt-bindings/soc/rockchip,vop2.h>
#include <dt-bindings/usb/pd.h>
#include "rk3588s-khadas-edge2.dts"
/ {
analog-sound {
compatible = "audio-graph-card";
label = "rk3588-es8316";
widgets = "Microphone", "Mic Jack",
"Headphone", "Headphones";
routing = "MIC2", "Mic Jack",
"Headphones", "HPOL",
"Headphones", "HPOR";
dais = <&i2s0_8ch_p0>;
hp-det-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hp_detect>;
};
hdmi0-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi0_con_in: endpoint {
remote-endpoint = <&hdmi0_out_con>;
};
};
};
vbus5v0_typec: regulator-vbus5v0-typec {
compatible = "regulator-fixed";
regulator-name = "vbus5v0_typec";
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&typec5v_pwren>;
vin-supply = <&vcc5v0_sys>;
};
};
&i2c2 {
fusb302: typec-portc@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PB5 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&usbc0_int>;
vbus-supply = <&vbus5v0_typec>;
usb_con: connector {
compatible = "usb-c-connector";
data-role = "dual";
label = "USB-C";
power-role = "dual";
try-power-role = "source";
op-sink-microwatt = <1000000>;
sink-pdos =
<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_FIXED(9000, 3000, PDO_FIXED_USB_COMM)
PDO_FIXED(12000, 3000, PDO_FIXED_USB_COMM)>;
source-pdos =
<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usbc0_orien_sw: endpoint {
remote-endpoint = <&usbdp_phy0_orientation_switch>;
};
};
port@1 {
reg = <1>;
usbc0_role_sw: endpoint {
remote-endpoint = <&dwc3_0_role_switch>;
};
};
port@2 {
reg = <2>;
dp_altmode_mux: endpoint {
remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
};
};
};
};
};
};
&i2c3 {
status = "okay";
es8316: audio-codec@10 {
compatible = "everest,es8316";
reg = <0x10>;
clocks = <&cru I2S0_8CH_MCLKOUT>;
clock-names = "mclk";
assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
assigned-clock-rates = <12288000>;
#sound-dai-cells = <0>;
port {
es8316_p0_0: endpoint {
remote-endpoint = <&i2s0_8ch_p0_0>;
};
};
};
};
&i2s0_8ch {
pinctrl-names = "default";
pinctrl-0 = <&i2s0_lrck
&i2s0_mclk
&i2s0_sclk
&i2s0_sdi0
&i2s0_sdo0>;
status = "okay";
i2s0_8ch_p0: port {
i2s0_8ch_p0_0: endpoint {
dai-format = "i2s";
mclk-fs = <256>;
remote-endpoint = <&es8316_p0_0>;
};
};
};
&pinctrl {
usb-typec {
usbc0_int: usbc0-int {
rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
};
typec5v_pwren: typec5v-pwren {
rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sound {
hp_detect: hp-detect {
rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
bluetooth {
bt_reset: bt-reset {
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_dev_wake: bt-dev-wake {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_host_wake: bt-host-wake {
rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};
&uart9 {
pinctrl-names = "default";
pinctrl-0 = <&uart9m2_xfer>, <&uart9m2_rtsn>, <&uart9m2_ctsn>;
uart-has-rtscts;
bluetooth {
compatible = "brcm,bcm43752-bt", "cypress,cyw4373a0-bt";
max-speed = <4000000>;
clocks = <&hym8563>;
clock-names = "lpo";
shutdown-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
device-wakeup-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PD5 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wakeup";
pinctrl-names = "default";
pinctrl-0 = <&bt_reset>, <&bt_dev_wake>, <&bt_host_wake>;
};
};
&u2phy0 {
status = "okay";
};
&u2phy0_otg {
status = "okay";
};
&usbdp_phy0 {
mode-switch;
orientation-switch;
sbu1-dc-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>;
sbu2-dc-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>;
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
usbdp_phy0_orientation_switch: endpoint@0 {
reg = <0>;
remote-endpoint = <&usbc0_orien_sw>;
};
usbdp_phy0_dp_altmode_mux: endpoint@1 {
reg = <1>;
remote-endpoint = <&dp_altmode_mux>;
};
};
};
&usb_host0_xhci {
usb-role-switch;
status = "okay";
port {
dwc3_0_role_switch: endpoint {
remote-endpoint = <&usbc0_role_sw>;
};
};
};
&hdmi0 {
status = "okay";
};
&hdmi0_in {
hdmi0_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi0>;
};
};
&hdmi0_out {
hdmi0_out_con: endpoint {
remote-endpoint = <&hdmi0_con_in>;
};
};
&hdptxphy_hdmi0 {
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vop {
status = "okay";
};
&vp0 {
vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi0_in_vp0>;
};
};

20
devicetree/vendor/README.md vendored Normal file
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@@ -0,0 +1,20 @@
# Rockchip Vendor BSP Device Trees
## Sources
* <https://github.com/armbian/linux-rockchip/tree/f3fb30ac9de06b41fb621d17bc53603f1f48ac90/arch/arm64/boot/dts/rockchip>
* Updated to `rk-6.1-rkr1` branch, currently called `vendor` branch in armbian/build
* roc-rk3588s-pc: <https://gitlab.com/firefly-linux/kernel/-/tree/b8646da2122f45a2c02082d949427b80d2e89b1f/arch/arm64/boot/dts/rockchip>
* itx-3588j: <https://gitlab.com/firefly-linux/kernel/-/tree/e14c28295dd7ee8f807899e9b0b7da5f79742e4f/arch/arm64/boot/dts/rockchip>
(note: in the dtb given here, the builtin bootargs in the source above were commented out
before building. Not sure if that was a necessary step - SS)
* rk3588-firefly-aio-3588q: <https://gitlab.com/firefly-linux/kernel/-/tree/fa0e053fd911339b825407cb6d4b167fad7cdc49/arch/arm64/boot/dts/rockchip>
* rk3588-rock-5b-plus: <https://github.com/radxa/kernel/blob/3b95df6d8bf567857b69e5266f1cb0651a6cfb3e/arch/arm64/boot/dts/rockchip/>
* rk3588s-fydetab-duo: <https://github.com/Linux-for-Fydetab-Duo/linux-rockchip/tree/14294048d2a0deb7f38c890329aded87038d3299/arch/arm64/boot/dts/rockchip>
(note: dtb taken from the `noble` branch which is based on the rockchip 6.1 rkr3 bsp kernel)
## License
SPDX-License-Identifier: GPL-2.0-only

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1
edk2 Submodule

Submodule edk2 added at fbe0805b20

1
edk2-non-osi Submodule

Submodule edk2-non-osi added at ea2040c2d4

View File

@@ -1,23 +0,0 @@
## @file
# Component description file for ASPEED Graphics Controller Driver.
#
# Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2020, ASPEED Technology Inc. All rights reserved.<BR>
# Copyright (c) 2021, American Megatrends International LLC.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x0001001B
BASE_NAME = ASpeedAst2500GopDxe
FILE_GUID = 7F81D838-F91D-4C44-8552-8FB912122FDD
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.1
[Binaries.AArch64]
PE32|AArch64/ASpeedAst2500Gop.efi|*
[Binaries.X64]
PE32|X64/ASpeedAst2500Gop.efi|*

View File

@@ -1,25 +0,0 @@
Copyright (c) 2020, ASPEED Technology Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.

View File

@@ -1,24 +0,0 @@
#/** @file
#
# Copyright (c) 2020 Realtek Semiconductor Corp. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
[Defines]
INF_VERSION = 1.27
BASE_NAME = RtkUsbUndiDxe
FILE_GUID = 2EB8953E-C191-4A5E-B2AC-705EFB14A613
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
[Binaries.AARCH64]
PE32|AArch64/RtkUsbUndiDxe.efi|*

View File

@@ -1,25 +0,0 @@
Copyright (c) 2020 Realtek Semiconductor Corp. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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@@ -1,504 +0,0 @@
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That's all there is to it!

View File

@@ -1,7 +0,0 @@
Binary build of the QEMU based x86 PE/COFF emulator for AARCH64
Repo: http://github.com/ardbiesheuvel/X86EmulatorPkg.git
Commit: 5f4deb30eb935f9004b93d97712cc3ac3ae1ca97
Repo: http://github.com/tiancore/edk2.git
Commit: 2e21e8c4b89656897797019a9c56bc5ccbf12df1

View File

@@ -1,21 +0,0 @@
#/** @file
#
# Copyright (c) 2017 - 2019, Linaro Limited. All rights reserved.
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2 of the License, or (at your option) any later version.
#
#**/
[Defines]
INF_VERSION = 1.27
BASE_NAME = X86EmulatorDxe
FILE_GUID = E6727A5E-CBCD-44C8-B37F-78BC3A0C16C8
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
[Binaries.common.AARCH64]
PE32|X86EmulatorDxe.efi|*
DXE_DEPEX|X86EmulatorDxe.depex|*

View File

@@ -1,88 +0,0 @@
EDK II Maintainers
==================
This file provides information about the primary maintainers for
EDK II.
In general, you should not privately email the maintainer. You should
email the edk2-devel list, but you can also Cc the maintainer.
Descriptions of section entries:
L: Mailing list that is relevant to this area (default is edk2-devel)
Patches and questions should be sent to the email list.
M: Cc address for patches and questions (ie, the package maintainer)
W: Web-page with status/info
T: SCM tree type and location. Type is one of: git, svn.
S: Status, one of the following:
Supported: Someone is actually paid to look after this.
Maintained: Someone actually looks after it.
Odd Fixes: It has a maintainer but they don't have time to do
much other than throw the odd patch in. See below.
Orphan: No current maintainer [but maybe you could take the
role as you write your new code].
Obsolete: Old code. Something tagged obsolete generally means
it has been replaced by a better system and you
should be using that.
EDK II
------
W: http://www.tianocore.org/edk2/
L: https://lists.sourceforge.net/lists/listinfo/edk2-devel
T: git - https://github.com/tianocore/edk2-non-osi.git
T: git - https://bitbucket.org/tianocore/edk2-non-osi.git
T: git - http://git.code.sf.net/p/tianocore/edk2-non-osi
T: svn - https://svn.code.sf.net/p/edk2/code/trunk/edk2-non-osi
Responsible Disclosure, Reporting Security Issues
-------------------------------------------------
W: https://github.com/tianocore/tianocore.github.io/wiki/Security
EDK II Packages:
----------------
Platform/Intel/KabylakeOpenBoardBinPkg
M: Chasel Chiu <chasel.chiu@intel.com>
M: Nate DeSimone <nathaniel.l.desimone@intel.com>
Platform/Intel/WhitleyOpenBoardBinPkg
M: Isaac Oram <isaac.w.oram@intel.com>
M: Nate DeSimone <nathaniel.l.desimone@intel.com>
M: Chasel Chiu <chasel.chiu@intel.com>
Platform/Intel/CoffeelakeSiliconBinPkg
M: Chasel Chiu <chasel.chiu@intel.com>
M: Sai Chaganty <rangasai.v.chaganty@intel.com>
Platform/Intel/CometlakeSiliconBinPkg
M: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
M: Sai Chaganty <rangasai.v.chaganty@intel.com>
Silicon/Intel/ElkhartlakeSiliconBinPkg
M: Nate DeSimone <nathaniel.l.desimone@intel.com>
M: Sai Chaganty <rangasai.v.chaganty@intel.com>
M: Jin Jhu Lim <jin.jhu.lim@intel.com>
Silicon/Intel/KabylakeSiliconBinPkg
M: Chasel Chiu <chasel.chiu@intel.com>
M: Sai Chaganty <rangasai.v.chaganty@intel.com>
Silicon/Intel/PurleySiliconBinPkg
M: Nate DeSimone <nathaniel.l.desimone@intel.com>
M: Isaac W Oram <isaac.w.oram@intel.com>
Silicon/Intel/WhitleySiliconBinPkg
M: Nate DeSimone <nathaniel.l.desimone@intel.com>
M: Isaac W Oram <isaac.w.oram@intel.com>
Silicon/Intel/QuarkSocBinPkg
M: Michael D Kinney <michael.d.kinney@intel.com>
M: Kelly Steele <kelly.steele@intel.com>
Silicon/Intel/Vlv2SocBinPkg
M: Zailiang Sun <zailiang.sun@intel.com>
M: Yi Qian <yi.qian@intel.com>
Silicon/Intel/TigerlakeSiliconBinPkg
M: Sai Chaganty <rangasai.v.chaganty@intel.com>
M: Nate DeSimone <nathaniel.l.desimone@intel.com>

View File

@@ -1,25 +0,0 @@
Copyright (c) 2013 - 2016, AMD Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.

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@@ -1,361 +0,0 @@
From http://community.arm.com/docs/DOC-8402, dated 4 Jul 2014.
Juno Software EULA
THIS END USER LICENCE AGREEMENT ("LICENCE") IS A LEGAL AGREEMENT BETWEEN YOU
(EITHER A SINGLE INDIVIDUAL, OR SINGLE LEGAL ENTITY) AND ARM LIMITED ("ARM") FOR
THE USE OF THE DELIVERABLES ACCOMPANYING THIS LICENCE. ARM IS ONLY WILLING TO
LICENSE THE DELIVERABLES TO YOU ON CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN
THIS LICENCE. BY CLICKING "I AGREE" OR BY INSTALLING OR OTHERWISE USING OR
COPYING THE DELIVERABLES YOU INDICATE THAT YOU AGREE TO BE BOUND BY ALL THE
TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE TERMS OF THIS LICENCE, ARM IS
UNWILLING TO LICENSE THE DELIVERABLES TO YOU AND YOU MAY NOT INSTALL, USE OR
COPY THE DELIVERABLES, BUT YOU SHOULD PROMPTLY RETURN THE DELIVERABLES TO YOUR
SUPPLIER AND ASK FOR A REFUND OF ANY LICENCE FEE PAID.
"Juno ARM Development Platform" means a hardware development board purchased
directly from ARM or its authorised distributors.
"Deliverables" means any software, firmware, boardfiles, data and documentation
accompanying this Licence, any printed, electronic or online documentation
supplied with it, and any updates, patches and modifications ARM may make
available to you under the terms of this Licence, in all cases relating to the
supporting deliverables for the Juno ARM Development Platform
"Separate Files" means the separate files identified in Part D of the Schedule.
1. LICENCE GRANTS.
(i) DELIVERABLES: ARM hereby grants to you, subject to the terms and conditions
of this Licence, a non-exclusive, non-transferable licence solely for use on a
Juno ARM Development Platform and only for the purposes of your internal
development, testing and debugging of software applications that are designed to
run solely on microprocessors manufactured under licence from ARM, to:
(a) use and copy the Deliverables identified in Part A of the Schedule;
(b) use, copy and modify the Deliverables identified in Part B and Part C of the
Schedule;
(c) distribute and sub-license to third parties the right to use, copy and
modify the Deliverables identified in Part C(i) of the Schedule, or your
derivatives thereof, as part of your own products ("Licensed Products")
provided you comply with the terms of Clause 1(ii);
(d) permit either or both your customers and your authorised distributors to
redistribute the Deliverables identified in Part C(i) of the Schedule, or your
derivatives thereof, solely as part of Licensed Products developed by you or
your permitted users (identified in clause 2 paragraph three below).
Except as permitted by clause 1(i)(b) above, you shall not modify the
Deliverables. Except as permitted by clauses 1(i)(c) and 1(i)(d) above, you
shall not redistribute any of the Deliverables.
(ii) FURTHER CONDITIONS APPLICABLE TO REDISTRIBUTION AND SUB-LICENSING: If you
choose to redistribute the Deliverables identified in Part C(i) of the Schedule
("Example Code") you agree: (a) to ensure that they are licensed for use only as
part of Licensed Products and only on microprocessors manufactured or simulated
under licence from ARM; (b) not to use ARMs or any of its licensors names,
logos or trademarks to market the Licensed Products; (c) to include valid
copyright notices on the Licensed Products, and preserve any copyright notices
which are included with, or in, the Example Code; (d) to comply with all the
other terms of this Licence; and (e) to ensure that any further redistribution
is limited to redistribution by either or both your customers and your
authorised distributors only as part of Licensed Products developed by you or
your permitted users and only for use on microprocessors manufactured or
simulated under licence from ARM and that your customers and authorised
distributors comply with the terms of this clause 1(ii).
2. RESTRICTIONS ON USE OF THE DELIVERABLES.
COPYING: You shall not use or copy the Deliverables except as expressly
authorised in this Licence. You may make one additional copy of the delivered
Deliverables media or image for backup or archival purposes.
PERMITTED USERS: The Deliverables shall be used only by your employees, or by
your bona fide sub-contractors for whose acts and omissions you hereby agree to
be responsible to ARM to the same extent as you are for any acts and omissions
of your employees, and provided always that such sub-contractors; (i) work only
onsite at your premises; (ii) comply with the terms of this Licence; (iii) are
contractually obligated to use the Deliverables only for your benefit, and (iv)
agree to assign all their work product and any rights they create therein in
the supply of such work to you. Only the single individual, company or other
legal entity to whom ARM is supplying this Licence may use the Deliverables.
Except as provided in this clause, you shall not allow third parties (including
but not limited to any subsidiary, parent or affiliated companies, or offsite
contractors you may have) to use the Deliverables unless ARM specifically agrees
otherwise with you on a case by case basis.
NO REMOTE USE: The Deliverables shall only be used onsite at your premises and
only for your benefit.
MULTIPLE VERSIONS: The media on which the Deliverables resides may contain more
than one version of the Deliverables, each of which is compatible with a
different operating system (such as Microsoft Windows XP Professional and Red
Hat Linux).
ACADEMIC OR EDUCATIONAL USERS ONLY: If you or your employer or institution paid
academic or educational pricing for the Deliverables, or the Deliverables are
identified as an academic or educational version (together "Academic Software"),
then notwithstanding anything else in this Licence, YOU AGREE TO USE THE
ACADEMIC SOFTWARE ONLY FOR ACADEMIC, NON-COMMERCIAL PURPOSES, AND ARM DOES NOT
GRANT YOU ANY RIGHTS TO DISTRIBUTE OR SUB-LICENSE ANY APPLICATIONS DEVELOPED
USING THE ACADEMIC SOFTWARE UNDER THIS LICENCE.
REVERSE ENGINEERING: Except to the extent that such activity is permitted by
applicable law you shall not reverse engineer, decompile or disassemble any of
the Deliverables. If the Deliverables were provided to you in Europe you shall
not reverse engineer, decompile or disassemble any of the Deliverables for the
purposes of error correction.
BENCHMARKING: This licence does not prevent you from using the Deliverables for
internal benchmarking purposes. However, you shall treat any and all
benchmarking data, and any other results of your use or testing of the
Deliverables which are indicative of performance, efficacy, reliability or
quality, as confidential information and you shall not disclose such information
to any third party without the express written permission of ARM.
RESTRICTIONS ON TRANSFER OF LICENSED RIGHTS: The rights granted to you under
this Licence may not be assigned, sublicensed or otherwise transferred by you
to any third party without the prior written consent of ARM. An assignment shall
be deemed to include, without limitation; (i) any transaction or series of
transactions whereby a third party acquires, directly or indirectly, the power
to control the management and policies of you, whether through the acquisition
of voting securities, by contract or otherwise; or (ii) the sale of more than
fifty percent (50%) of the your assets whether in a single transaction or series
of transactions. You shall not rent or lease the Deliverables. You shall not
share the Deliverables with contractors (except as identified in the PERMITTED
USERS clause above) or other third parties.
COPYRIGHT AND RESERVATION OF RIGHTS: The Deliverables are owned by ARM or its
licensors and are protected by copyright and other intellectual property laws
and international treaties. The Deliverables are licensed not sold. You acquire
no rights to the Deliverables other than as expressly provided by this Licence.
You shall not remove from the Deliverables any copyright notice or other notice
and shall ensure that any such notice is reproduced in any copies of the whole
or any part of the Deliverables made by you or your permitted users.
3. SUPPORT AND MAINTENANCE.
If you purchased the Deliverables directly from ARM, and you are not receiving
them as an update or upgrade or as Academic Software (defined in Clause 2), you
are entitled to reasonable support and maintenance for the Deliverables for the
period of one (1) year from the date of purchase. The support will be provided
on any version of the Deliverables which, at the date of your support request,
are either; (a) the current version made generally available by ARM; or (b) the
previous version made generally available by ARM at some time during the
previous ninety (90) days.
Support will be provided by telephone, email or other written format designated
by ARM, prioritised at ARMs discretion, and may not be used as a substitute for
training or as additional resource for your programming projects. Maintenance
will be provided in the form of upgrades, updates and patch releases to the
Deliverables as and when they are made generally available from ARM.
ARMs obligation under this Clause 3 is limited to the provision of support and
maintenance to you and ARM is under no obligation to provide any support and
maintenance to any third parties under this Licence. If you purchase support and
maintenance for additional years it will be provided pursuant to this Clause 3
and will be subject to the terms and conditions of this Licence.
If; (i) you obtained the Deliverables from an ARM authorised reseller or other
third party; (ii) Deliverables were provided free of charge or for evaluation;
or (iii) it is Academic Software, you are not entitled to any support for the
Deliverables from ARM, but ARM may, at its sole discretion provide limited
support to you. The vendor of the Deliverables may or may not offer support to
you for the Deliverables. Please refer to the Technical Support area of
http://www.arm.com for contact details for ARMs support service and (if
applicable) other authorised support channels. ARM shall be under no obligation
to provide support in respect of any modifications (where permitted) to the
Deliverables.
4. CONFIDENTIALITY.
You acknowledge that the Deliverables and any benchmarking data and related
information mentioned in Clause 2 contains trade secrets and confidential
material, and you agree to maintain all such information in confidence and
apply security measures no less stringent than the measures which you apply to
protect your own like information, but not less than a reasonable degree of
care, to prevent their unauthorised disclosure and use. Subject to any
restrictions imposed by applicable law, the period of confidentiality shall be
indefinite. You agree that you shall not use any such information other than in
normal use of the Deliverables under the licences granted in this Licence.
Notwithstanding the foregoing you may disclose the Deliverables identified in
Part C(i) of the Schedule to third parties solely in exercise of the licence
rights contained in Clause 1(i)(c) of this Licence.
5. LIMITED WARRANTIES.
For the period of ninety (90) days from the date of receipt by you of the
Deliverables, ARM warrants to you that (i) the media on which the Deliverables
are provided shall be free from defects in materials and workmanship under
normal use; and (ii) the Deliverables will perform substantially in accordance
with the accompanying documentation (if any). ARM's total liability and your
exclusive remedy for breach of these limited warranties shall be limited to ARM,
at ARM's option; (a) replacing the defective Deliverables; or (b) using
reasonable efforts to correct material, documented, reproducible defects in the
Deliverables and delivering such corrected Deliverables to you. Any replacement
Deliverables will be warranted for the remainder of the original warranty
period or thirty (30) days, whichever is the longer.
EXCEPT AS PROVIDED ABOVE, YOU AGREE THAT THE DELIVERABLES ARE LICENSED "AS IS",
AND THAT ARM EXPRESSLY DISCLAIMS ALL REPRESENTATIONS, WARRANTIES, CONDITIONS OR
OTHER TERMS, EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION THE
IMPLIED WARRANTIES OF NON- INFRINGEMENT, SATISFACTORY QUALITY, AND FITNESS FOR A
PARTICULAR PURPOSE.
YOU EXPRESSLY ASSUME ALL LIABILITIES AND RISKS, FOR USE OR OPERATION OF SOFTWARE
APPLICATIONS, INCLUDING WITHOUT LIMITATION, APPLICATIONS DESIGNED OR INTENDED
FOR MISSION CRITICAL APPLICATIONS, SUCH AS PACEMAKERS, WEAPONARY, AIRCRAFT
NAVIGATION, FACTORY CONTROL SYSTEMS, ETC. SHOULD THE DELIVERABLES PROVE
DEFECTIVE, YOU ASSUME THE ENTIRE COST OF ALL NECESSARY SERVICING, REPAIR OR
CORRECTION.
6. LIMITATION OF LIABILITY.
TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL ARM BE
LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES (INCLUDING
LOSS OF PROFITS) ARISING OUT OF THE USE OR INABILITY TO USE THE DELIVERABLES
WHETHER BASED ON A CLAIM UNDER CONTRACT, TORT OR OTHER LEGAL THEORY, EVEN IF ARM
WAS ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
ARM does not seek to limit or exclude liability for death or personal injury
arising from ARM's negligence or ARMs fraud and because some jurisdictions do
not permit the exclusion or limitation of liability for consequential or
incidental damages the above limitation relating to liability for consequential
damages may not apply to you.
NOTWITHSTANDING ANYTHING TO THE CONTRARY CONTAINED IN THIS LICENCE, THE MAXIMUM
LIABILITY OF ARM TO YOU IN AGGREGATE FOR ALL CLAIMS MADE AGAINST ARM IN CONTRACT
TORT OR OTHERWISE UNDER OR IN CONNECTION WITH THE SUBJECT MATTER OF THIS LICENCE
SHALL NOT EXCEED THE GREATER OF; (I) THE TOTAL OF SUMS PAID BY YOU TO ARM (IF
ANY) FOR THIS LICENCE; AND (II) $10 USD.
THE EXISTENCE OF MORE THAN ONE CLAIM WILL NOT ENLARGE OR EXTEND THE LIMIT.
7. THIRD PARTY RIGHTS.
The Separate Files are delivered subject to and your use is governed by their
own separate licence agreements. This Licence does not apply to such Separate
Files and they are not included in the term "Deliverables" under this Licence.
You agree to comply with all terms and conditions imposed on you in respect of
such Separate Files including those identified in the Schedule ("Third Party
Terms").
ARM HEREBY DISCLAIMS ANY AND ALL WARRANTIES EXPRESS OR IMPLIED FROM ANY THIRD
PARTIES REGARDING ANY SEPARATE FILES, ANY THIRD PARTY MATERIALS INCLUDED IN THE
DELIVERABLES, ANY THIRD PARTY MATERIALS FROM WHICH THE DELIVERABLES ARE DERIVED
(COLLECTIVELY "OTHER CODE"), AND THE USE OF ANY OR ALL THE OTHER CODE IN
CONNECTION WITH THE DELIVERABLES, INCLUDING (WITHOUT LIMITATION) ANY WARRANTIES
OF SATISFACTORY QUALITY OR FITNESS FOR A PARTICULAR PURPOSE.
NO THIRD PARTY LICENSORS OF OTHER CODE SHALL HAVE ANY LIABILITY FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING
WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND WHETHER MADE UNDER
CONTRACT, TORT OR OTHER LEGAL THEORY, ARISING IN ANY WAY OUT OF THE USE OR
DISTRIBUTION OF THE OTHER CODE OR THE EXERCISE OF ANY RIGHTS GRANTED UNDER
EITHER OR BOTH THIS LICENCE AND THE LEGAL TERMS APPLICABLE TO ANY SEPARATE
FILES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
8. GOVERNMENT END USERS.
US Government Restrictions: Use, duplication, reproduction, release,
modification, disclosure or transfer of the Deliverables is restricted in
accordance with the terms of this Licence.
9. TERM AND TERMINATION.
This Licence shall remain in force until terminated by you or by ARM. Without
prejudice to any of its other rights if you are in breach of any of the terms
and conditions of this Licence then ARM may terminate this Licence immediately
upon giving written notice to you. You may terminate this Licence at any time.
Upon termination of this Licence by you or by ARM you shall stop using the
Deliverables and confidential information and destroy all copies of the
Deliverables and confidential information in your possession together with all
documentation and related materials. Notwithstanding the foregoing, except where
ARM has terminated this Licence for your breach, your rights to distribute the
Example Code as part of Licensed Products developed prior to termination shall
survive termination of this Licence, subject to the terms of this Licence. The
provisions of Clauses 4, 6, 7, 8, 9 and 10 shall survive termination of this
Licence.
10. GENERAL.
This Licence is governed by English Law. Except where ARM agrees otherwise in;
(i) a written contract signed by you and ARM; or (ii) a written contract
provided by ARM and accepted by you, this is the only agreement between you and
ARM relating to the Deliverables and it may only be modified by written
agreement between you and ARM. This Licence may not be modified by purchase
orders, advertising or other representation by any person. If any clause or
sentence in this Licence is held by a court of law to be illegal or
unenforceable the remaining provisions of this Licence shall not be affected
thereby. The failure by ARM to enforce any of the provisions of this Licence,
unless waived in writing, shall not constitute a waiver of ARM's rights to
enforce such provision or any other provision of this Licence in the future.
The Deliverables provided under this Licence are subject to U.S. export control
laws, including the U.S. Export Administration Act and its associated
regulations, and may be subject to export or import regulations in other
countries. You agree to comply fully with all laws and regulations of the United
States and other countries ("Export Laws") to assure that the Deliverables, are
not (1) exported, directly or indirectly, in violation of Export Laws, either to
any countries that are subject to U.S.A. export restrictions or to any end user
who has been prohibited from participating in the U.S.A. export transactions by
any federal agency of the U.S.A. government; or (2) intended to be used for any
purpose prohibited by Export Laws, including, without limitation, nuclear,
chemical, or biological weapons proliferation.
To the extent that the provisions contained in this Licence conflict with any
provisions of any other licence you have entered with ARM governing the
Deliverables the provisions contained in this Licence shall prevail over and
shall supersede any such conflicting provisions.
SCHEDULE
Part A
Hardware Binaries:
FPGA bitstream file for any or all of the Hardware Source identified below in
this Part A
Software Binaries:
Motherboard configuration controller
Daughterboard configuration controller
Daughterboard Application note SelfTest
SCP firmware
Mali GPU driver
Documentation:
Documentation, provided as PDF
Hardware Source
Hardware netlists of the ARM CoreLink peripheral technology and components known as TLX-400, NIC-400, and PL330
Part B
Wrapper:
Application Note wrapper file provided as hardware source files and netlists.
Part C: Example Code
(i) Platform specific libraries and source code.
(ii) ARM source code of Application note SelfTest.
Part D: Separate Files
A. UEFI firmware, including drivers for third party components licensed to
you under BSD 3-Clause.
B. Linux kernel licensed to you under the GNU General Public License version
2.0
To the extent that ARM is obliged to do so, ARM hereby offers to supply the
files which are subject to the GNU General Public Licence version 2 (identified
above), in source code form, subject to the terms of the GNU General Public
License version 2, upon request. This offer is valid for three (3) years from
the date of your acceptance of this Licence.
C. ARM Trusted Firmware licensed to you under BSD 3-Clause.
/end
ARM contract references: LES-PRE-20435 JUNO ARM DEVELOPMENT PLATFORM DELIVERABLES

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@@ -1,26 +0,0 @@
#/** @file
#
# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
# Copyright (c) 2016, Linaro Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = GetInfoFromBmc
FILE_GUID = 43B59C81-9C5F-4021-B0F2-947DB839B781
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = GetBmcInfoDriverEntry
[Binaries]
PE32|GetInfoFromBmc.efi|*
DXE_DEPEX|GetInfoFromBmc.depex|*

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@@ -1,32 +0,0 @@
#/** @file
#
# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
# Copyright (c) 2016, Linaro Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = IpmiInterfacePei
FILE_GUID = 269702AF-8004-4570-A08E-00762AE65D15
MODULE_TYPE = PEIM
VERSION_STRING = 1.0
ENTRY_POINT = IpmiInterfacePeiEntry
[Sources]
[Binaries.AARCH64]
TE|IpmiInterfacePei.efi|*
[Depex]
TRUE

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@@ -1,28 +0,0 @@
#/** @file
#
# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
# Copyright (c) 2016, Linaro Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = IpmiInterfaceDxe
FILE_GUID = EF5483F8-68AD-4D71-9A23-674D2E9C013E
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
[Binaries.common]
PE32|IpmiInterfaceDxe.efi|*
DXE_DEPEX|IpmiInterfaceDxe.depex|*

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@@ -1,27 +0,0 @@
#/** @file
#
# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
# Copyright (c) 2016, Linaro Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = IpmiMiscOp
FILE_GUID = EC68451C-6D10-4ba2-9862-D27D4D6090DB
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = IpmiMiscOpEntry
[Binaries]
PE32|IpmiMiscOp.efi|*
DXE_DEPEX|IpmiMiscOpDxe.depex|*

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@@ -1,27 +0,0 @@
#/** @file
#
# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
# Copyright (c) 2016, Linaro Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = IpmiWatchdogDxe
FILE_GUID = 7C7ACA9F-DB25-43FB-A479-1B6E42F38792
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = InitializeWatchdogDxeEntry
[Binaries]
PE32|IpmiWatchdogDxe.efi|*
DXE_DEPEX|IpmiWatchdogDxe.depex|*

View File

@@ -1,24 +0,0 @@
#/** @file
#
# Copyright (c) 2017, Hisilicon Limited. All rights reserved.
# Copyright (c) 2017, Linaro Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
[Defines]
INF_VERSION = 0x00010019
BASE_NAME = SnpPV600Dxe
FILE_GUID = 3247F15F-3612-4803-BD4E-4104D7EF944A
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
[Binaries.AARCH64]
PE32|SnpPV600Dxe.efi|*

View File

@@ -1,26 +0,0 @@
#/** @file
#
# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
# Copyright (c) 2016, Linaro Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
[defines]
INF_VERSION = 0x00010005
BASE_NAME = NativeOhci
FILE_GUID = 043D0B5E-DAC1-463a-85BA-2CEDC33A8C4F
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
[Binaries]
PE32|NativeOhci.efi|*

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